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Pablo Trujillo controlpaths

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controlpaths / zynq_shared_memory.tcl
Created March 3, 2020 20:23
Example script for generate a block design.
## Shared memory between microblaze and hdl for share parameters.
## Digital tav
set projectDir ../project
## Delete log and journal
file delete {*}[glob vivado*.backup.jou]
file delete {*}[glob vivado*.backup.log]
file delete -force .Xil/
@controlpaths
controlpaths / clock_forwarding_example.v
Created March 21, 2020 11:07
Clock forwarding example for Xilinx 7 series
/* Clock forwarding for DAC. Single anded clock */
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
)ODDR_CLKDAC(
.Q(o_dac_clkout),
.C(clk100mhz),
.CE(1'b1),
.D1(1'b0),
@controlpaths
controlpaths / axi_fir8_coeff.py
Created March 31, 2020 18:26
Python code for 8 order FIR configuration
from pynq import Overlay
import numpy as np
from scipy import signal
import matplotlib.pyplot as plt
from pynq import MMIO
# Configure the overlay
overlay = Overlay("ultra96_bd_fir.bit")
# Define the IP addresses and definition
@controlpaths
controlpaths / buck_model.m
Created April 26, 2020 11:31
Script for Buck model.
## Buck model
clc
close all
clear all
pkg load control
s = tf('s');
fs = 1e6;
@controlpaths
controlpaths / mv_avg_filter_8_v1_0.v
Last active August 29, 2020 16:13
8th order moving average filter with 14 bits width.
/**
Module name: mv_avg_filter_8_v1_0
Author: P Trujillo (pablo@controlpaths.com)
Date: Aug 2020
Description: 8th order moving average filter
Revision: 1.0 Module created.
**/
module mv_avg_filter_8_v1_0 (
input clk,
@controlpaths
controlpaths / main_dma_fft.c
Created October 11, 2020 10:27
Code to manage 2 DMA for FFT acceleration.
/* Project FFT through DMA */
/* DMA libraries */
#include "xaxidma.h"
#include "xparameters.h"
#include "xdebug.h"
/* Math library */
#include "math.h"
@controlpaths
controlpaths / decimate_x4_v1_0.v
Last active November 22, 2020 16:43
Decimate module by 4
/**
Module name: decimate_x4_v1_0
Author: P Trujillo (pablo@controlpaths.com)
Date: Nov 2020
Description: Module to decimate by 4 increasing 1 bit resolution.
Revision: 1.0 Module created.
**/
module decimate_x4_v1_0 #(
parameter pw_input_width = 14
@controlpaths
controlpaths / image_generator.m
Created January 20, 2021 21:24
MATLAB script to check how image frequencies are generated.
%% Image frequencies
clear all
close all
clc
nSamples = 10;
f0 = 1;
% Angle generate