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corecode/gist:7dd007a1c343b6666118b488f005a3e9

Created February 25, 2019 10:26
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gistfile1.txt
Project Directory is /home/corecode/devel/forth-cpu/icecube/test2
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/synpwrap/synpwrap" -prj "test2_syn.prj" -log "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.srr"
Running in Lattice mode
Starting: /opt/lscc/iCEcube2.2017.08/synpbase/linux_a_64/mbin/synbatch
Install: /opt/lscc/iCEcube2.2017.08/synpbase
Hostname: ernest
Date: Sun Feb 24 22:21:58 2019
Version: L-2016.09L+ice40
Arguments: -product synplify_pro -batch test2_syn.prj
ProductType: synplify_pro
log file: "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.srr"
Running: test2_Implmnt in foreground
Running test2_syn|test2_Implmnt
Running: compile (Compile) on test2_syn|test2_Implmnt
# Sun Feb 24 22:21:58 2019
Running: compile_flow (Compile Process) on test2_syn|test2_Implmnt
# Sun Feb 24 22:21:58 2019
Running: compiler (Compile Input) on test2_syn|test2_Implmnt
# Sun Feb 24 22:21:58 2019
Copied /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/synwork/test2_comp.srs to /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.srs
compiler completed
# Sun Feb 24 22:21:59 2019
Return Code: 0
Run Time:00h:00m:01s
Running: multi_srs_gen (Multi-srs Generator) on test2_syn|test2_Implmnt
# Sun Feb 24 22:21:59 2019
multi_srs_gen completed
# Sun Feb 24 22:21:59 2019
Return Code: 0
Run Time:00h:00m:00s
Copied /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/synwork/test2_mult.srs to /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.srs
Complete: Compile Process on test2_syn|test2_Implmnt
Running: premap (Pre-mapping) on test2_syn|test2_Implmnt
# Sun Feb 24 22:21:59 2019
premap completed with warnings
# Sun Feb 24 22:22:00 2019
Return Code: 1
Run Time:00h:00m:01s
Complete: Compile on test2_syn|test2_Implmnt
Running: map (Map) on test2_syn|test2_Implmnt
# Sun Feb 24 22:22:00 2019
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on test2_syn|test2_Implmnt
# Sun Feb 24 22:22:00 2019
Copied /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/synwork/test2_m.srm to /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.srm
fpga_mapper completed with warnings
# Sun Feb 24 22:22:02 2019
Return Code: 1
Run Time:00h:00m:02s
Complete: Map on test2_syn|test2_Implmnt
Complete: Logic Synthesis on test2_syn|test2_Implmnt
exit status=0
exit status=0
Copyright (C) 1992-2014 Lattice Semiconductor Corporation. All rights reserved.
Child process exit with 0.
==contents of /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.srr
#Build: Synplify Pro L-2016.09L+ice40, Build 077R, Dec 2 2016
#install: /opt/lscc/iCEcube2.2017.08/synpbase
#OS: Linux
#Hostname: ernest
# Sun Feb 24 22:21:58 2019
#Implementation: test2_Implmnt
Synopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec 5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Synopsys Verilog Compiler, version comp2016q3p1, Build 141R, built Dec 5 2016
@N|Running in 64-bit mode
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Running on host :ernest
@I::"/opt/lscc/iCEcube2.2017.08/synpbase/lib/generic/sb_ice40.v" (library work)
@I::"/opt/lscc/iCEcube2.2017.08/synpbase/lib/vlog/hypermods.v" (library __hyper__lib__)
@I::"/opt/lscc/iCEcube2.2017.08/synpbase/lib/vlog/umr_capim.v" (library snps_haps)
@I::"/opt/lscc/iCEcube2.2017.08/synpbase/lib/vlog/scemi_objects.v" (library snps_haps)
@I::"/opt/lscc/iCEcube2.2017.08/synpbase/lib/vlog/scemi_pipes.svh" (library snps_haps)
@I::"/home/corecode/devel/forth-cpu/rtl/alu.v" (library work)
@I::"/home/corecode/devel/forth-cpu/rtl/cpu.v" (library work)
@I::"/home/corecode/devel/forth-cpu/rtl/cpu_top.v" (library work)
@I::"/home/corecode/devel/forth-cpu/rtl/spi.v" (library work)
@I::"/home/corecode/devel/forth-cpu/rtl/membus.v" (library work)
@I::"/home/corecode/devel/forth-cpu/rtl/ip.v" (library work)
@I::"/home/corecode/devel/forth-cpu/rtl/gpio.v" (library work)
@I::"/home/corecode/devel/forth-cpu/rtl/top_u4k.v" (library work)
@I::"/home/corecode/devel/forth-cpu/rtl/top.v" (library work)
@I::"/home/corecode/devel/forth-cpu/rtl/stack.v" (library work)
Verilog syntax check successful!
Selecting top level module top_u4k
@N: CG364 :"/opt/lscc/iCEcube2.2017.08/synpbase/lib/generic/sb_ice40.v":4020:7:4020:14|Synthesizing module SB_HFOSC in library work.
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/spi.v":3:7:3:9|Synthesizing module spi in library work.
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":174:7:174:16|Synthesizing module cpu_decode in library work.
width=32'b00000000000000000000000000010000
idata_width=32'b00000000000000000000000000010000
iaddr_width=32'b00000000000000000000000000001000
Generated name = cpu_decode_16s_16s_8s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/alu.v":3:7:3:17|Synthesizing module alu_reg_sel in library work.
width=32'b00000000000000000000000000010000
Generated name = alu_reg_sel_16s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/alu.v":23:7:23:15|Synthesizing module alu_logic in library work.
width=32'b00000000000000000000000000010000
Generated name = alu_logic_16s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/alu.v":45:7:45:15|Synthesizing module alu_adder in library work.
width=32'b00000000000000000000000000010000
Generated name = alu_adder_16s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/alu.v":66:7:66:13|Synthesizing module alu_mux in library work.
width=32'b00000000000000000000000000010000
Generated name = alu_mux_16s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/alu.v":86:7:86:13|Synthesizing module tos_mux in library work.
width=32'b00000000000000000000000000010000
Generated name = tos_mux_16s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/alu.v":114:7:114:14|Synthesizing module tos_comb in library work.
width=32'b00000000000000000000000000010000
Generated name = tos_comb_16s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/alu.v":198:7:198:13|Synthesizing module tos_mem in library work.
width=32'b00000000000000000000000000010000
daddr_width=32'b00000000000000000000000000001001
Generated name = tos_mem_16s_9s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/stack.v":3:7:3:13|Synthesizing module sp_comb in library work.
saddr_width=32'b00000000000000000000000000001000
Generated name = sp_comb_8s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/stack.v":56:7:56:11|Synthesizing module stack in library work.
saddr_width=32'b00000000000000000000000000001000
width=32'b00000000000000000000000000010000
Generated name = stack_8s_16s
@N: CL134 :"/home/corecode/devel/forth-cpu/rtl/stack.v":93:0:93:5|Found RAM stack_mem, depth=256, width=16
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/ip.v":3:7:3:13|Synthesizing module ip_comb in library work.
iaddr_width=32'b00000000000000000000000000001000
Generated name = ip_comb_8s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":3:7:3:17|Synthesizing module cpu_execute in library work.
width=32'b00000000000000000000000000010000
iaddr_width=32'b00000000000000000000000000001000
daddr_width=32'b00000000000000000000000000001001
psaddr_width=32'b00000000000000000000000000001000
rsaddr_width=32'b00000000000000000000000000001000
Generated name = cpu_execute_16s_8s_9s_8s_8s
@W: CL207 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":155:0:155:5|All reachable assignments to wait_state assign 0, register removed by optimization.
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":421:7:421:9|Synthesizing module cpu in library work.
width=32'b00000000000000000000000000010000
idata_width=32'b00000000000000000000000000010000
iaddr_width=32'b00000000000000000000000000001000
daddr_width=32'b00000000000000000000000000001001
psaddr_width=32'b00000000000000000000000000001000
rsaddr_width=32'b00000000000000000000000000001000
Generated name = cpu_16s_16s_8s_9s_8s_8s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/membus.v":75:7:75:9|Synthesizing module mem in library work.
width=32'b00000000000000000000000000010000
addr_width=32'b00000000000000000000000000001000
Generated name = mem_16s_8s
@N: CL134 :"/home/corecode/devel/forth-cpu/rtl/membus.v":92:0:92:5|Found RAM memory, depth=256, width=16
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/gpio.v":3:7:3:10|Synthesizing module gpio in library work.
npins=32'b00000000000000000000000000000101
Generated name = gpio_5s
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/membus.v":3:7:3:12|Synthesizing module membus in library work.
width=32'b00000000000000000000000000010000
npins=32'b00000000000000000000000000000101
Generated name = membus_16s_5s
@W: CS263 :"/home/corecode/devel/forth-cpu/rtl/membus.v":61:16:61:29|Port-width mismatch for port data_read. The port definition is 5 bits, but the actual port connection bit width is 16. Adjust either the definition or the instantiation of this port.
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/cpu_top.v":3:7:3:13|Synthesizing module cpu_top in library work.
npins=32'b00000000000000000000000000000101
width=32'b00000000000000000000000000010000
iaddr_width=32'b00000000000000000000000000001000
daddr_width=32'b00000000000000000000000000001001
Generated name = cpu_top_5s_16s_8s_9s
@N: CL134 :"/home/corecode/devel/forth-cpu/rtl/cpu_top.v":32:0:32:5|Found RAM iram, depth=256, width=16
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/top.v":3:7:3:9|Synthesizing module top in library work.
npins=32'b00000000000000000000000000000101
iaddr_width=32'b00000000000000000000000000001000
width=32'b00000000000000000000000000010000
Generated name = top_5s_8s_16s
@W: CG360 :"/home/corecode/devel/forth-cpu/rtl/top.v":25:25:25:37|Removing wire transfer_done, as there is no assignment to it.
@N: CG364 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":3:7:3:13|Synthesizing module top_u4k in library work.
@W: CG532 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":25:0:25:6|Within an initial block, only Verilog force statements and memory $readmemh/$readmemb initialization statements are recognized, and all other content is ignored.
@W: CS263 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":18:13:18:13|Port-width mismatch for port CLKHFPU. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":17:13:17:13|Port-width mismatch for port CLKHFEN. The port definition is 1 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@N: CL189 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":28:0:28:5|Register bit reset_counter[7] is always 1.
@W: CL260 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":28:0:28:5|Pruning register bit 7 of reset_counter[7:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL189 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":28:0:28:5|Register bit reset_counter[6] is always 1.
@W: CL260 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":28:0:28:5|Pruning register bit 6 of reset_counter[6:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL189 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":28:0:28:5|Register bit reset_counter[5] is always 1.
@W: CL260 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":28:0:28:5|Pruning register bit 5 of reset_counter[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL189 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":28:0:28:5|Register bit reset_counter[4] is always 1.
@W: CL260 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":28:0:28:5|Pruning register bit 4 of reset_counter[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL159 :"/home/corecode/devel/forth-cpu/rtl/membus.v":82:24:82:28|Input reset is unused.
@W: CL247 :"/home/corecode/devel/forth-cpu/rtl/alu.v":72:24:72:26|Input port bit 0 of TOS[15:0] is unused
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Sun Feb 24 22:21:58 2019
###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec 5 2016
@N|Running in 64-bit mode
@N: NF107 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":3:7:3:13|Selected library: work cell: top_u4k view verilog as top level
@N: NF107 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":3:7:3:13|Selected library: work cell: top_u4k view verilog as top level
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Sun Feb 24 22:21:58 2019
###########################################################]
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Sun Feb 24 22:21:58 2019
###########################################################]
Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec 5 2016
@N|Running in 64-bit mode
@N: NF107 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":3:7:3:13|Selected library: work cell: top_u4k view verilog as top level
@N: NF107 :"/home/corecode/devel/forth-cpu/rtl/top_u4k.v":3:7:3:13|Selected library: work cell: top_u4k view verilog as top level
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 69MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Sun Feb 24 22:21:59 2019
###########################################################]
Pre-mapping Report
# Sun Feb 24 22:21:59 2019
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1612R, Built Dec 5 2016 09:30:53
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
@A: MF827 |No constraint file specified.
@L: /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2_scck.rpt
Printing clock summary report in "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2_scck.rpt" file
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB)
@N: BN362 :"/home/corecode/devel/forth-cpu/rtl/spi.v":83:0:83:5|Removing sequential instance transfer_done (in view: work.spi(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
syn_allowed_resources : blockrams=20 set on top level netlist top_u4k
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB)
Clock Summary
*****************
Start Requested Requested Clock Clock Clock
Clock Frequency Period Type Group Load
-------------------------------------------------------------------------------------------------------
top_u4k|clk_inferred_clock 24.0 MHz 41.660 inferred Autoconstr_clkgroup_0 195
=======================================================================================================
@W: MT529 :"/home/corecode/devel/forth-cpu/rtl/spi.v":57:0:57:5|Found inferred clock top_u4k|clk_inferred_clock which controls 195 sequential elements including top.spi.numbits[3:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.sap.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 134MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 134MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Feb 24 22:22:00 2019
###########################################################]
Map & Optimize Report
# Sun Feb 24 22:22:00 2019
Synopsys Lattice Technology Mapper, Version maplat, Build 1612R, Built Dec 5 2016 09:30:53
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 100MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)
Available hyper_sources - for debug and ip models
None Found
@N: MT206 |Auto Constrain mode is enabled
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM logic_op_1[1:0] (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM zero_arg_1 (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM reg_sel_1 (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM inc_1 (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM adder_sel_1 (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM logic_op_1[1:0] (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|Found ROM .delname. (in view: work.cpu_decode_16s_16s_8s(verilog)) with 13 words by 2 bits.
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM zero_arg_1 (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|Found ROM .delname. (in view: work.cpu_decode_16s_16s_8s(verilog)) with 13 words by 1 bit.
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM reg_sel_1 (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|Found ROM .delname. (in view: work.cpu_decode_16s_16s_8s(verilog)) with 13 words by 1 bit.
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM inc_1 (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|Found ROM .delname. (in view: work.cpu_decode_16s_16s_8s(verilog)) with 13 words by 1 bit.
@W: FA239 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|ROM adder_sel_1 (in view: work.cpu_decode_16s_16s_8s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"/home/corecode/devel/forth-cpu/rtl/cpu.v":362:3:362:6|Found ROM .delname. (in view: work.cpu_decode_16s_16s_8s(verilog)) with 13 words by 1 bit.
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)
@W: FX107 :"/home/corecode/devel/forth-cpu/rtl/membus.v":92:0:92:5|RAM cpu_top.membus.mem.memory[15:0] (in view: work.top_5s_8s_16s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/home/corecode/devel/forth-cpu/rtl/cpu_top.v":32:0:32:5|RAM cpu_top.iram[15:0] (in view: work.top_5s_8s_16s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N: MO231 :"/home/corecode/devel/forth-cpu/rtl/top.v":30:0:30:5|Found counter in view:work.top_5s_8s_16s(verilog) instance iaddr_write[7:0]
@W: FX107 :"/home/corecode/devel/forth-cpu/rtl/stack.v":93:0:93:5|RAM rstack.stack_mem[15:0] (in view: work.cpu_execute_16s_8s_9s_8s_8s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"/home/corecode/devel/forth-cpu/rtl/stack.v":93:0:93:5|RAM pstack.stack_mem[15:0] (in view: work.cpu_execute_16s_8s_9s_8s_8s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 133MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 147MB peak: 149MB)
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 149MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 149MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 149MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 149MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 149MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 149MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 155MB peak: 158MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 27.84ns 349 / 99
@N: FX1017 :|SB_GB inserted on the net top.un1_reset_0_i.
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 156MB peak: 158MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 156MB peak: 158MB)
@S |Clock Optimization Summary
#### START OF CLOCK OPTIMIZATION REPORT #####[
0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 107 clock pin(s) of sequential element(s)
0 instances converted, 107 sequential instances remain driven by gated/generated clocks
================================================================================================= Gated/Generated Clocks ==================================================================================================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001 osc SB_HFOSC 107 reset_counter[0] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
===========================================================================================================================================================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######]
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 129MB peak: 158MB)
Writing Analyst data base /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/synwork/test2_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 158MB)
Writing EDIF Netlist and constraint files
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF
@N: FX1056 |Writing EDF file: /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.edf
L-2016.09L+ice40
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 155MB peak: 158MB)
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 158MB)
@W: MT420 |Found inferred clock top_u4k|clk_inferred_clock with period 41.66ns. Please declare a user-defined clock on object "n:clk"
##### START OF TIMING REPORT #####[
# Timing Report written on Sun Feb 24 22:22:02 2019
#
Top view: top_u4k
Requested Frequency: 24.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 17.403
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------------------
top_u4k|clk_inferred_clock 24.0 MHz 41.2 MHz 41.660 24.257 17.403 inferred Autoconstr_clkgroup_0
====================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-----------------------------------------------------------------------------------------------------------------------------------------------
top_u4k|clk_inferred_clock top_u4k|clk_inferred_clock | 41.660 17.403 | No paths - | No paths - | No paths -
===============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: top_u4k|clk_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------------------------------------------
top.cpu_top.membus.mem.memory_memory_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RDATA[3] mem_data_read[3] 0.920 17.403
top.cpu_top.membus.gpio.data_read[3] top_u4k|clk_inferred_clock SB_DFF Q gpio_data_read[3] 0.796 18.156
top.cpu_top.membus.mem_sel_read top_u4k|clk_inferred_clock SB_DFF Q mem_sel_read 0.796 18.187
top.cpu_top.membus.mem.memory_memory_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RDATA[2] mem_data_read[2] 0.920 19.239
top.cpu_top.membus.mem.memory_memory_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RDATA[0] mem_data_read[0] 0.920 19.332
top.cpu_top.membus.mem.memory_memory_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RDATA[1] mem_data_read[1] 0.920 19.342
top.cpu_top.membus.mem.memory_memory_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RDATA[4] mem_data_read[4] 0.920 19.363
top.cpu_top.membus.gpio.data_read[2] top_u4k|clk_inferred_clock SB_DFF Q gpio_data_read[2] 0.796 19.950
top.cpu_top.cpu.cpu_execute.tos_mem.mem_read_r top_u4k|clk_inferred_clock SB_DFFR Q mem_read_r 0.796 20.043
top.cpu_top.membus.gpio.data_read[0] top_u4k|clk_inferred_clock SB_DFF Q gpio_data_read[0] 0.796 20.043
========================================================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------------------------------------
top.cpu_top.iram_iram_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RADDR[1] iaddr[1] 41.360 17.403
top.cpu_top.iram_iram_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RADDR[2] iaddr[2] 41.360 17.403
top.cpu_top.iram_iram_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RADDR[3] iaddr[3] 41.360 17.403
top.cpu_top.iram_iram_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RADDR[4] iaddr[4] 41.360 17.403
top.cpu_top.iram_iram_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RADDR[5] iaddr[5] 41.360 17.403
top.cpu_top.iram_iram_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RADDR[6] iaddr[6] 41.360 17.403
top.cpu_top.iram_iram_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RADDR[7] iaddr[7] 41.360 17.403
top.cpu_top.iram_iram_0_0 top_u4k|clk_inferred_clock SB_RAM256x16 RADDR[0] iaddr[0] 41.360 19.394
top.cpu_top.cpu.cpu_execute.IP[1] top_u4k|clk_inferred_clock SB_DFFR D ip_result[1] 41.505 22.716
top.cpu_top.cpu.cpu_execute.IP[2] top_u4k|clk_inferred_clock SB_DFFR D ip_result[2] 41.505 22.716
=======================================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 41.660
- Setup time: 0.300
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 41.360
- Propagation time: 23.958
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 17.403
Number of logic level(s): 9
Starting point: top.cpu_top.membus.mem.memory_memory_0_0 / RDATA[3]
Ending point: top.cpu_top.iram_iram_0_0 / RADDR[2]
The start point is clocked by top_u4k|clk_inferred_clock [rising] on pin RCLK
The end point is clocked by top_u4k|clk_inferred_clock [rising] on pin RCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------------------------------------
top.cpu_top.membus.mem.memory_memory_0_0 SB_RAM256x16 RDATA[3] Out 0.920 0.920 -
mem_data_read[3] Net - - 2.259 - 1
top.cpu_top.membus.mem.memory_memory_0_0_RNIMSB11 SB_LUT4 I1 In - 3.179 -
top.cpu_top.membus.mem.memory_memory_0_0_RNIMSB11 SB_LUT4 O Out 0.558 3.737 -
dQ[3] Net - - 1.371 - 1
top.cpu_top.cpu.cpu_execute.tos_mem.TOS_r_esr_RNIERFG1[3] SB_LUT4 I2 In - 5.108 -
top.cpu_top.cpu.cpu_execute.tos_mem.TOS_r_esr_RNIERFG1[3] SB_LUT4 O Out 0.517 5.625 -
daddr[3] Net - - 1.371 - 9
top.cpu_top.cpu.cpu_execute.tos_mem.TOS_r_esr_RNIUOV03[4] SB_LUT4 I0 In - 6.996 -
top.cpu_top.cpu.cpu_execute.tos_mem.TOS_r_esr_RNIUOV03[4] SB_LUT4 O Out 0.661 7.657 -
un1_w_strobe_1_2 Net - - 1.371 - 2
top.cpu_top.cpu.cpu_execute.tos_mem.TOS_r_esr_RNIG5V16[4] SB_LUT4 I2 In - 9.028 -
top.cpu_top.cpu.cpu_execute.tos_mem.TOS_r_esr_RNIG5V16[4] SB_LUT4 O Out 0.558 9.586 -
TOS_is_zero_9 Net - - 1.371 - 1
top.cpu_top.cpu.cpu_execute.tos_mem.TOS_r_esr_RNIERD4K[4] SB_LUT4 I3 In - 10.957 -
top.cpu_top.cpu.cpu_execute.tos_mem.TOS_r_esr_RNIERD4K[4] SB_LUT4 O Out 0.465 11.423 -
TOS_is_zero Net - - 1.371 - 2
top.cpu_top.cpu.cpu_execute.ip_comb.un1_ip_skip SB_LUT4 I0 In - 12.793 -
top.cpu_top.cpu.cpu_execute.ip_comb.un1_ip_skip SB_LUT4 O Out 0.569 13.362 -
un1_ip_skip Net - - 1.371 - 1
top.cpu_top.cpu.cpu_execute.ip_comb.ip_result_sn.m2 SB_LUT4 I1 In - 14.733 -
top.cpu_top.cpu.cpu_execute.ip_comb.ip_result_sn.m2 SB_LUT4 O Out 0.589 15.322 -
N_5_mux Net - - 1.371 - 9
top.cpu_top.cpu.cpu_execute.ip_comb.ip_inc_cry_1_c_RNILJ2GO SB_LUT4 I1 In - 16.693 -
top.cpu_top.cpu.cpu_execute.ip_comb.ip_inc_cry_1_c_RNILJ2GO SB_LUT4 O Out 0.589 17.282 -
ip_result[2] Net - - 1.371 - 2
top.cpu_top.cpu.cpu_execute.IP_RNI7GO6P[2] SB_LUT4 I1 In - 18.653 -
top.cpu_top.cpu.cpu_execute.IP_RNI7GO6P[2] SB_LUT4 O Out 0.589 19.243 -
iaddr[2] Net - - 4.715 - 1
top.cpu_top.iram_iram_0_0 SB_RAM256x16 RADDR[2] In - 23.958 -
======================================================================================================================================
Total path delay (propagation time + setup) of 24.257 is 6.315(26.0%) logic and 17.942(74.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 158MB)
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 158MB)
---------------------------------------
Resource Usage Report for top_u4k
Mapping to part: ice5lp4ksg48
Cell usage:
GND 21 uses
SB_CARRY 45 uses
SB_DFF 22 uses
SB_DFFE 24 uses
SB_DFFER 5 uses
SB_DFFES 5 uses
SB_DFFESR 30 uses
SB_DFFR 11 uses
SB_DFFSR 2 uses
SB_GB 1 use
SB_HFOSC 1 use
SB_RAM256x16 4 uses
VCC 21 uses
SB_LUT4 383 uses
I/O ports: 8
I/O primitives: 8
SB_IO 8 uses
I/O Register bits: 0
Register bits not including I/Os: 99 (2%)
RAM/ROM usage summary
Block Rams : 4 of 20 (20%)
Total load per clock:
top_u4k|clk_inferred_clock: 107
@S |Mapping Summary:
Total LUTs: 383 (10%)
Distribution of All Consumed LUTs = LUT4
Distribution of All Consumed Luts 383 = 383
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 29MB peak: 158MB)
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Sun Feb 24 22:22:02 2019
###########################################################]
Synthesis exit by 0.
Current Implementation test2_Implmnt its sbt path: /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt
Synthesis succeeded.
Synthesis runtime 4 seconds
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/edifparser" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.edf /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ipfiles/iCE5LP/rgbsoft.edf " "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist" "-pSG48" -c --devicename iCE5LP4K
Lattice Semiconductor Corporation Edif Parser
Release: 2017.08.27940
Build Date: Sep 12 2017 08:01:35
Parsing edif file: /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.edf...
Parsing edif file: /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ipfiles/iCE5LP/rgbsoft.edf...
start to read sdc/scf file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.scf
sdc_reader OK /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/test2.scf
SB_RAM SB_RAM256x16 SB_RAM40_4K
Warning: property ROUTE_THROUGH_FABRIC doesn't exist at instance osc. default value (0) is added.
Stored edif netlist at /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k...
Warning: The terminal top.cpu_top.membus.mem.memory_memory_0_0:RCLKE is driven by default driver : VCC, Disconnecting it.
Warning: The terminal top.cpu_top.cpu.cpu_execute.rstack.stack_mem_stack_mem_0_0:RCLKE is driven by default driver : VCC, Disconnecting it.
Warning: The terminal top.cpu_top.cpu.cpu_execute.pstack.stack_mem_stack_mem_0_0:RCLKE is driven by default driver : VCC, Disconnecting it.
Warning: The terminal top.cpu_top.iram_iram_0_0:RCLKE is driven by default driver : VCC, Disconnecting it.
write Timing Constraint to /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc
EDIF Parser succeeded
Top module is: top_u4k
EDF Parser run-time: 1 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtplacer" --des-lib "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer" --device-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --package SG48 --deviceMarketName iCE5LP4K --sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc" --lib-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib" --effort_level std --out-sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc"
Executing : /opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtplacer --des-lib /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k --outdir /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer --device-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev --package SG48 --deviceMarketName iCE5LP4K --sdc-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc --lib-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib --effort_level std --out-sdc-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc
Lattice Semiconductor Corporation Placer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:22:02
I2004: Option and Settings Summary
=============================================================
Device file - /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev
Package - SG48
Design database - /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k
SDC file - /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc
Output directory - /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer
Timing library - /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib
Effort level - std
I2050: Starting reading inputs for placer
=============================================================
I2100: Reading design library: /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k/BFPGA_DESIGN_ep
I2065: Reading device file : /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev
I2051: Reading of inputs for placer completed successfully
I2053: Starting placement of the design
=============================================================
Input Design Statistics
Number of LUTs : 383
Number of DFFs : 99
Number of DFFs packed to IO : 0
Number of Carrys : 45
Number of RAMs : 4
Number of ROMs : 0
Number of IOs : 8
Number of GBIOs : 0
Number of GBs : 1
Number of WarmBoot : 0
Number of PLLs : 0
Number of I2Cs : 0
Number of SPIs : 0
Number of DSPs : 0
Number of SBIOODs : 0
Number of LEDDRVs : 0
Number of RGBDRVs : 0
Number of LEDDIPs : 0
Number of IRDRVs : 0
Number of LFOSCs : 0
Number of HFOSCs : 1
Phase 1
I2077: Start design legalization
Design Legalization Statistics
Number of feedthru LUTs inserted to legalize input of DFFs : 34
Number of feedthru LUTs inserted for LUTs driving multiple DFFs : 14
Number of LUTs replicated for LUTs driving multiple DFFs : 8
Number of feedthru LUTs inserted to legalize output of CARRYs : 2
Number of feedthru LUTs inserted to legalize global signals : 0
Number of feedthru CARRYs inserted to legalize input of CARRYs : 1
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 01xxxx : 0
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 10xxxx : 10
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 11xxxx : 0
Total LUTs inserted : 68
Total CARRYs inserted : 1
I2078: Design legalization is completed successfully
I2088: Phase 1, elapsed time : 0.0 (sec)
Phase 2
I2088: Phase 2, elapsed time : 0.1 (sec)
Phase 3
Info-1409: Inferred clock at osc/CLKHF
Design Statistics after Packing
Number of LUTs : 452
Number of DFFs : 104
Number of DFFs packed to IO : 0
Number of Carrys : 46
Device Utilization Summary after Packing
Sequential LogicCells
LUT and DFF : 97
LUT, DFF and CARRY : 7
Combinational LogicCells
Only LUT : 313
CARRY Only : 4
LUT with CARRY : 35
LogicCells : 456/3520
PLBs : 72/440
BRAMs : 4/20
IOs and GBIOs : 8/35
PLLs : 0/1
I2Cs : 0/2
SPIs : 0/2
DSPs : 0/4
SBIOODs : 0/4
LEDDRVs : 0/1
RGBDRVs : 0/1
IRDRVs : 0/1
LEDDIPs : 0/1
LFOSCs : 0/1
HFOSCs : 1/1
I2088: Phase 3, elapsed time : 0.9 (sec)
Phase 4
I2088: Phase 4, elapsed time : 0.2 (sec)
Phase 5
I2088: Phase 5, elapsed time : 0.7 (sec)
Phase 6
I2088: Phase 6, elapsed time : 33.0 (sec)
Final Design Statistics
Number of LUTs : 452
Number of DFFs : 104
Number of DFFs packed to IO : 0
Number of Carrys : 46
Number of RAMs : 4
Number of ROMs : 0
Number of IOs : 8
Number of GBIOs : 0
Number of GBs : 1
Number of WarmBoot : 0
Number of PLLs : 0
Number of I2Cs : 0
Number of SPIs : 0
Number of DSPs : 0
Number of SBIOODs : 0
Number of LEDDRVs : 0
Number of RGBDRVs : 0
Number of LEDDIPs : 0
Number of IRDRVs : 0
Number of LFOSCs : 0
Number of HFOSCs : 1
Device Utilization Summary
LogicCells : 456/3520
PLBs : 91/440
BRAMs : 4/20
IOs and GBIOs : 8/35
PLLs : 0/1
I2Cs : 0/2
SPIs : 0/2
DSPs : 0/4
SBIOODs : 0/4
LEDDRVs : 0/1
RGBDRVs : 0/1
IRDRVs : 0/1
LEDDIPs : 0/1
LFOSCs : 0/1
HFOSCs : 1/1
#####################################################################
Placement Timing Summary
The timing summary is based on estimated routing delays after
placement. For final timing report, please carry out the timing
analysis after routing.
=====================================================================
#####################################################################
Clock Summary
=====================================================================
Number of clocks: 1
Clock: osc/CLKHF | Frequency: 51.32 MHz | Target: 24.00 MHz
=====================================================================
End of Clock Summary
#####################################################################
I2054: Placement of design completed successfully
I2076: Placer run-time: 35.4 sec.
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/packer" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --package SG48 --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer" --DRC_only --translator "/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/sdc_translator.tcl" --src_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc" --dst_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --devicename iCE5LP4K
Lattice Semiconductor Corporation Packer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:02:57
Begin Packing...
initializing finish
Total HPWL cost is 1974
used logic cells: 456
Design Rule Checking Succeeded
DRC Checker run-time: 0 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/packer" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --package SG48 --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer" --translator "/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/sdc_translator.tcl" --src_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc" --dst_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --devicename iCE5LP4K
Lattice Semiconductor Corporation Packer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:02:57
Begin Packing...
initializing finish
Total HPWL cost is 1974
used logic cells: 456
Translating sdc file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc...
Translated sdc file is /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc
Packer succeeded
Packer run-time: 1 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbrouter" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/router" --sdf_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf" --pin_permutation
SJRouter....
Executing : /opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbrouter /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc --outdir /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/router --sdf_file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf --pin_permutation
Lattice Semiconductor Corporation Router
Release: 2017.08.27940
Build Date: Sep 12 2017 08:09:33
I1203: Reading Design top_u4k
Read design time: 0
I1202: Reading Architecture of device iCE5LP4K
Info-1409: Inferred clock at osc/CLKHF
Read device time: 5
I1209: Started routing
I1223: Total Nets : 616
I1212: Iteration 1 : 73 unrouted : 1 seconds
I1212: Iteration 2 : 7 unrouted : 0 seconds
I1212: Iteration 3 : 2 unrouted : 0 seconds
I1212: Iteration 4 : 0 unrouted : 0 seconds
I1215: Routing is successful
Routing time: 1
I1206: Completed routing
I1204: Writing Design top_u4k
Lib Closed
I1210: Writing routes
I1218: Exiting the router
I1224: Router run-time : 6 seconds
total 209776K
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/netlister" --verilog "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.v" --vhdl "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.vhd" --lib "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --view rt --device "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --splitio --in-sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --out-sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/netlister/top_u4k_sbt.sdc"
Lattice Semiconductor Corporation Verilog & VHDL Netlister
Release: 2017.08.27940
Build Date: Sep 12 2017 08:25:37
Generating Verilog & VHDL netlist files ...
Writing /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.v
Writing /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.vhd
Netlister succeeded.
Netlister run-time: 2 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtimer" --des-lib "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --lib-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib" --sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/netlister/top_u4k_sbt.sdc" --sdf-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf" --report-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/timer/top_u4k_timing.rpt" --device-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --timing-summary
Executing : /opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtimer --des-lib /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k --lib-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib --sdc-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/netlister/top_u4k_sbt.sdc --sdf-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf --report-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/timer/top_u4k_timing.rpt --device-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev --timing-summary
Lattice Semiconductor Corporation Timer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:08:07
Info-1409: Inferred clock at osc/CLKHF
Timer run-time: 2 seconds
timer succeeded.
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/bitmap" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --design "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --device_name iCE5LP4K --package SG48 --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/bitmap" --low_power on --init_ram on --init_ram_bank 1111 --frequency low --warm_boot on
Lattice Semiconductor Corporation Bit Stream Generator
Release: 2017.08.27940
Build Date: Sep 12 2017 08:24:49
Bit Stream File Size: 570040 (556K 696 Bits)
Bit Stream Generator succeeded
Bitmap run-time: 1 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtplacer" --des-lib "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer" --device-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --package SG48 --deviceMarketName iCE5LP4K --sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc" --lib-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib" --effort_level std --out-sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc"
Executing : /opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtplacer --des-lib /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k --outdir /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer --device-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev --package SG48 --deviceMarketName iCE5LP4K --sdc-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc --lib-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib --effort_level std --out-sdc-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc
Lattice Semiconductor Corporation Placer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:22:02
I2004: Option and Settings Summary
=============================================================
Device file - /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev
Package - SG48
Design database - /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k
SDC file - /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc
Output directory - /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer
Timing library - /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib
Effort level - std
I2050: Starting reading inputs for placer
=============================================================
I2100: Reading design library: /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k/BFPGA_DESIGN_ep
I2065: Reading device file : /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev
I2051: Reading of inputs for placer completed successfully
I2053: Starting placement of the design
=============================================================
Input Design Statistics
Number of LUTs : 383
Number of DFFs : 99
Number of DFFs packed to IO : 0
Number of Carrys : 45
Number of RAMs : 4
Number of ROMs : 0
Number of IOs : 8
Number of GBIOs : 0
Number of GBs : 1
Number of WarmBoot : 0
Number of PLLs : 0
Number of I2Cs : 0
Number of SPIs : 0
Number of DSPs : 0
Number of SBIOODs : 0
Number of LEDDRVs : 0
Number of RGBDRVs : 0
Number of LEDDIPs : 0
Number of IRDRVs : 0
Number of LFOSCs : 0
Number of HFOSCs : 1
Phase 1
I2077: Start design legalization
Design Legalization Statistics
Number of feedthru LUTs inserted to legalize input of DFFs : 34
Number of feedthru LUTs inserted for LUTs driving multiple DFFs : 14
Number of LUTs replicated for LUTs driving multiple DFFs : 8
Number of feedthru LUTs inserted to legalize output of CARRYs : 2
Number of feedthru LUTs inserted to legalize global signals : 0
Number of feedthru CARRYs inserted to legalize input of CARRYs : 1
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 01xxxx : 0
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 10xxxx : 10
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 11xxxx : 0
Total LUTs inserted : 68
Total CARRYs inserted : 1
I2078: Design legalization is completed successfully
I2088: Phase 1, elapsed time : 0.0 (sec)
Phase 2
I2088: Phase 2, elapsed time : 0.1 (sec)
Phase 3
Info-1409: Inferred clock at osc/CLKHF
Design Statistics after Packing
Number of LUTs : 452
Number of DFFs : 104
Number of DFFs packed to IO : 0
Number of Carrys : 46
Device Utilization Summary after Packing
Sequential LogicCells
LUT and DFF : 97
LUT, DFF and CARRY : 7
Combinational LogicCells
Only LUT : 313
CARRY Only : 4
LUT with CARRY : 35
LogicCells : 456/3520
PLBs : 72/440
BRAMs : 4/20
IOs and GBIOs : 8/35
PLLs : 0/1
I2Cs : 0/2
SPIs : 0/2
DSPs : 0/4
SBIOODs : 0/4
LEDDRVs : 0/1
RGBDRVs : 0/1
IRDRVs : 0/1
LEDDIPs : 0/1
LFOSCs : 0/1
HFOSCs : 1/1
I2088: Phase 3, elapsed time : 1.0 (sec)
Phase 4
I2088: Phase 4, elapsed time : 0.3 (sec)
Phase 5
I2088: Phase 5, elapsed time : 0.7 (sec)
Phase 6
I2088: Phase 6, elapsed time : 48.0 (sec)
Final Design Statistics
Number of LUTs : 452
Number of DFFs : 104
Number of DFFs packed to IO : 0
Number of Carrys : 46
Number of RAMs : 4
Number of ROMs : 0
Number of IOs : 8
Number of GBIOs : 0
Number of GBs : 1
Number of WarmBoot : 0
Number of PLLs : 0
Number of I2Cs : 0
Number of SPIs : 0
Number of DSPs : 0
Number of SBIOODs : 0
Number of LEDDRVs : 0
Number of RGBDRVs : 0
Number of LEDDIPs : 0
Number of IRDRVs : 0
Number of LFOSCs : 0
Number of HFOSCs : 1
Device Utilization Summary
LogicCells : 456/3520
PLBs : 97/440
BRAMs : 4/20
IOs and GBIOs : 8/35
PLLs : 0/1
I2Cs : 0/2
SPIs : 0/2
DSPs : 0/4
SBIOODs : 0/4
LEDDRVs : 0/1
RGBDRVs : 0/1
IRDRVs : 0/1
LEDDIPs : 0/1
LFOSCs : 0/1
HFOSCs : 1/1
#####################################################################
Placement Timing Summary
The timing summary is based on estimated routing delays after
placement. For final timing report, please carry out the timing
analysis after routing.
=====================================================================
#####################################################################
Clock Summary
=====================================================================
Number of clocks: 1
Clock: osc/CLKHF | Frequency: 83.11 MHz | Target: 24.00 MHz
=====================================================================
End of Clock Summary
#####################################################################
I2054: Placement of design completed successfully
I2076: Placer run-time: 50.5 sec.
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/packer" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --package SG48 --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer" --DRC_only --translator "/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/sdc_translator.tcl" --src_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc" --dst_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --devicename iCE5LP4K
X Error: BadMatch (invalid parameter attributes) 8
Major opcode: 42 (X_SetInputFocus)
Resource id: 0x3800026
Lattice Semiconductor Corporation Packer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:02:57
Begin Packing...
initializing finish
Total HPWL cost is 1884
used logic cells: 456
Design Rule Checking Succeeded
DRC Checker run-time: 0 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/packer" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --package SG48 --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer" --translator "/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/sdc_translator.tcl" --src_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc" --dst_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --devicename iCE5LP4K
Lattice Semiconductor Corporation Packer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:02:57
Begin Packing...
initializing finish
Total HPWL cost is 1884
used logic cells: 456
Translating sdc file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc...
Translated sdc file is /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc
Packer succeeded
Packer run-time: 0 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbrouter" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/router" --sdf_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf" --pin_permutation
SJRouter....
Executing : /opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbrouter /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc --outdir /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/router --sdf_file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf --pin_permutation
Lattice Semiconductor Corporation Router
Release: 2017.08.27940
Build Date: Sep 12 2017 08:09:33
I1203: Reading Design top_u4k
Read design time: 1
I1202: Reading Architecture of device iCE5LP4K
Info-1409: Inferred clock at osc/CLKHF
Read device time: 4
I1209: Started routing
I1223: Total Nets : 610
I1212: Iteration 1 : 50 unrouted : 1 seconds
I1212: Iteration 2 : 4 unrouted : 0 seconds
I1212: Iteration 3 : 2 unrouted : 0 seconds
I1212: Iteration 4 : 0 unrouted : 0 seconds
I1215: Routing is successful
Routing time: 1
I1206: Completed routing
I1204: Writing Design top_u4k
Lib Closed
I1210: Writing routes
I1218: Exiting the router
I1224: Router run-time : 7 seconds
total 209780K
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/netlister" --verilog "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.v" --vhdl "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.vhd" --lib "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --view rt --device "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --splitio --in-sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --out-sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/netlister/top_u4k_sbt.sdc"
Lattice Semiconductor Corporation Verilog & VHDL Netlister
Release: 2017.08.27940
Build Date: Sep 12 2017 08:25:37
Generating Verilog & VHDL netlist files ...
Writing /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.v
Writing /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.vhd
Netlister succeeded.
Netlister run-time: 3 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtimer" --des-lib "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --lib-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib" --sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/netlister/top_u4k_sbt.sdc" --sdf-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf" --report-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/timer/top_u4k_timing.rpt" --device-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --timing-summary
Executing : /opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtimer --des-lib /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k --lib-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib --sdc-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/netlister/top_u4k_sbt.sdc --sdf-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf --report-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/timer/top_u4k_timing.rpt --device-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev --timing-summary
Lattice Semiconductor Corporation Timer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:08:07
Info-1409: Inferred clock at osc/CLKHF
Timer run-time: 2 seconds
timer succeeded.
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtplacer" --des-lib "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer" --device-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --package SG48 --deviceMarketName iCE5LP4K --sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc" --lib-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib" --effort_level std --out-sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc"
Executing : /opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtplacer --des-lib /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k --outdir /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer --device-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev --package SG48 --deviceMarketName iCE5LP4K --sdc-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc --lib-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib --effort_level std --out-sdc-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc
Lattice Semiconductor Corporation Placer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:22:02
I2004: Option and Settings Summary
=============================================================
Device file - /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev
Package - SG48
Design database - /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k
SDC file - /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/Temp/sbt_temp.sdc
Output directory - /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer
Timing library - /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib
Effort level - std
I2050: Starting reading inputs for placer
=============================================================
I2100: Reading design library: /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k/BFPGA_DESIGN_ep
I2065: Reading device file : /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev
I2051: Reading of inputs for placer completed successfully
I2053: Starting placement of the design
=============================================================
Input Design Statistics
Number of LUTs : 383
Number of DFFs : 99
Number of DFFs packed to IO : 0
Number of Carrys : 45
Number of RAMs : 4
Number of ROMs : 0
Number of IOs : 8
Number of GBIOs : 0
Number of GBs : 1
Number of WarmBoot : 0
Number of PLLs : 0
Number of I2Cs : 0
Number of SPIs : 0
Number of DSPs : 0
Number of SBIOODs : 0
Number of LEDDRVs : 0
Number of RGBDRVs : 0
Number of LEDDIPs : 0
Number of IRDRVs : 0
Number of LFOSCs : 0
Number of HFOSCs : 1
Phase 1
I2077: Start design legalization
Design Legalization Statistics
Number of feedthru LUTs inserted to legalize input of DFFs : 34
Number of feedthru LUTs inserted for LUTs driving multiple DFFs : 14
Number of LUTs replicated for LUTs driving multiple DFFs : 8
Number of feedthru LUTs inserted to legalize output of CARRYs : 2
Number of feedthru LUTs inserted to legalize global signals : 0
Number of feedthru CARRYs inserted to legalize input of CARRYs : 1
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 01xxxx : 0
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 10xxxx : 10
Number of inserted LUTs to Legalize IOs with PIN_TYPE= 11xxxx : 0
Total LUTs inserted : 68
Total CARRYs inserted : 1
I2078: Design legalization is completed successfully
I2088: Phase 1, elapsed time : 0.0 (sec)
Phase 2
I2088: Phase 2, elapsed time : 0.1 (sec)
Phase 3
Info-1409: Inferred clock at osc/CLKHF
Design Statistics after Packing
Number of LUTs : 452
Number of DFFs : 104
Number of DFFs packed to IO : 0
Number of Carrys : 46
Device Utilization Summary after Packing
Sequential LogicCells
LUT and DFF : 97
LUT, DFF and CARRY : 7
Combinational LogicCells
Only LUT : 313
CARRY Only : 4
LUT with CARRY : 35
LogicCells : 456/3520
PLBs : 72/440
BRAMs : 4/20
IOs and GBIOs : 8/35
PLLs : 0/1
I2Cs : 0/2
SPIs : 0/2
DSPs : 0/4
SBIOODs : 0/4
LEDDRVs : 0/1
RGBDRVs : 0/1
IRDRVs : 0/1
LEDDIPs : 0/1
LFOSCs : 0/1
HFOSCs : 1/1
I2088: Phase 3, elapsed time : 1.0 (sec)
Phase 4
I2088: Phase 4, elapsed time : 0.2 (sec)
Phase 5
I2088: Phase 5, elapsed time : 0.7 (sec)
Phase 6
I2088: Phase 6, elapsed time : 32.8 (sec)
Final Design Statistics
Number of LUTs : 452
Number of DFFs : 104
Number of DFFs packed to IO : 0
Number of Carrys : 46
Number of RAMs : 4
Number of ROMs : 0
Number of IOs : 8
Number of GBIOs : 0
Number of GBs : 1
Number of WarmBoot : 0
Number of PLLs : 0
Number of I2Cs : 0
Number of SPIs : 0
Number of DSPs : 0
Number of SBIOODs : 0
Number of LEDDRVs : 0
Number of RGBDRVs : 0
Number of LEDDIPs : 0
Number of IRDRVs : 0
Number of LFOSCs : 0
Number of HFOSCs : 1
Device Utilization Summary
LogicCells : 456/3520
PLBs : 91/440
BRAMs : 4/20
IOs and GBIOs : 8/35
PLLs : 0/1
I2Cs : 0/2
SPIs : 0/2
DSPs : 0/4
SBIOODs : 0/4
LEDDRVs : 0/1
RGBDRVs : 0/1
IRDRVs : 0/1
LEDDIPs : 0/1
LFOSCs : 0/1
HFOSCs : 1/1
#####################################################################
Placement Timing Summary
The timing summary is based on estimated routing delays after
placement. For final timing report, please carry out the timing
analysis after routing.
=====================================================================
#####################################################################
Clock Summary
=====================================================================
Number of clocks: 1
Clock: osc/CLKHF | Frequency: 51.32 MHz | Target: 24.00 MHz
=====================================================================
End of Clock Summary
#####################################################################
I2054: Placement of design completed successfully
I2076: Placer run-time: 35.3 sec.
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/packer" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --package SG48 --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer" --DRC_only --translator "/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/sdc_translator.tcl" --src_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc" --dst_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --devicename iCE5LP4K
Lattice Semiconductor Corporation Packer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:02:57
Begin Packing...
initializing finish
Total HPWL cost is 1974
used logic cells: 456
Design Rule Checking Succeeded
DRC Checker run-time: 1 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/packer" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --package SG48 --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer" --translator "/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/sdc_translator.tcl" --src_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc" --dst_sdc_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --devicename iCE5LP4K
Lattice Semiconductor Corporation Packer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:02:57
Begin Packing...
initializing finish
Total HPWL cost is 1974
used logic cells: 456
Translating sdc file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/placer/top_u4k_pl.sdc...
Translated sdc file is /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc
Packer succeeded
Packer run-time: 0 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbrouter" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib" "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --outdir "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/router" --sdf_file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf" --pin_permutation
SJRouter....
Executing : /opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbrouter /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc --outdir /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/router --sdf_file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf --pin_permutation
Lattice Semiconductor Corporation Router
Release: 2017.08.27940
Build Date: Sep 12 2017 08:09:33
I1203: Reading Design top_u4k
Read design time: 1
I1202: Reading Architecture of device iCE5LP4K
Info-1409: Inferred clock at osc/CLKHF
Read device time: 4
I1209: Started routing
I1223: Total Nets : 616
I1212: Iteration 1 : 73 unrouted : 1 seconds
I1212: Iteration 2 : 7 unrouted : 0 seconds
I1212: Iteration 3 : 2 unrouted : 0 seconds
I1212: Iteration 4 : 0 unrouted : 0 seconds
I1215: Routing is successful
Routing time: 1
I1206: Completed routing
I1204: Writing Design top_u4k
Lib Closed
I1210: Writing routes
I1218: Exiting the router
I1224: Router run-time : 7 seconds
total 209776K
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/netlister" --verilog "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.v" --vhdl "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.vhd" --lib "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --view rt --device "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --splitio --in-sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/packer/top_u4k_pk.sdc" --out-sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/netlister/top_u4k_sbt.sdc"
Lattice Semiconductor Corporation Verilog & VHDL Netlister
Release: 2017.08.27940
Build Date: Sep 12 2017 08:25:37
Generating Verilog & VHDL netlist files ...
Writing /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.v
Writing /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.vhd
Netlister succeeded.
Netlister run-time: 3 (sec)
"/opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtimer" --des-lib "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k" --lib-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib" --sdc-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/netlister/top_u4k_sbt.sdc" --sdf-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf" --report-file "/home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/timer/top_u4k_timing.rpt" --device-file "/opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev" --timing-summary
Executing : /opt/lscc/iCEcube2.2017.08/sbt_backend/bin/linux/opt/sbtimer --des-lib /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/netlist/oadb-top_u4k --lib-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ice40TH4K.lib --sdc-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/netlister/top_u4k_sbt.sdc --sdf-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/simulation_netlist/top_u4k_sbt.sdf --report-file /home/corecode/devel/forth-cpu/icecube/test2/test2_Implmnt/sbt/outputs/timer/top_u4k_timing.rpt --device-file /opt/lscc/iCEcube2.2017.08/sbt_backend/devices/ICE40T04.dev --timing-summary
Lattice Semiconductor Corporation Timer
Release: 2017.08.27940
Build Date: Sep 12 2017 08:08:07
Info-1409: Inferred clock at osc/CLKHF
Timer run-time: 2 seconds
timer succeeded.
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