A simple Makefile for C

Makefile

TARGET := main

SRC := src
INC := include
BIN := bin
TEST := test
BUILD := build

# group the files
HEADER = $(wildcard $(INC)/*.h)
OBJECT = $(patsubst %, $(BUILD)/%, $(notdir $(SOURCE:.c=.o)))

CC = gcc
CFLAGS = -I$(INC) -std=c11

# $@ : target
# $^ : dependency list
# $< : first name in dependency list

# compile target if any object file or header file changes
$(BIN)/$(TARGET): $(OBJECT) $(HEADER)
        $(CC) $(CFLAGS) -o $@ $(OBJECT)

# compile object files but do not link them
$(BUILD)/%.o: $(SRC)/%.c
	$(CC) $(CFLAGS) -o $@ -c $<

# avoid doing something to file named clean
.PHONY: clean

clean:
        rm -f build/* bin/*