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Created June 9, 2016 08:05
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gistfile1.txt
From 1f6246cd4f15dfea22edba7d70119e8b8c0d6821 Mon Sep 17 00:00:00 2001
From: coypu <coypu@sdf.org>
Date: Thu, 9 Jun 2016 09:22:59 +0300
Subject: [PATCH 1/4] Rename AR9380 to AR9300
AR9300 is the name used in linux (upstream).
Also, it likely matches devices like AR9340, and it wouldn't make sense
to call that device newer than AR9380.
---
sys/dev/ic/athn.c | 48 ++++++++++++++++++++++++------------------------
sys/dev/ic/athnreg.h | 26 +++++++++++++-------------
2 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index cbeb3d9..42bd559 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -171,7 +171,7 @@ athn_attach(struct athn_softc *sc)
#endif
else if (AR_SREV_9287(sc))
error = ar9287_attach(sc);
- else if (AR_SREV_9380(sc) || AR_SREV_9485(sc))
+ else if (AR_SREV_9300(sc) || AR_SREV_9485(sc))
error = ar9380_attach(sc);
else
error = ENOTSUP;
@@ -287,7 +287,7 @@ athn_attach(struct athn_softc *sc)
IEEE80211_HTCAP_DSSSCCK40;
if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc))
ic->ic_htcaps |= IEEE80211_HTCAP_SGI20;
- if (AR_SREV_9380_10_OR_LATER(sc))
+ if (AR_SREV_9300_10_OR_LATER(sc))
ic->ic_htcaps |= IEEE80211_HTCAP_LDPC;
if (AR_SREV_9280_10_OR_LATER(sc)) {
ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
@@ -295,7 +295,7 @@ athn_attach(struct athn_softc *sc)
}
ntxstreams = sc->sc_ntxchains;
nrxstreams = sc->sc_nrxchains;
- if (!AR_SREV_9380_10_OR_LATER(sc)) {
+ if (!AR_SREV_9300_10_OR_LATER(sc)) {
ntxstreams = MIN(ntxstreams, 2);
nrxstreams = MIN(nrxstreams, 2);
}
@@ -575,8 +575,8 @@ athn_get_mac_name(struct athn_softc *sc)
return "AR9271";
case AR_SREV_VERSION_9287:
return "AR9287";
- case AR_SREV_VERSION_9380:
- return "AR9380";
+ case AR_SREV_VERSION_9300:
+ return "AR9300";
case AR_SREV_VERSION_9485:
return "AR9485";
default:
@@ -616,7 +616,7 @@ athn_reset_power_on(struct athn_softc *sc)
AR_WRITE(sc, AR_RTC_FORCE_WAKE,
AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
- if (!AR_SREV_9380_10_OR_LATER(sc)) {
+ if (!AR_SREV_9300_10_OR_LATER(sc)) {
/* Make sure no DMA is active by doing an AHB reset. */
AR_WRITE(sc, AR_RC, AR_RC_AHB);
}
@@ -624,7 +624,7 @@ athn_reset_power_on(struct athn_softc *sc)
AR_WRITE(sc, AR_RTC_RESET, 0);
AR_WRITE_BARRIER(sc);
DELAY(2);
- if (!AR_SREV_9380_10_OR_LATER(sc))
+ if (!AR_SREV_9300_10_OR_LATER(sc))
AR_WRITE(sc, AR_RC, 0);
AR_WRITE(sc, AR_RTC_RESET, 1);
@@ -655,9 +655,9 @@ athn_reset(struct athn_softc *sc, int cold_reset)
(AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |
- (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0));
+ (!AR_SREV_9300_10_OR_LATER(sc) ? AR_RC_AHB : 0));
}
- else if (!AR_SREV_9380_10_OR_LATER(sc))
+ else if (!AR_SREV_9300_10_OR_LATER(sc))
AR_WRITE(sc, AR_RC, AR_RC_AHB);
AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |
@@ -690,7 +690,7 @@ athn_set_power_awake(struct athn_softc *sc)
AR_RTC_STATUS_SHUTDOWN) {
if ((error = athn_reset_power_on(sc)) != 0)
return error;
- if (!AR_SREV_9380_10_OR_LATER(sc))
+ if (!AR_SREV_9300_10_OR_LATER(sc))
athn_init_pll(sc, NULL);
}
AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
@@ -722,7 +722,7 @@ athn_set_power_sleep(struct athn_softc *sc)
AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
/* Allow the MAC to go to sleep. */
AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
- if (!AR_SREV_9380_10_OR_LATER(sc))
+ if (!AR_SREV_9300_10_OR_LATER(sc))
AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
/*
* NB: Clearing RTC_RESET_EN when setting the chip to sleep mode
@@ -738,7 +738,7 @@ athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c)
{
uint32_t pll;
- if (AR_SREV_9380_10_OR_LATER(sc)) {
+ if (AR_SREV_9300_10_OR_LATER(sc)) {
if (AR_SREV_9485(sc))
AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666);
pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);
@@ -1258,7 +1258,7 @@ athn_calib_to(void *arg)
/* Do periodic (every 4 minutes) PA calibration. */
if (AR_SREV_9285_11_OR_LATER(sc) &&
- !AR_SREV_9380_10_OR_LATER(sc) &&
+ !AR_SREV_9300_10_OR_LATER(sc) &&
(ticks - (sc->sc_pa_calib_ticks + 240 * hz)) >= 0) {
sc->sc_pa_calib_ticks = ticks;
if (AR_SREV_9271(sc))
@@ -1297,7 +1297,7 @@ athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan,
struct athn_ops *ops = &sc->sc_ops;
int error;
- if (AR_SREV_9380_10_OR_LATER(sc))
+ if (AR_SREV_9300_10_OR_LATER(sc))
error = ar9003_init_calib(sc);
else if (AR_SREV_9285_10_OR_LATER(sc))
error = ar9285_init_calib(sc, curchan, extchan);
@@ -1306,7 +1306,7 @@ athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan,
if (error != 0)
return error;
- if (!AR_SREV_9380_10_OR_LATER(sc)) {
+ if (!AR_SREV_9300_10_OR_LATER(sc)) {
/* Do PA calibration. */
if (AR_SREV_9285_11_OR_LATER(sc)) {
extern int ticks;
@@ -1322,7 +1322,7 @@ athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *curchan,
if (AR_SREV_9160_10_OR_LATER(sc)) {
/* Support IQ calibration. */
sc->sc_sup_calib_mask = ATHN_CAL_IQ;
- if (AR_SREV_9380_10_OR_LATER(sc)) {
+ if (AR_SREV_9300_10_OR_LATER(sc)) {
/* Support temperature compensation calibration. */
sc->sc_sup_calib_mask |= ATHN_CAL_TEMP;
}
@@ -1684,7 +1684,7 @@ athn_init_dma(struct athn_softc *sc)
{
uint32_t reg;
- if (!AR_SREV_9380_10_OR_LATER(sc)) {
+ if (!AR_SREV_9300_10_OR_LATER(sc)) {
/* Set AHB not to do cacheline prefetches. */
AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
}
@@ -1695,7 +1695,7 @@ athn_init_dma(struct athn_softc *sc)
/* Set initial Tx trigger level. */
if (AR_SREV_9285(sc) || AR_SREV_9271(sc))
reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B);
- else if (!AR_SREV_9380_10_OR_LATER(sc))
+ else if (!AR_SREV_9300_10_OR_LATER(sc))
reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B);
AR_WRITE(sc, AR_TXCFG, reg);
@@ -1719,7 +1719,7 @@ athn_init_dma(struct athn_softc *sc)
AR_WRITE_BARRIER(sc);
/* Reset Tx status ring. */
- if (AR_SREV_9380_10_OR_LATER(sc))
+ if (AR_SREV_9300_10_OR_LATER(sc))
ar9003_reset_txsring(sc);
}
@@ -1924,7 +1924,7 @@ athn_init_tx_queues(struct athn_softc *sc)
AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD),
AR_D_MISC_POST_FR_BKOFF_DIS);
- if (AR_SREV_9380_10_OR_LATER(sc)) {
+ if (AR_SREV_9300_10_OR_LATER(sc)) {
/* Enable MAC descriptor CRC check. */
AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
}
@@ -2232,7 +2232,7 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan,
if (AR_SREV_9280_10_OR_LATER(sc))
AR_SETBITS(sc, sc->sc_gpio_input_en_off, AR_GPIO_JTAG_DISABLE);
- if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc))
+ if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9300_10_OR_LATER(sc))
ar9287_1_3_enable_async_fifo(sc);
/* Write init values to hardware. */
@@ -2303,7 +2303,7 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan,
AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN |
AR_IMR_RXMINTR | AR_IMR_RXINTM |
AR_IMR_GENTMR | AR_IMR_BCNMISC;
- if (AR_SREV_9380_10_OR_LATER(sc))
+ if (AR_SREV_9300_10_OR_LATER(sc))
sc->sc_imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK;
#ifndef IEEE80211_STA_ONLY
if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP)
@@ -2317,7 +2317,7 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan,
sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin);
AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
- if (AR_SREV_9380_10_OR_LATER(sc)) {
+ if (AR_SREV_9300_10_OR_LATER(sc)) {
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0);
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0);
AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0);
@@ -2328,7 +2328,7 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan,
AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA);
- if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc))
+ if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9300_10_OR_LATER(sc))
ar9287_1_3_setup_async_fifo(sc);
/* Disable sequence number generation in hardware. */
diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h
index 0070de4..2491717 100644
--- a/sys/dev/ic/athnreg.h
+++ b/sys/dev/ic/athnreg.h
@@ -789,9 +789,9 @@
#define AR_SREV_REVISION_9287_11 1
#define AR_SREV_REVISION_9287_12 2
#define AR_SREV_REVISION_9287_13 3
-#define AR_SREV_VERSION_9380 0x1c0
-#define AR_SREV_REVISION_9380_10 0
-#define AR_SREV_REVISION_9380_20 2
+#define AR_SREV_VERSION_9300 0x1c0
+#define AR_SREV_REVISION_9300_10 0
+#define AR_SREV_REVISION_9300_20 2
#define AR_SREV_VERSION_9485 0x240
#define AR_SREV_REVISION_9485_10 0
@@ -1406,16 +1406,16 @@
((sc)->sc_mac_ver > AR_SREV_VERSION_9287 || \
(AR_SREV_9287(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9287_13))
-#define AR_SREV_9380(sc) \
- ((sc)->sc_mac_ver == AR_SREV_VERSION_9380)
-#define AR_SREV_9380_10_OR_LATER(sc) \
- ((sc)->sc_mac_ver >= AR_SREV_VERSION_9380)
-#define AR_SREV_9380_20(sc) \
- (AR_SREV_9380(sc) && \
- (sc)->sc_mac_rev == AR_SREV_REVISION_9380_20)
-#define AR_SREV_9380_20_OR_LATER(sc) \
- ((sc)->sc_mac_ver > AR_SREV_VERSION_9380 || \
- (AR_SREV_9380(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9380_20))
+#define AR_SREV_9300(sc) \
+ ((sc)->sc_mac_ver == AR_SREV_VERSION_9300)
+#define AR_SREV_9300_10_OR_LATER(sc) \
+ ((sc)->sc_mac_ver >= AR_SREV_VERSION_9300)
+#define AR_SREV_9300_20(sc) \
+ (AR_SREV_9300(sc) && \
+ (sc)->sc_mac_rev == AR_SREV_REVISION_9300_20)
+#define AR_SREV_9300_20_OR_LATER(sc) \
+ ((sc)->sc_mac_ver > AR_SREV_VERSION_9300 || \
+ (AR_SREV_9300(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9300_20))
#define AR_SREV_9485(sc) \
((sc)->sc_mac_ver == AR_SREV_VERSION_9485)
--
2.8.2
From e4de2de5ad68c4ca6f0986c22921d03051a3191d Mon Sep 17 00:00:00 2001
From: coypu <coypu@sdf.org>
Date: Thu, 9 Jun 2016 09:24:57 +0300
Subject: [PATCH 2/4] Use different AR_CR_RXE for AR9300 or newer.
From linux.
athn(4) doesn't document any devices like this as working, so it is
unlikely to negatively affect any device.
---
sys/dev/ic/arn5008.c | 4 ++--
sys/dev/ic/athn.c | 2 +-
sys/dev/ic/athnreg.h | 2 +-
sys/dev/usb/if_athn_usb.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/sys/dev/ic/arn5008.c b/sys/dev/ic/arn5008.c
index 9efed9a..5f8d598 100644
--- a/sys/dev/ic/arn5008.c
+++ b/sys/dev/ic/arn5008.c
@@ -719,7 +719,7 @@ ar5008_rx_enable(struct athn_softc *sc)
/* Enable Rx. */
AR_WRITE(sc, AR_RXDP, SIMPLEQ_FIRST(&rxq->head)->bf_daddr);
- AR_WRITE(sc, AR_CR, AR_CR_RXE);
+ AR_WRITE(sc, AR_CR, AR_CR_RXE(sc));
AR_WRITE_BARRIER(sc);
}
@@ -950,7 +950,7 @@ ar5008_rx_process(struct athn_softc *sc)
rxq->lastds = ds;
/* Re-enable Rx. */
- AR_WRITE(sc, AR_CR, AR_CR_RXE);
+ AR_WRITE(sc, AR_CR, AR_CR_RXE(sc));
AR_WRITE_BARRIER(sc);
return 0;
}
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index 42bd559..af9028b 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -1749,7 +1749,7 @@ athn_stop_rx_dma(struct athn_softc *sc)
AR_WRITE(sc, AR_CR, AR_CR_RXD);
/* Wait for Rx enable bit to go low. */
for (ntries = 0; ntries < 100; ntries++) {
- if (!(AR_READ(sc, AR_CR) & AR_CR_RXE))
+ if (!(AR_READ(sc, AR_CR) & AR_CR_RXE(sc)))
return 0;
DELAY(100);
}
diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h
index 2491717..5fdc6e9 100644
--- a/sys/dev/ic/athnreg.h
+++ b/sys/dev/ic/athnreg.h
@@ -257,7 +257,7 @@
/* Bits for AR_CR. */
-#define AR_CR_RXE 0x00000004
+#define AR_CR_RXE(sc) (AR_SREV_9300_10_OR_LATER(sc) ? 0x0000000c : 0x00000004)
#define AR_CR_RXD 0x00000020
#define AR_CR_SWI 0x00000040
diff --git a/sys/dev/usb/if_athn_usb.c b/sys/dev/usb/if_athn_usb.c
index 471f68b..5c56068 100644
--- a/sys/dev/usb/if_athn_usb.c
+++ b/sys/dev/usb/if_athn_usb.c
@@ -1569,7 +1569,7 @@ athn_usb_rx_enable(struct athn_softc *sc)
DPRINTFN(DBG_FN, sc, "\n");
- AR_WRITE(sc, AR_CR, AR_CR_RXE);
+ AR_WRITE(sc, AR_CR, AR_CR_RXE(sc));
AR_WRITE_BARRIER(sc);
}
--
2.8.2
From 42a99999e1cc44e0ccef31ab22d6f2bbcc136c99 Mon Sep 17 00:00:00 2001
From: coypu <coypu@sdf.org>
Date: Thu, 9 Jun 2016 10:08:03 +0300
Subject: [PATCH 3/4] Sprinkle AR9430 specific redefinitions
Adjust code to pass sc.
---
sys/dev/ic/arn5008.c | 16 ++++++++--------
sys/dev/ic/arn9003.c | 12 ++++++------
sys/dev/ic/athn.c | 32 ++++++++++++++++----------------
sys/dev/ic/athnreg.h | 18 +++++++++++-------
4 files changed, 41 insertions(+), 37 deletions(-)
diff --git a/sys/dev/ic/arn5008.c b/sys/dev/ic/arn5008.c
index 5f8d598..f5f3905 100644
--- a/sys/dev/ic/arn5008.c
+++ b/sys/dev/ic/arn5008.c
@@ -1183,19 +1183,19 @@ ar5008_intr(struct athn_softc *sc)
uint32_t intr, intr5, sync;
/* Get pending interrupts. */
- intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
+ intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE(sc));
if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
- intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ intr = AR_READ(sc, AR_INTR_SYNC_CAUSE(sc));
if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0)
return 0; /* Not for us. */
}
- if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+ if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE(sc)) & AR_INTR_MAC_IRQ) &&
(AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
intr = AR_READ(sc, AR_ISR);
else
intr = 0;
- sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync;
+ sync = AR_READ(sc, AR_INTR_SYNC_CAUSE(sc)) & sc->sc_isync;
if (intr == 0 && sync == 0)
return 0; /* Not for us. */
@@ -1257,13 +1257,13 @@ ar5008_intr(struct athn_softc *sc)
if ((sc->sc_flags & ATHN_FLAG_RFSILENT) &&
(sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) {
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
- (void)AR_READ(sc, AR_INTR_SYNC_ENABLE);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), 0);
+ (void)AR_READ(sc, AR_INTR_SYNC_ENABLE(sc));
pmf_event_inject(sc->sc_dev, PMFE_RADIO_OFF);
}
- AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
- (void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE(sc), sync);
+ (void)AR_READ(sc, AR_INTR_SYNC_CAUSE(sc));
}
return 1;
}
diff --git a/sys/dev/ic/arn9003.c b/sys/dev/ic/arn9003.c
index e539930..2ba24af 100644
--- a/sys/dev/ic/arn9003.c
+++ b/sys/dev/ic/arn9003.c
@@ -1342,19 +1342,19 @@ ar9003_intr(struct athn_softc *sc)
uint32_t intr, sync;
/* Get pending interrupts. */
- intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
+ intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE(sc));
if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
- intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ intr = AR_READ(sc, AR_INTR_SYNC_CAUSE(sc));
if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0)
return 0; /* Not for us. */
}
- if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+ if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE(sc)) & AR_INTR_MAC_IRQ) &&
(AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
intr = AR_READ(sc, AR_ISR);
else
intr = 0;
- sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync;
+ sync = AR_READ(sc, AR_INTR_SYNC_CAUSE(sc)) & sc->sc_isync;
if (intr == 0 && sync == 0)
return 0; /* Not for us. */
@@ -1416,8 +1416,8 @@ ar9003_intr(struct athn_softc *sc)
return 1;
}
- AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
- (void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE(sc), sync);
+ (void)AR_READ(sc, AR_INTR_SYNC_CAUSE(sc));
}
return 1;
}
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index af9028b..19bb35d 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -651,9 +651,9 @@ athn_reset(struct athn_softc *sc, int cold_reset)
AR_WRITE(sc, AR_RTC_FORCE_WAKE,
AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
- if (AR_READ(sc, AR_INTR_SYNC_CAUSE) &
+ if (AR_READ(sc, AR_INTR_SYNC_CAUSE(sc)) &
(AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), 0);
AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |
(!AR_SREV_9300_10_OR_LATER(sc) ? AR_RC_AHB : 0));
}
@@ -805,7 +805,7 @@ athn_config_pcie(struct athn_softc *sc)
DELAY(1000);
/* Allow forcing of PCIe core into L1 state. */
- AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+ AR_SETBITS(sc, AR_PCIE_PM_CTRL(sc), AR_PCIE_PM_CTRL_ENA);
#ifndef ATHN_PCIE_WAEN
AR_WRITE(sc, AR_WA, sc->sc_workaround);
@@ -2097,11 +2097,11 @@ athn_enable_interrupts(struct athn_softc *sc)
AR_WRITE(sc, AR_IER, AR_IER_ENABLE);
- AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
- AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+ AR_WRITE(sc, AR_INTR_ASYNC_ENABLE(sc), AR_INTR_MAC_IRQ);
+ AR_WRITE(sc, AR_INTR_ASYNC_MASK(sc), AR_INTR_MAC_IRQ);
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
- AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), sc->sc_isync);
+ AR_WRITE(sc, AR_INTR_SYNC_MASK(sc), sc->sc_isync);
AR_WRITE_BARRIER(sc);
}
@@ -2112,11 +2112,11 @@ athn_disable_interrupts(struct athn_softc *sc)
AR_WRITE(sc, AR_IER, 0);
(void)AR_READ(sc, AR_IER);
- AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0);
- (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE);
+ AR_WRITE(sc, AR_INTR_ASYNC_ENABLE(sc), 0);
+ (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE(sc));
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
- (void)AR_READ(sc, AR_INTR_SYNC_ENABLE);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), 0);
+ (void)AR_READ(sc, AR_INTR_SYNC_ENABLE(sc));
AR_WRITE(sc, AR_IMR, 0);
@@ -2311,12 +2311,12 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan,
#endif
AR_WRITE(sc, AR_IMR, sc->sc_imask);
AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT);
- AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE(sc), 0xffffffff);
sc->sc_isync = AR_INTR_SYNC_DEFAULT;
if (sc->sc_flags & ATHN_FLAG_RFSILENT)
sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin);
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
- AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), sc->sc_isync);
+ AR_WRITE(sc, AR_INTR_SYNC_MASK(sc), 0);
if (AR_SREV_9300_10_OR_LATER(sc)) {
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0);
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0);
@@ -2940,8 +2940,8 @@ athn_stop(struct ifnet *ifp, int disable)
/* Disable interrupts. */
athn_disable_interrupts(sc);
/* Acknowledge interrupts (avoids interrupt storms). */
- AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
- AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE(sc), 0xffffffff);
+ AR_WRITE(sc, AR_INTR_SYNC_MASK(sc), 0);
for (qid = 0; qid < ATHN_QID_COUNT; qid++)
athn_stop_tx_dma(sc, qid);
diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h
index 5fdc6e9..b091719 100644
--- a/sys/dev/ic/athnreg.h
+++ b/sys/dev/ic/athnreg.h
@@ -98,17 +98,17 @@
#define AR_RC 0x4000
#define AR_WA 0x4004
#define AR_PM_STATE 0x4008
-#define AR_PCIE_PM_CTRL 0x4014
+#define AR_PCIE_PM_CTRL(sc) (AR_SREV_9340(sc) ? 0x4004 : 0x4014)
#define AR_HOST_TIMEOUT 0x4018
#define AR_EEPROM 0x401c
#define AR_SREV 0x4020
#define AR_AHB_MODE 0x4024
-#define AR_INTR_SYNC_CAUSE 0x4028
-#define AR_INTR_SYNC_ENABLE 0x402c
-#define AR_INTR_ASYNC_MASK 0x4030
-#define AR_INTR_SYNC_MASK 0x4034
-#define AR_INTR_ASYNC_CAUSE 0x4038
-#define AR_INTR_ASYNC_ENABLE 0x403c
+#define AR_INTR_SYNC_CAUSE(sc) (AR_SREV_9340(sc) ? 0x4010 : 0x4028)
+#define AR_INTR_SYNC_ENABLE(sc) (AR_SREV_9340(sc) ? 0x4014 : 0x402c)
+#define AR_INTR_ASYNC_MASK(sc) (AR_SREV_9340(sc) ? 0x4018 : 0x4030)
+#define AR_INTR_SYNC_MASK(sc) (AR_SREV_9340(sc) ? 0x401c : 0x4034)
+#define AR_INTR_ASYNC_CAUSE(sc) (AR_SREV_9340(sc) ? 0x4020 : 0x4038)
+#define AR_INTR_ASYNC_ENABLE(sc) (AR_SREV_9340(sc) ? 0x4024 : 0x403c)
#define AR_PCIE_SERDES 0x4040
#define AR_PCIE_SERDES2 0x4044
#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4
@@ -792,6 +792,7 @@
#define AR_SREV_VERSION_9300 0x1c0
#define AR_SREV_REVISION_9300_10 0
#define AR_SREV_REVISION_9300_20 2
+#define AR_SREV_VERSION_9340 0x300
#define AR_SREV_VERSION_9485 0x240
#define AR_SREV_REVISION_9485_10 0
@@ -1406,6 +1407,9 @@
((sc)->sc_mac_ver > AR_SREV_VERSION_9287 || \
(AR_SREV_9287(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9287_13))
+#define AR_SREV_9340(sc) \
+ (((sc)->sc_mac_ver == AR_SREV_VERSION_9340))
+
#define AR_SREV_9300(sc) \
((sc)->sc_mac_ver == AR_SREV_VERSION_9300)
#define AR_SREV_9300_10_OR_LATER(sc) \
--
2.8.2
From e89c5a94d1c5f4bfd26457c8911e19f76c706d54 Mon Sep 17 00:00:00 2001
From: coypu <coypu@sdf.org>
Date: Thu, 9 Jun 2016 10:29:21 +0300
Subject: [PATCH 4/4] Sprinkle some AR9100 and AR9340 specific redefs
from linux.
---
sys/dev/ic/athn.c | 2 +-
sys/dev/ic/athnreg.h | 14 ++++++++++----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index 19bb35d..6791eef 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -541,7 +541,7 @@ athn_get_chipid(struct athn_softc *sc)
{
uint32_t reg;
- reg = AR_READ(sc, AR_SREV);
+ reg = AR_READ(sc, AR_SREV(sc));
if (MS(reg, AR_SREV_ID) == 0xff) {
sc->sc_mac_ver = MS(reg, AR_SREV_VERSION2);
sc->sc_mac_rev = MS(reg, AR_SREV_REVISION2);
diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h
index b091719..87b9b03 100644
--- a/sys/dev/ic/athnreg.h
+++ b/sys/dev/ic/athnreg.h
@@ -96,12 +96,14 @@
#define AR_CFG_LED 0x1f04
#define AR_EEPROM_OFFSET(i) (0x2000 + (i) * 4)
#define AR_RC 0x4000
-#define AR_WA 0x4004
+#define AR_WA (AR_SREV_9340(sc) ? 0x40c4 : 0x4004)
#define AR_PM_STATE 0x4008
#define AR_PCIE_PM_CTRL(sc) (AR_SREV_9340(sc) ? 0x4004 : 0x4014)
-#define AR_HOST_TIMEOUT 0x4018
+#define AR_HOST_TIMEOUT (AR_SREV_9340(sc) ? 0x4008 : 0x4018)
#define AR_EEPROM 0x401c
-#define AR_SREV 0x4020
+#define AR_SREV(sc) \
+ ((AR_SREV_9100(sc)) ? 0x0600 : (AR_SREV_9340(sc) \
+ ? 0x400c : 0x4020))
#define AR_AHB_MODE 0x4024
#define AR_INTR_SYNC_CAUSE(sc) (AR_SREV_9340(sc) ? 0x4010 : 0x4028)
#define AR_INTR_SYNC_ENABLE(sc) (AR_SREV_9340(sc) ? 0x4014 : 0x402c)
@@ -750,7 +752,8 @@
#define AR_EEPROM_PROT_MASK_S 10
/* Bits for AR_SREV. */
-#define AR_SREV_ID_M 0x000000ff
+#define AR_SREV_ID_M \
+ ((AR_SREV_9100(sc)) ? 0x00000fff : 0x000000ff)
#define AR_SREV_ID_S 0
#define AR_SREV_REVISION_M 0x00000007
#define AR_SREV_REVISION_S 0
@@ -1339,6 +1342,9 @@
(sc)->sc_mac_rev >= AR_SREV_REVISION_5416_22) || \
(sc)->sc_mac_ver >= AR_SREV_VERSION_9100)
+#define AR_SREV_9100(sc) \
+ ((sc->sc_mac_ver) == AR_SREV_VERSION_9100)
+
#define AR_SREV_9160(sc) \
((sc)->sc_mac_ver == AR_SREV_VERSION_9160)
#define AR_SREV_9160_10_OR_LATER(sc) \
--
2.8.2
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