ps2 tools (needs to be gcc.old)

gistfile1.txt

We do have prefetch, ldc1, sdc1.
stop whining about double float, it requires changing the
status register to enable it.

Index: binutils/dist/gas/config/tc-mips.c
===================================================================
RCS file: /cvsroot/src/external/gpl3/binutils/dist/gas/config/tc-mips.c,v
retrieving revision 1.19
diff -u -r1.19 tc-mips.c
--- binutils/dist/gas/config/tc-mips.c	26 Oct 2016 18:42:55 -0000	1.19
+++ binutils/dist/gas/config/tc-mips.c	17 Jan 2018 19:43:03 -0000
@@ -518,7 +518,7 @@
 
 /* True, if CPU has support for ldc1 and sdc1. */
 #define CPU_HAS_LDC1_SDC1(CPU)	\
-   ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
+   ((mips_opts.isa != ISA_MIPS1))
 
 /* True if mflo and mfhi can be immediately followed by instructions
    which write to the HI and LO registers.
Index: gcc/dist/gcc/config/mips/mips.c
===================================================================
RCS file: /cvsroot/src/external/gpl3/gcc/dist/gcc/config/mips/mips.c,v
retrieving revision 1.6
diff -u -r1.6 mips.c
--- gcc/dist/gcc/config/mips/mips.c	24 Jan 2016 09:43:33 -0000	1.6
+++ gcc/dist/gcc/config/mips/mips.c	17 Jan 2018 19:43:16 -0000
@@ -17433,11 +17433,6 @@
 
   /* End of code shared with GAS.  */
 
-  /* The R5900 FPU only supports single precision.  */
-  if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
-    error ("unsupported combination: %s",
-	   "-march=r5900 -mhard-float -mdouble-float");
-
   /* If a -mlong* option was given, check that it matches the ABI,
      otherwise infer the -mlong* setting from the other options.  */
   if ((target_flags_explicit & MASK_LONG64) != 0)
Index: gcc/dist/gcc/config/mips/mips.h
===================================================================
RCS file: /cvsroot/src/external/gpl3/gcc/dist/gcc/config/mips/mips.h,v
retrieving revision 1.1.1.3
diff -u -r1.1.1.3 mips.h
--- gcc/dist/gcc/config/mips/mips.h	24 Jan 2016 06:06:28 -0000	1.1.1.3
+++ gcc/dist/gcc/config/mips/mips.h	17 Jan 2018 19:43:18 -0000
@@ -948,7 +948,6 @@
 
 /* ISA has LDC1 and SDC1.  */
 #define ISA_HAS_LDC1_SDC1	(!ISA_MIPS1				\
-				 && !TARGET_MIPS5900			\
 				 && !TARGET_MIPS16)
 
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
@@ -1091,7 +1090,6 @@
 /* ISA has data prefetch instructions.  This controls use of 'pref'.  */
 #define ISA_HAS_PREFETCH	((ISA_MIPS4				\
 				  || TARGET_LOONGSON_2EF		\
-				  || TARGET_MIPS5900			\
 				  || mips_isa_rev >= 1)			\
 				 && !TARGET_MIPS16)