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coypoop/gist:73974221cafe7e32d9d9c871fe2c7e66

Created June 9, 2016 07:09
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gistfile1.txt
From 42a99999e1cc44e0ccef31ab22d6f2bbcc136c99 Mon Sep 17 00:00:00 2001
From: coypu <coypu@sdf.org>
Date: Thu, 9 Jun 2016 10:08:03 +0300
Subject: [PATCH 1/1] Sprinkle AR9430 specific redefinitions
Adjust code to pass sc.
---
sys/dev/ic/arn5008.c | 16 ++++++++--------
sys/dev/ic/arn9003.c | 12 ++++++------
sys/dev/ic/athn.c | 32 ++++++++++++++++----------------
sys/dev/ic/athnreg.h | 18 +++++++++++-------
4 files changed, 41 insertions(+), 37 deletions(-)
diff --git a/sys/dev/ic/arn5008.c b/sys/dev/ic/arn5008.c
index 5f8d598..f5f3905 100644
--- a/sys/dev/ic/arn5008.c
+++ b/sys/dev/ic/arn5008.c
@@ -1183,19 +1183,19 @@ ar5008_intr(struct athn_softc *sc)
uint32_t intr, intr5, sync;
/* Get pending interrupts. */
- intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
+ intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE(sc));
if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
- intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ intr = AR_READ(sc, AR_INTR_SYNC_CAUSE(sc));
if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0)
return 0; /* Not for us. */
}
- if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+ if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE(sc)) & AR_INTR_MAC_IRQ) &&
(AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
intr = AR_READ(sc, AR_ISR);
else
intr = 0;
- sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync;
+ sync = AR_READ(sc, AR_INTR_SYNC_CAUSE(sc)) & sc->sc_isync;
if (intr == 0 && sync == 0)
return 0; /* Not for us. */
@@ -1257,13 +1257,13 @@ ar5008_intr(struct athn_softc *sc)
if ((sc->sc_flags & ATHN_FLAG_RFSILENT) &&
(sync & AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin))) {
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
- (void)AR_READ(sc, AR_INTR_SYNC_ENABLE);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), 0);
+ (void)AR_READ(sc, AR_INTR_SYNC_ENABLE(sc));
pmf_event_inject(sc->sc_dev, PMFE_RADIO_OFF);
}
- AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
- (void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE(sc), sync);
+ (void)AR_READ(sc, AR_INTR_SYNC_CAUSE(sc));
}
return 1;
}
diff --git a/sys/dev/ic/arn9003.c b/sys/dev/ic/arn9003.c
index e539930..2ba24af 100644
--- a/sys/dev/ic/arn9003.c
+++ b/sys/dev/ic/arn9003.c
@@ -1342,19 +1342,19 @@ ar9003_intr(struct athn_softc *sc)
uint32_t intr, sync;
/* Get pending interrupts. */
- intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
+ intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE(sc));
if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
- intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ intr = AR_READ(sc, AR_INTR_SYNC_CAUSE(sc));
if (intr == AR_INTR_SPURIOUS || (intr & sc->sc_isync) == 0)
return 0; /* Not for us. */
}
- if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+ if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE(sc)) & AR_INTR_MAC_IRQ) &&
(AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
intr = AR_READ(sc, AR_ISR);
else
intr = 0;
- sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->sc_isync;
+ sync = AR_READ(sc, AR_INTR_SYNC_CAUSE(sc)) & sc->sc_isync;
if (intr == 0 && sync == 0)
return 0; /* Not for us. */
@@ -1416,8 +1416,8 @@ ar9003_intr(struct athn_softc *sc)
return 1;
}
- AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
- (void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE(sc), sync);
+ (void)AR_READ(sc, AR_INTR_SYNC_CAUSE(sc));
}
return 1;
}
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index af9028b..19bb35d 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -651,9 +651,9 @@ athn_reset(struct athn_softc *sc, int cold_reset)
AR_WRITE(sc, AR_RTC_FORCE_WAKE,
AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
- if (AR_READ(sc, AR_INTR_SYNC_CAUSE) &
+ if (AR_READ(sc, AR_INTR_SYNC_CAUSE(sc)) &
(AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), 0);
AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |
(!AR_SREV_9300_10_OR_LATER(sc) ? AR_RC_AHB : 0));
}
@@ -805,7 +805,7 @@ athn_config_pcie(struct athn_softc *sc)
DELAY(1000);
/* Allow forcing of PCIe core into L1 state. */
- AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+ AR_SETBITS(sc, AR_PCIE_PM_CTRL(sc), AR_PCIE_PM_CTRL_ENA);
#ifndef ATHN_PCIE_WAEN
AR_WRITE(sc, AR_WA, sc->sc_workaround);
@@ -2097,11 +2097,11 @@ athn_enable_interrupts(struct athn_softc *sc)
AR_WRITE(sc, AR_IER, AR_IER_ENABLE);
- AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
- AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+ AR_WRITE(sc, AR_INTR_ASYNC_ENABLE(sc), AR_INTR_MAC_IRQ);
+ AR_WRITE(sc, AR_INTR_ASYNC_MASK(sc), AR_INTR_MAC_IRQ);
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
- AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), sc->sc_isync);
+ AR_WRITE(sc, AR_INTR_SYNC_MASK(sc), sc->sc_isync);
AR_WRITE_BARRIER(sc);
}
@@ -2112,11 +2112,11 @@ athn_disable_interrupts(struct athn_softc *sc)
AR_WRITE(sc, AR_IER, 0);
(void)AR_READ(sc, AR_IER);
- AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0);
- (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE);
+ AR_WRITE(sc, AR_INTR_ASYNC_ENABLE(sc), 0);
+ (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE(sc));
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
- (void)AR_READ(sc, AR_INTR_SYNC_ENABLE);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), 0);
+ (void)AR_READ(sc, AR_INTR_SYNC_ENABLE(sc));
AR_WRITE(sc, AR_IMR, 0);
@@ -2311,12 +2311,12 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *curchan,
#endif
AR_WRITE(sc, AR_IMR, sc->sc_imask);
AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT);
- AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE(sc), 0xffffffff);
sc->sc_isync = AR_INTR_SYNC_DEFAULT;
if (sc->sc_flags & ATHN_FLAG_RFSILENT)
sc->sc_isync |= AR_INTR_SYNC_GPIO_PIN(sc->sc_rfsilent_pin);
- AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
- AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
+ AR_WRITE(sc, AR_INTR_SYNC_ENABLE(sc), sc->sc_isync);
+ AR_WRITE(sc, AR_INTR_SYNC_MASK(sc), 0);
if (AR_SREV_9300_10_OR_LATER(sc)) {
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0);
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0);
@@ -2940,8 +2940,8 @@ athn_stop(struct ifnet *ifp, int disable)
/* Disable interrupts. */
athn_disable_interrupts(sc);
/* Acknowledge interrupts (avoids interrupt storms). */
- AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
- AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
+ AR_WRITE(sc, AR_INTR_SYNC_CAUSE(sc), 0xffffffff);
+ AR_WRITE(sc, AR_INTR_SYNC_MASK(sc), 0);
for (qid = 0; qid < ATHN_QID_COUNT; qid++)
athn_stop_tx_dma(sc, qid);
diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h
index 5fdc6e9..b091719 100644
--- a/sys/dev/ic/athnreg.h
+++ b/sys/dev/ic/athnreg.h
@@ -98,17 +98,17 @@
#define AR_RC 0x4000
#define AR_WA 0x4004
#define AR_PM_STATE 0x4008
-#define AR_PCIE_PM_CTRL 0x4014
+#define AR_PCIE_PM_CTRL(sc) (AR_SREV_9340(sc) ? 0x4004 : 0x4014)
#define AR_HOST_TIMEOUT 0x4018
#define AR_EEPROM 0x401c
#define AR_SREV 0x4020
#define AR_AHB_MODE 0x4024
-#define AR_INTR_SYNC_CAUSE 0x4028
-#define AR_INTR_SYNC_ENABLE 0x402c
-#define AR_INTR_ASYNC_MASK 0x4030
-#define AR_INTR_SYNC_MASK 0x4034
-#define AR_INTR_ASYNC_CAUSE 0x4038
-#define AR_INTR_ASYNC_ENABLE 0x403c
+#define AR_INTR_SYNC_CAUSE(sc) (AR_SREV_9340(sc) ? 0x4010 : 0x4028)
+#define AR_INTR_SYNC_ENABLE(sc) (AR_SREV_9340(sc) ? 0x4014 : 0x402c)
+#define AR_INTR_ASYNC_MASK(sc) (AR_SREV_9340(sc) ? 0x4018 : 0x4030)
+#define AR_INTR_SYNC_MASK(sc) (AR_SREV_9340(sc) ? 0x401c : 0x4034)
+#define AR_INTR_ASYNC_CAUSE(sc) (AR_SREV_9340(sc) ? 0x4020 : 0x4038)
+#define AR_INTR_ASYNC_ENABLE(sc) (AR_SREV_9340(sc) ? 0x4024 : 0x403c)
#define AR_PCIE_SERDES 0x4040
#define AR_PCIE_SERDES2 0x4044
#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4
@@ -792,6 +792,7 @@
#define AR_SREV_VERSION_9300 0x1c0
#define AR_SREV_REVISION_9300_10 0
#define AR_SREV_REVISION_9300_20 2
+#define AR_SREV_VERSION_9340 0x300
#define AR_SREV_VERSION_9485 0x240
#define AR_SREV_REVISION_9485_10 0
@@ -1406,6 +1407,9 @@
((sc)->sc_mac_ver > AR_SREV_VERSION_9287 || \
(AR_SREV_9287(sc) && (sc)->sc_mac_rev >= AR_SREV_REVISION_9287_13))
+#define AR_SREV_9340(sc) \
+ (((sc)->sc_mac_ver == AR_SREV_VERSION_9340))
+
#define AR_SREV_9300(sc) \
((sc)->sc_mac_ver == AR_SREV_VERSION_9300)
#define AR_SREV_9300_10_OR_LATER(sc) \
--
2.8.2
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