ps2 sys wip

gistfile1.txt

Index: arch/mips/mips/locore_mips3.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/locore_mips3.S,v
retrieving revision 1.113
diff -u -r1.113 locore_mips3.S
--- arch/mips/mips/locore_mips3.S	27 Jul 2016 09:32:35 -0000	1.113
+++ arch/mips/mips/locore_mips3.S	18 Jan 2018 21:28:29 -0000
@@ -127,7 +127,7 @@
 	.set	mips3
 #endif
 
-#ifdef _LP64
+#ifdef _LP64 && 0 /* XXX 64bit CP0 functions */
 #define	_MFC0	dmfc0
 #define	_MTC0	dmtc0
 #else
@@ -701,7 +701,7 @@
  * and ASID bits are implemented.  Assumes that interrupts are disabled.
  */
 LEAF(mips3_cp0_tlb_entry_hi_probe)
-	dmfc0	t0, MIPS_COP_0_TLB_HI
+	mfc0	t0, MIPS_COP_0_TLB_HI # XXX R5900 only mfc0
 	li	v0, -1		/* all 1s */
 #if defined(__mips_isa_rev) && __mips_isa_rev >= 2
 	dinsu	v0, zero, 62, 2
@@ -709,10 +709,10 @@
 	dsll	v0, v0, 2	/* except the top 2 */
 	dsrl	v0, v0, 2
 #endif
-	dmtc0	v0, MIPS_COP_0_TLB_HI
+	mtc0	v0, MIPS_COP_0_TLB_HI
 	COP0_SYNC
-	dmfc0	v0, MIPS_COP_0_TLB_HI
-	dmtc0	t0, MIPS_COP_0_TLB_HI
+	mfc0	v0, MIPS_COP_0_TLB_HI
+	mtc0	t0, MIPS_COP_0_TLB_HI
 	COP0_SYNC
 	nop
 #ifdef __mips_o32
@@ -738,12 +738,12 @@
  * PA bits are implemented.  Assumes that interrupts are disabled.
  */
 LEAF(mips3_cp0_tlb_entry_lo_probe)
-	dmfc0	t0, MIPS_COP_0_TLB_LO0
+	mfc0	t0, MIPS_COP_0_TLB_LO0
 	li	v0, -64		/* all 1s except low 6 bits */
-	dmtc0	v0, MIPS_COP_0_TLB_LO0
+	mtc0	v0, MIPS_COP_0_TLB_LO0
 	COP0_SYNC
-	dmfc0	v0, MIPS_COP_0_TLB_LO0
-	dmtc0	t0, MIPS_COP_0_TLB_LO0
+	mfc0	v0, MIPS_COP_0_TLB_LO0
+	mtc0	t0, MIPS_COP_0_TLB_LO0
 	COP0_SYNC
 #ifdef __mips_o32
 #if BYTE_ORDER == BIG_ENDIAN
Index: arch/mips/mips/mipsX_subr.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mipsX_subr.S,v
retrieving revision 1.104
diff -u -r1.104 mipsX_subr.S
--- arch/mips/mips/mipsX_subr.S	20 Aug 2017 09:47:13 -0000	1.104
+++ arch/mips/mips/mipsX_subr.S	18 Jan 2018 21:28:30 -0000
@@ -219,7 +219,7 @@
 /*
  * Use correct-sized m?c0/dm?c0 opcodes.
  */
-#if defined(USE_64BIT_CP0_FUNCTIONS)
+#if defined(USE_64BIT_CP0_FUNCTIONS) && 0
 #define	_MFC0	dmfc0
 #define	_MTC0	dmtc0
 #else
Index: arch/mips/mips/mips_fpu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mips_fpu.c,v
retrieving revision 1.15
diff -u -r1.15 mips_fpu.c
--- arch/mips/mips/mips_fpu.c	7 May 2017 05:45:07 -0000	1.15
+++ arch/mips/mips/mips_fpu.c	18 Jan 2018 21:28:30 -0000
@@ -119,7 +119,7 @@
 	 * save FPCSR and FP register values.
 	 */
 #if !defined(__mips_soft_float)
-#if !defined(__mips_o32)
+#if 0 /* XXX */
 	if (tf->tf_regs[_R_SR] & MIPS3_SR_FR) {
 		KASSERT(_MIPS_SIM_NEWABI_P(l->l_proc->p_md.md_abi));
 		fp[32] = fpcsr;
@@ -249,7 +249,7 @@
 	 * load FP registers and establish processes' FP context.
 	 */
 #if !defined(__mips_soft_float)
-#if !defined(__mips_o32)
+#if 0 /* XXX */
 	if (tf->tf_regs[_R_SR] & MIPS3_SR_FR) {
 		KASSERT(_MIPS_SIM_NEWABI_P(l->l_proc->p_md.md_abi));
 		__asm volatile (
Index: arch/playstation2/conf/Makefile.playstation2.inc
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/conf/Makefile.playstation2.inc,v
retrieving revision 1.10
diff -u -r1.10 Makefile.playstation2.inc
--- arch/playstation2/conf/Makefile.playstation2.inc	28 Mar 2016 10:31:45 -0000	1.10
+++ arch/playstation2/conf/Makefile.playstation2.inc	18 Jan 2018 21:28:31 -0000
@@ -1,5 +1,8 @@
 #	$NetBSD: Makefile.playstation2.inc,v 1.10 2016/03/28 10:31:45 martin Exp $
 
 # Playstation2 uses 128 bit access, which currently requires n32 ABI
-CFLAGS+= -mabi=n32 -march=r5900 -fno-pic -msoft-float
-AFLAGS+= -mabi=n32 -march=r5900 -fno-pic -msoft-float
+CFLAGS+= -march=r5900 -fno-pic -msoft-float
+AFLAGS+= -march=r5900 -fno-pic -msoft-float
+
+CFLAGS+=	-mabi=n32
+AFLAGS+=	-mabi=n32
Index: arch/playstation2/conf/std.playstation2
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/conf/std.playstation2,v
retrieving revision 1.11
diff -u -r1.11 std.playstation2
--- arch/playstation2/conf/std.playstation2	31 Mar 2014 11:43:53 -0000	1.11
+++ arch/playstation2/conf/std.playstation2	18 Jan 2018 21:28:31 -0000
@@ -9,7 +9,7 @@
 
 options 	IPL_ICU_MASK
 
-options 	NOFPU		# Don't use FPU (R5900 FPU is single float only)
+options 	NOFPU		# Don't use FPU
 options 	SOFTFLOAT	# emulate FPU insn
 
 options 	EXEC_ELF32	# exec ELF32 binaries
Index: arch/playstation2/dev/sbus.c
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/dev/sbus.c,v
retrieving revision 1.17
diff -u -r1.17 sbus.c
--- arch/playstation2/dev/sbus.c	19 Jul 2016 17:04:25 -0000	1.17
+++ arch/playstation2/dev/sbus.c	18 Jan 2018 21:28:31 -0000
@@ -196,7 +196,7 @@
 void
 sbus_intr_disestablish(void *handle)
 {
-	int irq = (int)handle;
+	intptr_t irq = (intptr_t)handle;
 
 	switch (irq) {
 	default:
Index: arch/playstation2/dev/spd.c
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/dev/spd.c,v
retrieving revision 1.13
diff -u -r1.13 spd.c
--- arch/playstation2/dev/spd.c	19 Jul 2016 17:04:25 -0000	1.13
+++ arch/playstation2/dev/spd.c	18 Jan 2018 21:28:31 -0000
@@ -171,7 +171,7 @@
 void
 spd_intr_disestablish(void *handle)
 {
-	int slot = (int)handle;
+	intptr_t slot = (intptr_t)handle;
 
 	KDASSERT(LEGAL_SLOT(slot));
 
Index: arch/playstation2/ee/dmac.c
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/ee/dmac.c,v
retrieving revision 1.12
diff -u -r1.12 dmac.c
--- arch/playstation2/ee/dmac.c	31 Mar 2014 11:25:49 -0000	1.12
+++ arch/playstation2/ee/dmac.c	18 Jan 2018 21:28:31 -0000
@@ -237,7 +237,7 @@
 void
 dmac_intr_disestablish(void *handle)
 {
-	int ch = (int)(handle);
+	intptr_t ch = (intptr_t)handle;
 	struct _ipl_dispatcher *dispatcher = &__dmac_dispatcher[ch];
 	int i, s;
 
Index: arch/playstation2/ee/intc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/ee/intc.c,v
retrieving revision 1.8
diff -u -r1.8 intc.c
--- arch/playstation2/ee/intc.c	31 Mar 2014 11:25:49 -0000	1.8
+++ arch/playstation2/ee/intc.c	18 Jan 2018 21:28:31 -0000
@@ -205,7 +205,7 @@
 void
 intc_intr_disestablish(void *handle)
 {
-	int ch = (int)(handle);
+	intptr_t ch = (intptr_t)handle;
 	struct _ipl_dispatcher *dispatcher = &__intc_dispatcher[ch];
 	u_int32_t bit;
 	int i, s;
Index: arch/playstation2/include/param.h
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/include/param.h,v
retrieving revision 1.10
diff -u -r1.10 param.h
--- arch/playstation2/include/param.h	1 Apr 2014 14:08:50 -0000	1.10
+++ arch/playstation2/include/param.h	18 Jan 2018 21:28:31 -0000
@@ -88,7 +88,6 @@
  * clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple
  * of the hardware page size.
  */
-#define	MSIZE		256		/* size of an mbuf */
 
 #ifndef MCLSHIFT
 #define	MCLSHIFT	11		/* convert bytes to m_buf clusters */
Index: arch/playstation2/playstation2/autoconf.c
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/playstation2/autoconf.c,v
retrieving revision 1.9
diff -u -r1.9 autoconf.c
--- arch/playstation2/playstation2/autoconf.c	4 Jul 2014 07:27:57 -0000	1.9
+++ arch/playstation2/playstation2/autoconf.c	18 Jan 2018 21:28:32 -0000
@@ -40,6 +40,8 @@
 void
 cpu_configure(void)
 {
+	/* Enable all interrupts */
+	(void)splhigh();
 	/*
 	 * During autoconfiguration, SIF BIOS uses DMAC SIF0 interrupt.
 	 * so enable DMAC interrupt here. (EIE | INT1 | IE)
@@ -51,9 +53,6 @@
 
 	if (config_rootfound("mainbus", NULL) == NULL)
 		panic("no mainbus found");
-
-	/* Enable all interrupts */
-	spl0();
 }
 
 void
Index: arch/playstation2/playstation2/interrupt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/playstation2/interrupt.c,v
retrieving revision 1.15
diff -u -r1.15 interrupt.c
--- arch/playstation2/playstation2/interrupt.c	19 Jul 2016 16:39:54 -0000	1.15
+++ arch/playstation2/playstation2/interrupt.c	18 Jan 2018 21:28:32 -0000
@@ -105,7 +105,7 @@
 	evcnt_attach_static(&_playstation2_evcnt.dmac);
 
 	/* install software interrupt handler */
-	intc_intr_establish(I_CH10_TIMER1, IPL_SOFT, timer1_intr, 0);
+	intc_intr_establish(I_CH10_TIMER1, IPL_SOFTCLOCK, timer1_intr, 0);
 	intc_intr_establish(I_CH11_TIMER2, IPL_SOFTCLOCK, timer2_intr, 0);
 
 	/* IPL_SOFTNET and IPL_SOFTSERIAL are shared interrupt. */
@@ -150,6 +150,7 @@
 		(void)splhigh();
 	}
 }
+#if 0
 void
 setsoft(int ipl)
 {
@@ -165,7 +166,7 @@
 	/* kick one shot timer */
 	timer_one_shot(timer_map[ipl]);
 }
-
+#endif
 /*
  * SPL support
  */
@@ -198,7 +199,7 @@
 
 	return (opl);
 }
-
+#if 0
 void
 splset(int npl)
 {
@@ -217,7 +218,7 @@
 	splset(0);
 	_spllower(0);
 }
-
+#endif
 /*
  * SIF BIOS call of interrupt utility.
  */
Index: arch/playstation2/playstation2/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/playstation2/machdep.c,v
retrieving revision 1.33
diff -u -r1.33 machdep.c
--- arch/playstation2/playstation2/machdep.c	6 Nov 2017 03:47:47 -0000	1.33
+++ arch/playstation2/playstation2/machdep.c	18 Jan 2018 21:28:32 -0000
@@ -56,6 +56,9 @@
 #include <machine/bootinfo.h>
 #include <machine/psl.h>
 #include <machine/intr.h>/* hardintr_init */
+
+#include <mips/locore.h>
+
 #include <playstation2/playstation2/sifbios.h>
 #include <playstation2/playstation2/interrupt.h>
 
@@ -87,7 +90,6 @@
 	extern char kernel_text[], edata[], end[];
 	void *kernend;
 	struct pcb *pcb0;
-	vaddr_t v;
 	paddr_t start;
 	size_t size;
 
@@ -95,7 +97,7 @@
 	 * Clear the BSS segment.
 	 */
 	kernend = (void *)mips_round_page(end);
-	memset(edata, 0, kernend - edata);
+	memset(edata, 0, (char *) kernend - edata);
 
 	/* disable all interrupt */
 	interrupt_init_bootstrap();
@@ -119,7 +121,7 @@
 	 * Initialize locore-function vector.
 	 * Clear out the I and D caches.
 	 */
-	mips_vector_init();
+	mips_vector_init(NULL, false);
 
 	/*
 	 * Load the rest of the available pages into the VM system.
@@ -127,7 +129,7 @@
 	start = (paddr_t)round_page(MIPS_KSEG0_TO_PHYS(kernend));
 	size = PS2_MEMORY_SIZE - start - BOOTINFO_BLOCK_SIZE;
 	memset((void *)MIPS_PHYS_TO_KSEG1(start), 0, size);
-	    
+
 	/* kernel itself */
 	mem_clusters[0].start = trunc_page(MIPS_KSEG0_TO_PHYS(kernel_text));
 	mem_clusters[0].size = start - mem_clusters[0].start;
@@ -135,11 +137,11 @@
 	mem_clusters[1].start = start;
 	mem_clusters[1].size = size;
 	/* load */
-	printf("load memory %#lx, %#x\n", start, size);
+	printf("load memory %#lx, %#lx\n", start, size);
 	uvm_page_physload(atop(start), atop(start + size),
 	    atop(start), atop(start + size), VM_FREELIST_DEFAULT);
 
-	strcpy(cpu_model, "SONY PlayStation 2");
+	cpu_setmodel("SONY PlayStation 2");
 
 	/*
 	 * Initialize error message buffer (at end of core).
@@ -151,15 +153,12 @@
 	/*
 	 * Allocate uarea page for lwp0 and set it.
 	 */
-	v = uvm_pageboot_alloc(USPACE);
+	mips_init_lwp0_uarea();
 
-	pcb0 = lwp_getpcb(&lwp0);
-	pcb0->pcb_context[11] = PSL_LOWIPL;	/* SR */
 #ifdef IPL_ICU_MASK
+	pcb0 = lwp_getpcb(&lwp0);
 	pcb0->pcb_ppl = 0;
 #endif
-
-	lwp0.l_md.md_regs = (struct frame *)(v + USPACE) - 1
 }
 
 /*
Index: arch/playstation2/playstation2/sifbios.c
===================================================================
RCS file: /cvsroot/src/sys/arch/playstation2/playstation2/sifbios.c,v
retrieving revision 1.11
diff -u -r1.11 sifbios.c
--- arch/playstation2/playstation2/sifbios.c	31 Mar 2014 11:25:49 -0000	1.11
+++ arch/playstation2/playstation2/sifbios.c	18 Jan 2018 21:28:32 -0000
@@ -52,7 +52,7 @@
 #define SIFBIOS_SIGNATURE_PTR	MIPS_PHYS_TO_KSEG1(0x00001004)
 #define SIFBIOS_SIGNATURE	(('P' << 0)|('S' << 8)|('2' << 16)|('b' << 24))
 
-STATIC int (*__sifbios_call)(int, void *);
+STATIC intptr_t (*__sifbios_call)(int, void *);
 #define CALL(t, n, a)	((t)(*__sifbios_call)((n), (void *)(a)))
 
 STATIC void sifbios_rpc_callback(void *, int);
@@ -64,8 +64,8 @@
 	/* check BIOS exits */
 	if (*(u_int32_t *)SIFBIOS_SIGNATURE_PTR != SIFBIOS_SIGNATURE)
 		panic("SIFBIOS not found");
-	
-	__sifbios_call = *((int (**)(int, void*))SIFBIOS_ENTRY_PTR);
+
+	__sifbios_call = *((intptr_t (**)(int, void*))SIFBIOS_ENTRY_PTR);
 }
 
 int