HDMI2USB Frequency Counter Patch

0001-Add-test-frequency-counters-using-minispartan6-board.patch

From 853153920e7f2d4b6e5bf311a57c2c3184036909 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Wed, 27 Jan 2016 10:49:45 -0500
Subject: [PATCH] Add test frequency counters using minispartan6 board.

---
 gateware/freq_count.py       | 55 ++++++++++++++++++++++++++++++++++++++++++++
 targets/minispartan6_base.py | 34 +++++++++++++++++++++++++++
 2 files changed, 89 insertions(+)
 create mode 100644 gateware/freq_count.py

diff --git a/gateware/freq_count.py b/gateware/freq_count.py
new file mode 100644
index 0000000..81f1bc8
--- /dev/null
+++ b/gateware/freq_count.py
@@ -0,0 +1,55 @@
+from migen.fhdl.std import *
+from migen.genlib.fifo import AsyncFIFO
+from migen.fhdl.bitcontainer import flen
+from migen.bank.description import *
+
+
+# Allocate room for 3 frequency counters.
+class FreqCounterDebug(Module, AutoCSR):
+    def __init__(self, counter_param_list):
+        for params in counter_param_list:
+            setattr(self.submodules, params[0], FreqCounter(*params[1:]))
+
+
+class FreqCounter(Module, AutoCSR):
+    # measured_sig: Signal to measure frequency
+    # ref_clk: counts up to a gate_time number of cycles. It should be at least 
+    # twice as fast as the maximum frequency of the measured signal to avoid
+    # samples being missed.
+    # self.freq_out is the last measured frequency over the interval.
+    # posedge: If true, edge transitions from low to high count as a frequency event.
+    # Otherwise, high to low transitions count.
+    def __init__(self, measured_sig, ref_clk, gate_time=50000000, posedge=True):
+        self.clock_domains.cd_ref_clk = ClockDomain()
+        self.comb += [self.cd_ref_clk.clk.eq(ref_clk)]
+
+        event = Signal(1)
+        prev_sig = Signal(1)
+        gate_count = Signal(max=gate_time)
+        freq_count = Signal(max=gate_time)
+        self.freq_out = CSRStatus(32)
+        self.freq_cnt = CSRStatus(32)
+        self.gate_cnt = CSRStatus(32)
+
+        self.comb += [self.freq_cnt.status.eq(freq_count)]
+        self.comb += [self.gate_cnt.status.eq(gate_count)]
+
+        self.sync.ref_clk += [prev_sig.eq(measured_sig)]
+
+        if posedge:
+            self.comb += [event.eq(measured_sig & ~prev_sig)]
+        else:
+            self.comb += [event.eq(~measured_sig & prev_sig)]
+
+        # We will latch data into the queue on the leading edge of the next
+        # clock if gate_count has saturated.
+        self.sync.ref_clk += [If(gate_count == gate_time - 1,
+                gate_count.eq(0),
+                freq_count.eq(0),
+                self.freq_out.status.eq(freq_count)).
+            Else(
+                # TODO: We should probably count an edge transition detected
+                # on the leading edge just before the gate_count resets.
+                If(event,
+                    freq_count.eq(freq_count + 1)),
+                gate_count.eq(gate_count + 1))]
diff --git a/targets/minispartan6_base.py b/targets/minispartan6_base.py
index 9342813..4c2fc4d 100644
--- a/targets/minispartan6_base.py
+++ b/targets/minispartan6_base.py
@@ -17,6 +17,10 @@ from liteusb.frontend.wishbone import LiteUSBWishboneBridge
 
 from misoclib.com.gpio import GPIOOut
 
+# Debug stuff
+from gateware.freq_count import FreqCounterDebug
+from migen.genlib.misc import Counter
+
 class _CRG(Module):
     def __init__(self, platform, clk_freq):
         self.clock_domains.cd_sys = ClockDomain()
@@ -86,6 +90,36 @@ class BaseSoC(SDRAMSoC):
             self.register_sdram_phy(self.sdrphy)
 
 
+
+
+# Test SoC for frequency counters.
+class FreqSoC(BaseSoC):
+    csr_map = {
+        "freq_counters": 16,
+    }
+    csr_map.update(BaseSoC.csr_map)
+
+    def __init__(self, platform, **kwargs):
+        BaseSoC.__init__(self, platform, **kwargs)
+
+        # Create a clock domain to play with- get some generate signals from here.
+        clk50 = platform.request("clk50")
+        self.clock_domains.cd_clk50 = ClockDomain()
+        self.comb += self.cd_clk50.clk.eq(clk50)
+
+        # 25 MHz out-of-phase signal
+        test_sig25 = Signal(1)
+        self.sync.clk50 += [test_sig25.eq(~test_sig25)]
+        # LOadless CLK50_IBUF
+
+        test_sig40 = Signal(1)
+        self.sync += [test_sig40.eq(~test_sig40)]
+
+        self.submodules.freq_counters = FreqCounterDebug(
+            [("test_sig40", test_sig40, ClockSignal("sys"), 80000000),
+             ("test_sig25", test_sig25, ClockSignal("sys"), 80000000)])
+
+
 class USBSoC(BaseSoC):
     csr_map = {
         "usb_dma": 16,
-- 
2.6.3