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@cr1901
Created January 1, 2019 07:13
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Boneless Formal Example
# Generated by Yosys 0.8+29 (git sha1 d86ea6ba, x86_64-w64-mingw32-g++ 7.3.0 -Os)
autoidx 712
attribute \cells_not_processed 1
attribute \src "boneless.v:3"
module \boneless_formal
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:161$14_CHECK[0:0]$116
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:161$14_EN[0:0]$117
attribute \src "boneless.v:161"
wire $0$formal$boneless.v:161$14_EN[0:0]$563
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:169$15_CHECK[0:0]$118
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:169$15_EN[0:0]$119
attribute \src "boneless.v:169"
wire $0$formal$boneless.v:169$15_EN[0:0]$565
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:173$16_CHECK[0:0]$120
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:173$16_EN[0:0]$121
attribute \src "boneless.v:173"
wire $0$formal$boneless.v:173$16_EN[0:0]$567
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:179$17_CHECK[0:0]$122
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:179$17_EN[0:0]$123
attribute \src "boneless.v:179"
wire $0$formal$boneless.v:179$17_EN[0:0]$569
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:184$18_CHECK[0:0]$124
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:184$18_EN[0:0]$125
attribute \src "boneless.v:184"
wire $0$formal$boneless.v:184$18_EN[0:0]$571
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:185$19_CHECK[0:0]$126
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:185$19_EN[0:0]$127
attribute \src "boneless.v:185"
wire $0$formal$boneless.v:185$19_EN[0:0]$573
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:188$20_CHECK[0:0]$128
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:188$20_EN[0:0]$129
attribute \src "boneless.v:188"
wire $0$formal$boneless.v:188$20_EN[0:0]$575
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:190$21_CHECK[0:0]$130
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:190$21_EN[0:0]$131
attribute \src "boneless.v:190"
wire $0$formal$boneless.v:190$21_EN[0:0]$577
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:192$22_CHECK[0:0]$132
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:192$22_EN[0:0]$133
attribute \src "boneless.v:192"
wire $0$formal$boneless.v:192$22_EN[0:0]$579
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:194$23_CHECK[0:0]$134
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:194$23_EN[0:0]$135
attribute \src "boneless.v:194"
wire $0$formal$boneless.v:194$23_EN[0:0]$581
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:195$24_CHECK[0:0]$136
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:195$24_EN[0:0]$137
attribute \src "boneless.v:195"
wire $0$formal$boneless.v:195$24_EN[0:0]$583
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:227$25_CHECK[0:0]$138
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:227$25_EN[0:0]$139
attribute \src "boneless.v:227"
wire $0$formal$boneless.v:227$25_EN[0:0]$585
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:229$26_CHECK[0:0]$140
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:229$26_EN[0:0]$141
attribute \src "boneless.v:229"
wire $0$formal$boneless.v:229$26_EN[0:0]$587
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:230$27_CHECK[0:0]$142
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:230$27_EN[0:0]$143
attribute \src "boneless.v:230"
wire $0$formal$boneless.v:230$27_EN[0:0]$589
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:231$28_CHECK[0:0]$144
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:231$28_EN[0:0]$145
attribute \src "boneless.v:231"
wire $0$formal$boneless.v:231$28_EN[0:0]$591
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:233$29_CHECK[0:0]$146
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:233$29_EN[0:0]$147
attribute \src "boneless.v:233"
wire $0$formal$boneless.v:233$29_EN[0:0]$593
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:234$30_CHECK[0:0]$148
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:234$30_EN[0:0]$149
attribute \src "boneless.v:234"
wire $0$formal$boneless.v:234$30_EN[0:0]$595
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:235$31_CHECK[0:0]$150
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:235$31_EN[0:0]$151
attribute \src "boneless.v:235"
wire $0$formal$boneless.v:235$31_EN[0:0]$597
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:236$32_CHECK[0:0]$152
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:236$32_EN[0:0]$153
attribute \src "boneless.v:236"
wire $0$formal$boneless.v:236$32_EN[0:0]$599
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:242$33_CHECK[0:0]$154
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:242$33_EN[0:0]$155
attribute \src "boneless.v:242"
wire $0$formal$boneless.v:242$33_EN[0:0]$601
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:243$34_CHECK[0:0]$156
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:243$34_EN[0:0]$157
attribute \src "boneless.v:243"
wire $0$formal$boneless.v:243$34_EN[0:0]$603
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:246$35_CHECK[0:0]$158
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:246$35_EN[0:0]$159
attribute \src "boneless.v:246"
wire $0$formal$boneless.v:246$35_EN[0:0]$605
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:249$36_CHECK[0:0]$160
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:249$36_EN[0:0]$161
attribute \src "boneless.v:249"
wire $0$formal$boneless.v:249$36_EN[0:0]$607
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:251$37_CHECK[0:0]$162
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:251$37_EN[0:0]$163
attribute \src "boneless.v:251"
wire $0$formal$boneless.v:251$37_EN[0:0]$609
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:253$38_CHECK[0:0]$164
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:253$38_EN[0:0]$165
attribute \src "boneless.v:253"
wire $0$formal$boneless.v:253$38_EN[0:0]$611
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:255$39_CHECK[0:0]$166
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:255$39_EN[0:0]$167
attribute \src "boneless.v:255"
wire $0$formal$boneless.v:255$39_EN[0:0]$613
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:256$40_CHECK[0:0]$168
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:256$40_EN[0:0]$169
attribute \src "boneless.v:256"
wire $0$formal$boneless.v:256$40_EN[0:0]$615
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:261$41_CHECK[0:0]$170
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:261$41_EN[0:0]$171
attribute \src "boneless.v:261"
wire $0$formal$boneless.v:261$41_EN[0:0]$617
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:262$42_CHECK[0:0]$172
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:262$42_EN[0:0]$173
attribute \src "boneless.v:262"
wire $0$formal$boneless.v:262$42_EN[0:0]$619
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:265$43_CHECK[0:0]$174
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:265$43_EN[0:0]$175
attribute \src "boneless.v:265"
wire $0$formal$boneless.v:265$43_EN[0:0]$621
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:266$44_CHECK[0:0]$176
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:266$44_EN[0:0]$177
attribute \src "boneless.v:266"
wire $0$formal$boneless.v:266$44_EN[0:0]$623
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:269$45_CHECK[0:0]$178
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:269$45_EN[0:0]$179
attribute \src "boneless.v:269"
wire $0$formal$boneless.v:269$45_EN[0:0]$625
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:270$46_CHECK[0:0]$180
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:270$46_EN[0:0]$181
attribute \src "boneless.v:270"
wire $0$formal$boneless.v:270$46_EN[0:0]$627
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:271$47_CHECK[0:0]$182
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:271$47_EN[0:0]$183
attribute \src "boneless.v:271"
wire $0$formal$boneless.v:271$47_EN[0:0]$629
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:272$48_CHECK[0:0]$184
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:272$48_EN[0:0]$185
attribute \src "boneless.v:272"
wire $0$formal$boneless.v:272$48_EN[0:0]$631
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:275$49_CHECK[0:0]$186
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:275$49_EN[0:0]$187
attribute \src "boneless.v:275"
wire $0$formal$boneless.v:275$49_EN[0:0]$633
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:276$50_CHECK[0:0]$188
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:276$50_EN[0:0]$189
attribute \src "boneless.v:276"
wire $0$formal$boneless.v:276$50_EN[0:0]$635
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:277$51_CHECK[0:0]$190
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:277$51_EN[0:0]$191
attribute \src "boneless.v:277"
wire $0$formal$boneless.v:277$51_EN[0:0]$637
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:278$52_CHECK[0:0]$192
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:278$52_EN[0:0]$193
attribute \src "boneless.v:278"
wire $0$formal$boneless.v:278$52_EN[0:0]$639
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:279$53_CHECK[0:0]$194
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:279$53_EN[0:0]$195
attribute \src "boneless.v:279"
wire $0$formal$boneless.v:279$53_EN[0:0]$641
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:282$54_CHECK[0:0]$196
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:282$54_EN[0:0]$197
attribute \src "boneless.v:282"
wire $0$formal$boneless.v:282$54_EN[0:0]$643
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:283$55_CHECK[0:0]$198
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:283$55_EN[0:0]$199
attribute \src "boneless.v:283"
wire $0$formal$boneless.v:283$55_EN[0:0]$645
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:285$56_CHECK[0:0]$200
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:285$56_EN[0:0]$201
attribute \src "boneless.v:285"
wire $0$formal$boneless.v:285$56_EN[0:0]$647
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:286$57_CHECK[0:0]$202
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:286$57_EN[0:0]$203
attribute \src "boneless.v:286"
wire $0$formal$boneless.v:286$57_EN[0:0]$649
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:289$58_CHECK[0:0]$204
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:289$58_EN[0:0]$205
attribute \src "boneless.v:289"
wire $0$formal$boneless.v:289$58_EN[0:0]$651
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:290$59_CHECK[0:0]$206
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:290$59_EN[0:0]$207
attribute \src "boneless.v:290"
wire $0$formal$boneless.v:290$59_EN[0:0]$653
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:293$60_CHECK[0:0]$208
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:293$60_EN[0:0]$209
attribute \src "boneless.v:293"
wire $0$formal$boneless.v:293$60_EN[0:0]$655
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:294$61_CHECK[0:0]$210
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:294$61_EN[0:0]$211
attribute \src "boneless.v:294"
wire $0$formal$boneless.v:294$61_EN[0:0]$657
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:296$62_CHECK[0:0]$212
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:296$62_EN[0:0]$213
attribute \src "boneless.v:296"
wire $0$formal$boneless.v:296$62_EN[0:0]$659
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:298$63_CHECK[0:0]$214
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:298$63_EN[0:0]$215
attribute \src "boneless.v:298"
wire $0$formal$boneless.v:298$63_EN[0:0]$661
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:300$64_CHECK[0:0]$216
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:300$64_EN[0:0]$217
attribute \src "boneless.v:300"
wire $0$formal$boneless.v:300$64_EN[0:0]$663
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:301$65_CHECK[0:0]$218
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:301$65_EN[0:0]$219
attribute \src "boneless.v:301"
wire $0$formal$boneless.v:301$65_EN[0:0]$665
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:311$66_CHECK[0:0]$220
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:311$66_EN[0:0]$221
attribute \src "boneless.v:311"
wire $0$formal$boneless.v:311$66_EN[0:0]$667
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:312$67_CHECK[0:0]$222
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:312$67_EN[0:0]$223
attribute \src "boneless.v:312"
wire $0$formal$boneless.v:312$67_EN[0:0]$669
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:313$68_CHECK[0:0]$224
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:313$68_EN[0:0]$225
attribute \src "boneless.v:313"
wire $0$formal$boneless.v:313$68_EN[0:0]$671
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:314$69_CHECK[0:0]$226
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:314$69_EN[0:0]$227
attribute \src "boneless.v:314"
wire $0$formal$boneless.v:314$69_EN[0:0]$673
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:315$70_CHECK[0:0]$228
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:315$70_EN[0:0]$229
attribute \src "boneless.v:315"
wire $0$formal$boneless.v:315$70_EN[0:0]$675
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:316$71_CHECK[0:0]$230
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:316$71_EN[0:0]$231
attribute \src "boneless.v:316"
wire $0$formal$boneless.v:316$71_EN[0:0]$677
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:317$72_CHECK[0:0]$232
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:317$72_EN[0:0]$233
attribute \src "boneless.v:317"
wire $0$formal$boneless.v:317$72_EN[0:0]$679
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:320$73_CHECK[0:0]$234
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:320$73_EN[0:0]$235
attribute \src "boneless.v:320"
wire $0$formal$boneless.v:320$73_EN[0:0]$681
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:321$74_CHECK[0:0]$236
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:321$74_EN[0:0]$237
attribute \src "boneless.v:321"
wire $0$formal$boneless.v:321$74_EN[0:0]$683
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:322$75_CHECK[0:0]$238
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:322$75_EN[0:0]$239
attribute \src "boneless.v:322"
wire $0$formal$boneless.v:322$75_EN[0:0]$685
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:323$76_CHECK[0:0]$240
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:323$76_EN[0:0]$241
attribute \src "boneless.v:323"
wire $0$formal$boneless.v:323$76_EN[0:0]$687
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:326$77_CHECK[0:0]$242
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:326$77_EN[0:0]$243
attribute \src "boneless.v:326"
wire $0$formal$boneless.v:326$77_EN[0:0]$689
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:327$78_CHECK[0:0]$244
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:327$78_EN[0:0]$245
attribute \src "boneless.v:327"
wire $0$formal$boneless.v:327$78_EN[0:0]$691
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:328$79_CHECK[0:0]$246
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:328$79_EN[0:0]$247
attribute \src "boneless.v:328"
wire $0$formal$boneless.v:328$79_EN[0:0]$693
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:329$80_CHECK[0:0]$248
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:329$80_EN[0:0]$249
attribute \src "boneless.v:329"
wire $0$formal$boneless.v:329$80_EN[0:0]$695
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:332$81_CHECK[0:0]$250
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:332$81_EN[0:0]$251
attribute \src "boneless.v:332"
wire $0$formal$boneless.v:332$81_EN[0:0]$697
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:333$82_CHECK[0:0]$252
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:333$82_EN[0:0]$253
attribute \src "boneless.v:333"
wire $0$formal$boneless.v:333$82_EN[0:0]$699
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:334$83_CHECK[0:0]$254
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:334$83_EN[0:0]$255
attribute \src "boneless.v:334"
wire $0$formal$boneless.v:334$83_EN[0:0]$701
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:335$84_CHECK[0:0]$256
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:335$84_EN[0:0]$257
attribute \src "boneless.v:335"
wire $0$formal$boneless.v:335$84_EN[0:0]$703
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:340$85_CHECK[0:0]$258
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:340$85_EN[0:0]$259
attribute \src "boneless.v:340"
wire $0$formal$boneless.v:340$85_EN[0:0]$705
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:341$86_CHECK[0:0]$260
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:341$86_EN[0:0]$261
attribute \src "boneless.v:341"
wire $0$formal$boneless.v:341$86_EN[0:0]$707
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:346$87_CHECK[0:0]$262
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:346$87_EN[0:0]$263
attribute \src "boneless.v:346"
wire $0$formal$boneless.v:346$87_EN[0:0]$709
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:347$88_CHECK[0:0]$264
attribute \src "boneless.v:155"
wire $0$formal$boneless.v:347$88_EN[0:0]$265
attribute \src "boneless.v:347"
wire $0$formal$boneless.v:347$88_EN[0:0]$711
attribute \src "boneless.v:24"
wire width 16 $0$memwr$\ext$boneless.v:26$13_ADDR[15:0]$95
attribute \src "boneless.v:24"
wire width 16 $0$memwr$\ext$boneless.v:26$13_DATA[15:0]$96
attribute \src "boneless.v:24"
wire width 16 $0$memwr$\ext$boneless.v:26$13_EN[15:0]$97
attribute \src "boneless.v:13"
wire width 16 $0$memwr$\mem$boneless.v:15$12_ADDR[15:0]$90
attribute \src "boneless.v:13"
wire width 16 $0$memwr$\mem$boneless.v:15$12_DATA[15:0]$91
attribute \src "boneless.v:13"
wire width 16 $0$memwr$\mem$boneless.v:15$12_EN[15:0]$92
attribute \src "boneless.v:155"
wire width 16 $0$past$boneless.v:265$1$0[15:0]$105
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:266$2$0[3:0]$106
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:272$3$0[3:0]$107
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:279$4$0[3:0]$108
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:290$5$0[3:0]$109
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:301$6$0[3:0]$110
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:323$7$0[3:0]$111
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:329$8$0[3:0]$112
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:335$9$0[3:0]$113
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:341$10$0[3:0]$114
attribute \src "boneless.v:155"
wire width 4 $0$past$boneless.v:347$11$0[3:0]$115
attribute \src "boneless.v:24"
wire width 16 $0\ext_r_data[15:0]
attribute \src "boneless.v:155"
wire $0\fs_jumped[0:0]
attribute \src "boneless.v:155"
wire width 16 $0\fs_next_pc[15:0]
attribute \src "boneless.v:155"
wire $0\fs_past_ext_adr[0:0]
attribute \src "boneless.v:155"
wire $0\fs_past_ext_r_en[0:0]
attribute \src "boneless.v:155"
wire $0\fs_past_ext_w_en[0:0]
attribute \src "boneless.v:13"
wire width 16 $0\mem_r_data[15:0]
attribute \src "boneless.v:44"
wire width 13 $0\r_win[12:0]
attribute \src "boneless.v:155"
wire width 17 $0\stb.addi.res[16:0]
attribute \src "boneless.v:155"
wire width 16 $0\stb.addi.tmp[15:0]
attribute \src "boneless.v:155"
wire $0\stb.addi.v[0:0]
attribute \src "boneless.v:155"
wire $0\stb.arith.c[0:0]
attribute \src "boneless.v:155"
wire width 17 $0\stb.arith.res[16:0]
attribute \src "boneless.v:155"
wire $0\stb.arith.v[0:0]
attribute \src "boneless.v:151"
wire $1\fs_jumped[0:0]
attribute \src "boneless.v:154"
wire $1\fs_past_ext_adr[0:0]
attribute \src "boneless.v:152"
wire $1\fs_past_ext_r_en[0:0]
attribute \src "boneless.v:153"
wire $1\fs_past_ext_w_en[0:0]
attribute \src "boneless.v:155"
wire width 17 $1\stb.addi.res[16:0]
attribute \src "boneless.v:155"
wire width 16 $1\stb.addi.tmp[15:0]
attribute \src "boneless.v:155"
wire $1\stb.addi.v[0:0]
attribute \src "boneless.v:155"
wire $1\stb.arith.c[0:0]
attribute \src "boneless.v:155"
wire width 17 $1\stb.arith.res[16:0]
attribute \src "boneless.v:155"
wire $1\stb.arith.v[0:0]
attribute \src "boneless.v:155"
wire width 17 $2\stb.addi.res[16:0]
attribute \src "boneless.v:155"
wire width 16 $2\stb.addi.tmp[15:0]
attribute \src "boneless.v:155"
wire $2\stb.addi.v[0:0]
attribute \src "boneless.v:155"
wire $2\stb.arith.c[0:0]
attribute \src "boneless.v:155"
wire width 17 $2\stb.arith.res[16:0]
attribute \src "boneless.v:155"
wire $2\stb.arith.v[0:0]
attribute \src "boneless.v:155"
wire $3\stb.arith.c[0:0]
attribute \src "boneless.v:155"
wire width 17 $3\stb.arith.res[16:0]
attribute \src "boneless.v:155"
wire $3\stb.arith.v[0:0]
attribute \src "boneless.v:207"
wire width 17 $add$boneless.v:207$296_Y
attribute \src "boneless.v:265"
wire width 16 $add$boneless.v:265$371_Y
attribute \src "boneless.v:270"
wire width 16 $add$boneless.v:270$376_Y
attribute \src "boneless.v:278"
wire width 16 $add$boneless.v:278$386_Y
attribute \src "boneless.v:285"
wire width 16 $add$boneless.v:285$393_Y
attribute \src "boneless.v:289"
wire width 16 $add$boneless.v:289$399_Y
attribute \src "boneless.v:300"
wire width 16 $add$boneless.v:300$415_Y
attribute \src "boneless.v:300"
wire width 16 $add$boneless.v:300$416_Y
attribute \src "boneless.v:308"
wire width 17 $add$boneless.v:308$421_Y
attribute \src "boneless.v:322"
wire width 16 $add$boneless.v:322$439_Y
attribute \src "boneless.v:322"
wire width 16 $add$boneless.v:322$440_Y
attribute \src "boneless.v:327"
wire width 16 $add$boneless.v:327$444_Y
attribute \src "boneless.v:327"
wire width 16 $add$boneless.v:327$445_Y
attribute \src "boneless.v:334"
wire width 16 $add$boneless.v:334$452_Y
attribute \src "boneless.v:336"
wire width 16 $add$boneless.v:336$455_Y
attribute \src "boneless.v:336"
wire width 16 $add$boneless.v:336$456_Y
attribute \src "boneless.v:342"
wire width 16 $add$boneless.v:342$461_Y
attribute \src "boneless.v:348"
wire width 16 $add$boneless.v:348$464_Y
attribute \src "boneless.v:348"
wire width 16 $add$boneless.v:348$465_Y
attribute \src "boneless.v:188"
wire width 16 $and$boneless.v:188$280_Y
attribute \src "boneless.v:100"
wire $eq$boneless.v:100$102_Y
attribute \src "boneless.v:101"
wire $eq$boneless.v:101$103_Y
attribute \src "boneless.v:169"
wire $eq$boneless.v:169$271_Y
attribute \src "boneless.v:173"
wire $eq$boneless.v:173$273_Y
attribute \src "boneless.v:179"
wire $eq$boneless.v:179$274_Y
attribute \src "boneless.v:182"
wire $eq$boneless.v:182$275_Y
attribute \src "boneless.v:185"
wire $eq$boneless.v:185$277_Y
attribute \src "boneless.v:188"
wire $eq$boneless.v:188$281_Y
attribute \src "boneless.v:190"
wire $eq$boneless.v:190$285_Y
attribute \src "boneless.v:192"
wire $eq$boneless.v:192$289_Y
attribute \src "boneless.v:194"
wire $eq$boneless.v:194$290_Y
attribute \src "boneless.v:194"
wire $eq$boneless.v:194$291_Y
attribute \src "boneless.v:195"
wire $eq$boneless.v:195$292_Y
attribute \src "boneless.v:202"
wire $eq$boneless.v:202$293_Y
attribute \src "boneless.v:209"
wire $eq$boneless.v:209$301_Y
attribute \src "boneless.v:215"
wire $eq$boneless.v:215$315_Y
attribute \src "boneless.v:221"
wire $eq$boneless.v:221$329_Y
attribute \src "boneless.v:226"
wire $eq$boneless.v:226$335_Y
attribute \src "boneless.v:230"
wire $eq$boneless.v:230$337_Y
attribute \src "boneless.v:231"
wire $eq$boneless.v:231$338_Y
attribute \src "boneless.v:233"
wire $eq$boneless.v:233$339_Y
attribute \src "boneless.v:233"
wire $eq$boneless.v:233$340_Y
attribute \src "boneless.v:234"
wire $eq$boneless.v:234$341_Y
attribute \src "boneless.v:235"
wire $eq$boneless.v:235$342_Y
attribute \src "boneless.v:236"
wire $eq$boneless.v:236$343_Y
attribute \src "boneless.v:241"
wire $eq$boneless.v:241$344_Y
attribute \src "boneless.v:241"
wire $eq$boneless.v:241$345_Y
attribute \src "boneless.v:243"
wire $eq$boneless.v:243$347_Y
attribute \src "boneless.v:246"
wire $eq$boneless.v:246$350_Y
attribute \src "boneless.v:248"
wire width 16 $eq$boneless.v:248$353_Y
attribute \src "boneless.v:251"
wire $eq$boneless.v:251$361_Y
attribute \src "boneless.v:253"
wire $eq$boneless.v:253$364_Y
attribute \src "boneless.v:255"
wire $eq$boneless.v:255$365_Y
attribute \src "boneless.v:255"
wire $eq$boneless.v:255$366_Y
attribute \src "boneless.v:256"
wire $eq$boneless.v:256$367_Y
attribute \src "boneless.v:260"
wire $eq$boneless.v:260$368_Y
attribute \src "boneless.v:262"
wire $eq$boneless.v:262$369_Y
attribute \src "boneless.v:265"
wire $eq$boneless.v:265$372_Y
attribute \src "boneless.v:266"
wire $eq$boneless.v:266$373_Y
attribute \src "boneless.v:268"
wire $eq$boneless.v:268$374_Y
attribute \src "boneless.v:270"
wire $eq$boneless.v:270$377_Y
attribute \src "boneless.v:271"
wire $eq$boneless.v:271$379_Y
attribute \src "boneless.v:272"
wire $eq$boneless.v:272$380_Y
attribute \src "boneless.v:274"
wire $eq$boneless.v:274$381_Y
attribute \src "boneless.v:277"
wire $eq$boneless.v:277$383_Y
attribute \src "boneless.v:278"
wire $eq$boneless.v:278$387_Y
attribute \src "boneless.v:279"
wire $eq$boneless.v:279$388_Y
attribute \src "boneless.v:281"
wire $eq$boneless.v:281$389_Y
attribute \src "boneless.v:285"
wire $eq$boneless.v:285$394_Y
attribute \src "boneless.v:286"
wire $eq$boneless.v:286$396_Y
attribute \src "boneless.v:289"
wire $eq$boneless.v:289$401_Y
attribute \src "boneless.v:290"
wire $eq$boneless.v:290$402_Y
attribute \src "boneless.v:292"
wire $eq$boneless.v:292$403_Y
attribute \src "boneless.v:292"
wire $eq$boneless.v:292$404_Y
attribute \src "boneless.v:292"
wire $eq$boneless.v:292$406_Y
attribute \src "boneless.v:294"
wire $eq$boneless.v:294$408_Y
attribute \src "boneless.v:295"
wire $eq$boneless.v:295$409_Y
attribute \src "boneless.v:296"
wire $eq$boneless.v:296$410_Y
attribute \src "boneless.v:297"
wire $eq$boneless.v:297$411_Y
attribute \src "boneless.v:298"
wire $eq$boneless.v:298$413_Y
attribute \src "boneless.v:299"
wire $eq$boneless.v:299$414_Y
attribute \src "boneless.v:300"
wire $eq$boneless.v:300$417_Y
attribute \src "boneless.v:301"
wire $eq$boneless.v:301$418_Y
attribute \src "boneless.v:303"
wire $eq$boneless.v:303$419_Y
attribute \src "boneless.v:309"
wire $eq$boneless.v:309$424_Y
attribute \src "boneless.v:312"
wire $eq$boneless.v:312$429_Y
attribute \src "boneless.v:313"
wire $eq$boneless.v:313$430_Y
attribute \src "boneless.v:314"
wire $eq$boneless.v:314$431_Y
attribute \src "boneless.v:314"
wire $eq$boneless.v:314$432_Y
attribute \src "boneless.v:315"
wire $eq$boneless.v:315$433_Y
attribute \src "boneless.v:316"
wire $eq$boneless.v:316$434_Y
attribute \src "boneless.v:317"
wire $eq$boneless.v:317$435_Y
attribute \src "boneless.v:319"
wire $eq$boneless.v:319$436_Y
attribute \src "boneless.v:321"
wire $eq$boneless.v:321$437_Y
attribute \src "boneless.v:322"
wire $eq$boneless.v:322$441_Y
attribute \src "boneless.v:323"
wire $eq$boneless.v:323$442_Y
attribute \src "boneless.v:325"
wire $eq$boneless.v:325$443_Y
attribute \src "boneless.v:327"
wire $eq$boneless.v:327$446_Y
attribute \src "boneless.v:328"
wire $eq$boneless.v:328$448_Y
attribute \src "boneless.v:329"
wire $eq$boneless.v:329$449_Y
attribute \src "boneless.v:331"
wire $eq$boneless.v:331$450_Y
attribute \src "boneless.v:333"
wire $eq$boneless.v:333$451_Y
attribute \src "boneless.v:334"
wire $eq$boneless.v:334$453_Y
attribute \src "boneless.v:335"
wire $eq$boneless.v:335$454_Y
attribute \src "boneless.v:339"
wire $eq$boneless.v:339$457_Y
attribute \src "boneless.v:341"
wire $eq$boneless.v:341$459_Y
attribute \src "boneless.v:347"
wire $eq$boneless.v:347$463_Y
attribute \src "boneless.v:350"
wire $eq$boneless.v:350$466_Y
attribute \src "boneless.v:351"
wire $eq$boneless.v:351$467_Y
attribute \src "boneless.v:352"
wire $eq$boneless.v:352$468_Y
attribute \src "boneless.v:353"
wire $eq$boneless.v:353$469_Y
attribute \src "boneless.v:354"
wire $eq$boneless.v:354$470_Y
attribute \src "boneless.v:355"
wire $eq$boneless.v:355$473_Y
attribute \src "boneless.v:356"
wire $eq$boneless.v:356$475_Y
attribute \src "boneless.v:357"
wire $eq$boneless.v:357$478_Y
attribute \src "boneless.v:97"
wire $eq$boneless.v:97$99_Y
attribute \src "boneless.v:98"
wire $eq$boneless.v:98$100_Y
attribute \src "boneless.v:99"
wire $eq$boneless.v:99$101_Y
attribute \src "boneless.v:161"
wire $formal$boneless.v:161$14_CHECK
attribute \src "boneless.v:161"
wire $formal$boneless.v:161$14_EN
attribute \src "boneless.v:169"
wire $formal$boneless.v:169$15_CHECK
attribute \src "boneless.v:169"
wire $formal$boneless.v:169$15_EN
attribute \src "boneless.v:173"
wire $formal$boneless.v:173$16_CHECK
attribute \src "boneless.v:173"
wire $formal$boneless.v:173$16_EN
attribute \src "boneless.v:179"
wire $formal$boneless.v:179$17_CHECK
attribute \src "boneless.v:179"
wire $formal$boneless.v:179$17_EN
attribute \src "boneless.v:184"
wire $formal$boneless.v:184$18_CHECK
attribute \src "boneless.v:184"
wire $formal$boneless.v:184$18_EN
attribute \src "boneless.v:185"
wire $formal$boneless.v:185$19_CHECK
attribute \src "boneless.v:185"
wire $formal$boneless.v:185$19_EN
attribute \src "boneless.v:188"
wire $formal$boneless.v:188$20_CHECK
attribute \src "boneless.v:188"
wire $formal$boneless.v:188$20_EN
attribute \src "boneless.v:190"
wire $formal$boneless.v:190$21_CHECK
attribute \src "boneless.v:190"
wire $formal$boneless.v:190$21_EN
attribute \src "boneless.v:192"
wire $formal$boneless.v:192$22_CHECK
attribute \src "boneless.v:192"
wire $formal$boneless.v:192$22_EN
attribute \src "boneless.v:194"
wire $formal$boneless.v:194$23_CHECK
attribute \src "boneless.v:194"
wire $formal$boneless.v:194$23_EN
attribute \src "boneless.v:195"
wire $formal$boneless.v:195$24_CHECK
attribute \src "boneless.v:195"
wire $formal$boneless.v:195$24_EN
attribute \src "boneless.v:227"
wire $formal$boneless.v:227$25_CHECK
attribute \src "boneless.v:227"
wire $formal$boneless.v:227$25_EN
attribute \src "boneless.v:229"
wire $formal$boneless.v:229$26_CHECK
attribute \src "boneless.v:229"
wire $formal$boneless.v:229$26_EN
attribute \src "boneless.v:230"
wire $formal$boneless.v:230$27_CHECK
attribute \src "boneless.v:230"
wire $formal$boneless.v:230$27_EN
attribute \src "boneless.v:231"
wire $formal$boneless.v:231$28_CHECK
attribute \src "boneless.v:231"
wire $formal$boneless.v:231$28_EN
attribute \src "boneless.v:233"
wire $formal$boneless.v:233$29_CHECK
attribute \src "boneless.v:233"
wire $formal$boneless.v:233$29_EN
attribute \src "boneless.v:234"
wire $formal$boneless.v:234$30_CHECK
attribute \src "boneless.v:234"
wire $formal$boneless.v:234$30_EN
attribute \src "boneless.v:235"
wire $formal$boneless.v:235$31_CHECK
attribute \src "boneless.v:235"
wire $formal$boneless.v:235$31_EN
attribute \src "boneless.v:236"
wire $formal$boneless.v:236$32_CHECK
attribute \src "boneless.v:236"
wire $formal$boneless.v:236$32_EN
attribute \src "boneless.v:242"
wire $formal$boneless.v:242$33_CHECK
attribute \src "boneless.v:242"
wire $formal$boneless.v:242$33_EN
attribute \src "boneless.v:243"
wire $formal$boneless.v:243$34_CHECK
attribute \src "boneless.v:243"
wire $formal$boneless.v:243$34_EN
attribute \src "boneless.v:246"
wire $formal$boneless.v:246$35_CHECK
attribute \src "boneless.v:246"
wire $formal$boneless.v:246$35_EN
attribute \src "boneless.v:249"
wire $formal$boneless.v:249$36_CHECK
attribute \src "boneless.v:249"
wire $formal$boneless.v:249$36_EN
attribute \src "boneless.v:251"
wire $formal$boneless.v:251$37_CHECK
attribute \src "boneless.v:251"
wire $formal$boneless.v:251$37_EN
attribute \src "boneless.v:253"
wire $formal$boneless.v:253$38_CHECK
attribute \src "boneless.v:253"
wire $formal$boneless.v:253$38_EN
attribute \src "boneless.v:255"
wire $formal$boneless.v:255$39_CHECK
attribute \src "boneless.v:255"
wire $formal$boneless.v:255$39_EN
attribute \src "boneless.v:256"
wire $formal$boneless.v:256$40_CHECK
attribute \src "boneless.v:256"
wire $formal$boneless.v:256$40_EN
attribute \src "boneless.v:261"
wire $formal$boneless.v:261$41_CHECK
attribute \src "boneless.v:261"
wire $formal$boneless.v:261$41_EN
attribute \src "boneless.v:262"
wire $formal$boneless.v:262$42_CHECK
attribute \src "boneless.v:262"
wire $formal$boneless.v:262$42_EN
attribute \src "boneless.v:265"
wire $formal$boneless.v:265$43_CHECK
attribute \src "boneless.v:265"
wire $formal$boneless.v:265$43_EN
attribute \src "boneless.v:266"
wire $formal$boneless.v:266$44_CHECK
attribute \src "boneless.v:266"
wire $formal$boneless.v:266$44_EN
attribute \src "boneless.v:269"
wire $formal$boneless.v:269$45_CHECK
attribute \src "boneless.v:269"
wire $formal$boneless.v:269$45_EN
attribute \src "boneless.v:270"
wire $formal$boneless.v:270$46_CHECK
attribute \src "boneless.v:270"
wire $formal$boneless.v:270$46_EN
attribute \src "boneless.v:271"
wire $formal$boneless.v:271$47_CHECK
attribute \src "boneless.v:271"
wire $formal$boneless.v:271$47_EN
attribute \src "boneless.v:272"
wire $formal$boneless.v:272$48_CHECK
attribute \src "boneless.v:272"
wire $formal$boneless.v:272$48_EN
attribute \src "boneless.v:275"
wire $formal$boneless.v:275$49_CHECK
attribute \src "boneless.v:275"
wire $formal$boneless.v:275$49_EN
attribute \src "boneless.v:276"
wire $formal$boneless.v:276$50_CHECK
attribute \src "boneless.v:276"
wire $formal$boneless.v:276$50_EN
attribute \src "boneless.v:277"
wire $formal$boneless.v:277$51_CHECK
attribute \src "boneless.v:277"
wire $formal$boneless.v:277$51_EN
attribute \src "boneless.v:278"
wire $formal$boneless.v:278$52_CHECK
attribute \src "boneless.v:278"
wire $formal$boneless.v:278$52_EN
attribute \src "boneless.v:279"
wire $formal$boneless.v:279$53_CHECK
attribute \src "boneless.v:279"
wire $formal$boneless.v:279$53_EN
attribute \src "boneless.v:282"
wire $formal$boneless.v:282$54_CHECK
attribute \src "boneless.v:282"
wire $formal$boneless.v:282$54_EN
attribute \src "boneless.v:283"
wire $formal$boneless.v:283$55_CHECK
attribute \src "boneless.v:283"
wire $formal$boneless.v:283$55_EN
attribute \src "boneless.v:285"
wire $formal$boneless.v:285$56_CHECK
attribute \src "boneless.v:285"
wire $formal$boneless.v:285$56_EN
attribute \src "boneless.v:286"
wire $formal$boneless.v:286$57_CHECK
attribute \src "boneless.v:286"
wire $formal$boneless.v:286$57_EN
attribute \src "boneless.v:289"
wire $formal$boneless.v:289$58_CHECK
attribute \src "boneless.v:289"
wire $formal$boneless.v:289$58_EN
attribute \src "boneless.v:290"
wire $formal$boneless.v:290$59_CHECK
attribute \src "boneless.v:290"
wire $formal$boneless.v:290$59_EN
attribute \src "boneless.v:293"
wire $formal$boneless.v:293$60_CHECK
attribute \src "boneless.v:293"
wire $formal$boneless.v:293$60_EN
attribute \src "boneless.v:294"
wire $formal$boneless.v:294$61_CHECK
attribute \src "boneless.v:294"
wire $formal$boneless.v:294$61_EN
attribute \src "boneless.v:296"
wire $formal$boneless.v:296$62_CHECK
attribute \src "boneless.v:296"
wire $formal$boneless.v:296$62_EN
attribute \src "boneless.v:298"
wire $formal$boneless.v:298$63_CHECK
attribute \src "boneless.v:298"
wire $formal$boneless.v:298$63_EN
attribute \src "boneless.v:300"
wire $formal$boneless.v:300$64_CHECK
attribute \src "boneless.v:300"
wire $formal$boneless.v:300$64_EN
attribute \src "boneless.v:301"
wire $formal$boneless.v:301$65_CHECK
attribute \src "boneless.v:301"
wire $formal$boneless.v:301$65_EN
attribute \src "boneless.v:311"
wire $formal$boneless.v:311$66_CHECK
attribute \src "boneless.v:311"
wire $formal$boneless.v:311$66_EN
attribute \src "boneless.v:312"
wire $formal$boneless.v:312$67_CHECK
attribute \src "boneless.v:312"
wire $formal$boneless.v:312$67_EN
attribute \src "boneless.v:313"
wire $formal$boneless.v:313$68_CHECK
attribute \src "boneless.v:313"
wire $formal$boneless.v:313$68_EN
attribute \src "boneless.v:314"
wire $formal$boneless.v:314$69_CHECK
attribute \src "boneless.v:314"
wire $formal$boneless.v:314$69_EN
attribute \src "boneless.v:315"
wire $formal$boneless.v:315$70_CHECK
attribute \src "boneless.v:315"
wire $formal$boneless.v:315$70_EN
attribute \src "boneless.v:316"
wire $formal$boneless.v:316$71_CHECK
attribute \src "boneless.v:316"
wire $formal$boneless.v:316$71_EN
attribute \src "boneless.v:317"
wire $formal$boneless.v:317$72_CHECK
attribute \src "boneless.v:317"
wire $formal$boneless.v:317$72_EN
attribute \src "boneless.v:320"
wire $formal$boneless.v:320$73_CHECK
attribute \src "boneless.v:320"
wire $formal$boneless.v:320$73_EN
attribute \src "boneless.v:321"
wire $formal$boneless.v:321$74_CHECK
attribute \src "boneless.v:321"
wire $formal$boneless.v:321$74_EN
attribute \src "boneless.v:322"
wire $formal$boneless.v:322$75_CHECK
attribute \src "boneless.v:322"
wire $formal$boneless.v:322$75_EN
attribute \src "boneless.v:323"
wire $formal$boneless.v:323$76_CHECK
attribute \src "boneless.v:323"
wire $formal$boneless.v:323$76_EN
attribute \src "boneless.v:326"
wire $formal$boneless.v:326$77_CHECK
attribute \src "boneless.v:326"
wire $formal$boneless.v:326$77_EN
attribute \src "boneless.v:327"
wire $formal$boneless.v:327$78_CHECK
attribute \src "boneless.v:327"
wire $formal$boneless.v:327$78_EN
attribute \src "boneless.v:328"
wire $formal$boneless.v:328$79_CHECK
attribute \src "boneless.v:328"
wire $formal$boneless.v:328$79_EN
attribute \src "boneless.v:329"
wire $formal$boneless.v:329$80_CHECK
attribute \src "boneless.v:329"
wire $formal$boneless.v:329$80_EN
attribute \src "boneless.v:332"
wire $formal$boneless.v:332$81_CHECK
attribute \src "boneless.v:332"
wire $formal$boneless.v:332$81_EN
attribute \src "boneless.v:333"
wire $formal$boneless.v:333$82_CHECK
attribute \src "boneless.v:333"
wire $formal$boneless.v:333$82_EN
attribute \src "boneless.v:334"
wire $formal$boneless.v:334$83_CHECK
attribute \src "boneless.v:334"
wire $formal$boneless.v:334$83_EN
attribute \src "boneless.v:335"
wire $formal$boneless.v:335$84_CHECK
attribute \src "boneless.v:335"
wire $formal$boneless.v:335$84_EN
attribute \src "boneless.v:340"
wire $formal$boneless.v:340$85_CHECK
attribute \src "boneless.v:340"
wire $formal$boneless.v:340$85_EN
attribute \src "boneless.v:341"
wire $formal$boneless.v:341$86_CHECK
attribute \src "boneless.v:341"
wire $formal$boneless.v:341$86_EN
attribute \src "boneless.v:346"
wire $formal$boneless.v:346$87_CHECK
attribute \src "boneless.v:346"
wire $formal$boneless.v:346$87_EN
attribute \src "boneless.v:347"
wire $formal$boneless.v:347$88_CHECK
attribute \src "boneless.v:347"
wire $formal$boneless.v:347$88_EN
attribute \src "boneless.v:161"
wire $logic_and$boneless.v:161$269_Y
attribute \src "boneless.v:210"
wire $logic_and$boneless.v:210$305_Y
attribute \src "boneless.v:216"
wire $logic_and$boneless.v:216$319_Y
attribute \src "boneless.v:222"
wire $logic_and$boneless.v:222$333_Y
attribute \src "boneless.v:310"
wire $logic_and$boneless.v:310$428_Y
attribute \src "boneless.v:161"
wire $logic_not$boneless.v:161$267_Y
attribute \src "boneless.v:161"
wire $logic_not$boneless.v:161$268_Y
attribute \src "boneless.v:215"
wire $logic_not$boneless.v:215$314_Y
attribute \src "boneless.v:221"
wire $logic_not$boneless.v:221$328_Y
attribute \src "boneless.v:227"
wire $logic_not$boneless.v:227$336_Y
attribute \src "boneless.v:282"
wire $logic_not$boneless.v:282$390_Y
attribute \src "boneless.v:340"
wire $logic_not$boneless.v:340$458_Y
attribute \src "boneless.v:346"
wire $logic_not$boneless.v:346$462_Y
attribute \src "boneless.v:355"
wire $logic_not$boneless.v:355$471_Y
attribute \src "boneless.v:160"
wire $logic_or$boneless.v:160$266_Y
attribute \src "boneless.v:168"
wire $logic_or$boneless.v:168$270_Y
attribute \src "boneless.v:172"
wire $logic_or$boneless.v:172$272_Y
attribute \src "boneless.v:241"
wire $logic_or$boneless.v:241$346_Y
attribute \src "boneless.v:276"
wire $logic_or$boneless.v:276$382_Y
attribute \src "boneless.v:283"
wire $logic_or$boneless.v:283$391_Y
attribute \src "boneless.v:292"
wire $logic_or$boneless.v:292$405_Y
attribute \src "boneless.v:292"
wire $logic_or$boneless.v:292$407_Y
attribute \src "boneless.v:209"
wire $lt$boneless.v:209$298_Y
attribute \src "boneless.v:209"
wire $lt$boneless.v:209$300_Y
attribute \src "boneless.v:210"
wire $lt$boneless.v:210$303_Y
attribute \src "boneless.v:215"
wire $lt$boneless.v:215$311_Y
attribute \src "boneless.v:215"
wire $lt$boneless.v:215$313_Y
attribute \src "boneless.v:216"
wire $lt$boneless.v:216$317_Y
attribute \src "boneless.v:221"
wire $lt$boneless.v:221$325_Y
attribute \src "boneless.v:221"
wire $lt$boneless.v:221$327_Y
attribute \src "boneless.v:222"
wire $lt$boneless.v:222$331_Y
attribute \src "boneless.v:309"
wire $lt$boneless.v:309$423_Y
attribute \src "boneless.v:310"
wire $lt$boneless.v:310$426_Y
attribute \src "boneless.v:25"
wire width 16 $memrd$\ext$boneless.v:25$98_DATA
attribute \src "boneless.v:278"
wire width 16 $memrd$\ext$boneless.v:278$384_DATA
attribute \src "boneless.v:289"
wire width 16 $memrd$\ext$boneless.v:289$397_DATA
attribute \src "boneless.v:14"
wire width 16 $memrd$\mem$boneless.v:14$93_DATA
attribute \src "boneless.v:188"
wire width 16 $memrd$\mem$boneless.v:188$278_DATA
attribute \src "boneless.v:188"
wire width 16 $memrd$\mem$boneless.v:188$279_DATA
attribute \src "boneless.v:190"
wire width 16 $memrd$\mem$boneless.v:190$282_DATA
attribute \src "boneless.v:190"
wire width 16 $memrd$\mem$boneless.v:190$283_DATA
attribute \src "boneless.v:192"
wire width 16 $memrd$\mem$boneless.v:192$286_DATA
attribute \src "boneless.v:192"
wire width 16 $memrd$\mem$boneless.v:192$287_DATA
attribute \src "boneless.v:207"
wire width 16 $memrd$\mem$boneless.v:207$294_DATA
attribute \src "boneless.v:207"
wire width 16 $memrd$\mem$boneless.v:207$295_DATA
attribute \src "boneless.v:209"
wire width 16 $memrd$\mem$boneless.v:209$297_DATA
attribute \src "boneless.v:209"
wire width 16 $memrd$\mem$boneless.v:209$299_DATA
attribute \src "boneless.v:210"
wire width 16 $memrd$\mem$boneless.v:210$302_DATA
attribute \src "boneless.v:213"
wire width 16 $memrd$\mem$boneless.v:213$306_DATA
attribute \src "boneless.v:213"
wire width 16 $memrd$\mem$boneless.v:213$307_DATA
attribute \src "boneless.v:215"
wire width 16 $memrd$\mem$boneless.v:215$310_DATA
attribute \src "boneless.v:215"
wire width 16 $memrd$\mem$boneless.v:215$312_DATA
attribute \src "boneless.v:216"
wire width 16 $memrd$\mem$boneless.v:216$316_DATA
attribute \src "boneless.v:219"
wire width 16 $memrd$\mem$boneless.v:219$320_DATA
attribute \src "boneless.v:219"
wire width 16 $memrd$\mem$boneless.v:219$321_DATA
attribute \src "boneless.v:221"
wire width 16 $memrd$\mem$boneless.v:221$324_DATA
attribute \src "boneless.v:221"
wire width 16 $memrd$\mem$boneless.v:221$326_DATA
attribute \src "boneless.v:222"
wire width 16 $memrd$\mem$boneless.v:222$330_DATA
attribute \src "boneless.v:246"
wire width 16 $memrd$\mem$boneless.v:246$348_DATA
attribute \src "boneless.v:248"
wire width 16 $memrd$\mem$boneless.v:248$351_DATA
attribute \src "boneless.v:249"
wire width 16 $memrd$\mem$boneless.v:249$354_DATA
attribute \src "boneless.v:251"
wire width 16 $memrd$\mem$boneless.v:251$359_DATA
attribute \src "boneless.v:253"
wire width 16 $memrd$\mem$boneless.v:253$362_DATA
attribute \src "boneless.v:265"
wire width 16 $memrd$\mem$boneless.v:265$370_DATA
attribute \src "boneless.v:265"
wire width 16 $memrd$\mem$boneless.v:265$479_DATA
attribute \src "boneless.v:270"
wire width 16 $memrd$\mem$boneless.v:270$375_DATA
attribute \src "boneless.v:271"
wire width 16 $memrd$\mem$boneless.v:271$378_DATA
attribute \src "boneless.v:278"
wire width 16 $memrd$\mem$boneless.v:278$385_DATA
attribute \src "boneless.v:285"
wire width 16 $memrd$\mem$boneless.v:285$392_DATA
attribute \src "boneless.v:286"
wire width 16 $memrd$\mem$boneless.v:286$395_DATA
attribute \src "boneless.v:289"
wire width 16 $memrd$\mem$boneless.v:289$398_DATA
attribute \src "boneless.v:289"
wire width 16 $memrd$\mem$boneless.v:289$400_DATA
attribute \src "boneless.v:308"
wire width 16 $memrd$\mem$boneless.v:308$420_DATA
attribute \src "boneless.v:309"
wire width 16 $memrd$\mem$boneless.v:309$422_DATA
attribute \src "boneless.v:310"
wire width 16 $memrd$\mem$boneless.v:310$425_DATA
attribute \src "boneless.v:322"
wire width 16 $memrd$\mem$boneless.v:322$438_DATA
attribute \src "boneless.v:328"
wire width 16 $memrd$\mem$boneless.v:328$447_DATA
attribute \src "boneless.v:342"
wire width 16 $memrd$\mem$boneless.v:342$460_DATA
attribute \src "boneless.v:26"
wire width 16 $memwr$\ext$boneless.v:26$13_ADDR
attribute \src "boneless.v:26"
wire width 16 $memwr$\ext$boneless.v:26$13_DATA
attribute \src "boneless.v:26"
wire width 16 $memwr$\ext$boneless.v:26$13_EN
attribute \src "boneless.v:15"
wire width 16 $memwr$\mem$boneless.v:15$12_ADDR
attribute \src "boneless.v:15"
wire width 16 $memwr$\mem$boneless.v:15$12_DATA
attribute \src "boneless.v:15"
wire width 16 $memwr$\mem$boneless.v:15$12_EN
attribute \src "boneless.v:183"
wire $ne$boneless.v:183$276_Y
attribute \src "boneless.v:210"
wire $ne$boneless.v:210$304_Y
attribute \src "boneless.v:216"
wire $ne$boneless.v:216$318_Y
attribute \src "boneless.v:222"
wire $ne$boneless.v:222$332_Y
attribute \src "boneless.v:225"
wire $ne$boneless.v:225$334_Y
attribute \src "boneless.v:310"
wire $ne$boneless.v:310$427_Y
attribute \src "boneless.v:214"
wire $not$boneless.v:214$309_Y
attribute \src "boneless.v:220"
wire $not$boneless.v:220$323_Y
attribute \src "boneless.v:190"
wire width 16 $or$boneless.v:190$284_Y
attribute \src "boneless.v:249"
wire width 16 $or$boneless.v:249$357_Y
attribute \src "boneless.v:355"
wire $or$boneless.v:355$472_Y
attribute \src "boneless.v:357"
wire $or$boneless.v:357$477_Y
attribute \src "boneless.v:265"
wire width 16 $past$boneless.v:265$1$0
attribute \src "boneless.v:266"
wire width 4 $past$boneless.v:266$2$0
attribute \src "boneless.v:272"
wire width 4 $past$boneless.v:272$3$0
attribute \src "boneless.v:279"
wire width 4 $past$boneless.v:279$4$0
attribute \src "boneless.v:290"
wire width 4 $past$boneless.v:290$5$0
attribute \src "boneless.v:301"
wire width 4 $past$boneless.v:301$6$0
attribute \src "boneless.v:323"
wire width 4 $past$boneless.v:323$7$0
attribute \src "boneless.v:329"
wire width 4 $past$boneless.v:329$8$0
attribute \src "boneless.v:335"
wire width 4 $past$boneless.v:335$9$0
attribute \src "boneless.v:341"
wire width 4 $past$boneless.v:341$10$0
attribute \src "boneless.v:347"
wire width 4 $past$boneless.v:347$11$0
attribute \src "boneless.v:249"
wire $reduce_bool$boneless.v:249$358_Y
attribute \src "boneless.v:246"
wire width 16 $shl$boneless.v:246$349_Y
attribute \src "boneless.v:248"
wire width 16 $shl$boneless.v:248$352_Y
attribute \src "boneless.v:298"
wire width 16 $shl$boneless.v:298$412_Y
attribute \src "boneless.v:249"
wire width 16 $shr$boneless.v:249$356_Y
attribute \src "boneless.v:251"
wire width 16 $shr$boneless.v:251$360_Y
attribute \src "boneless.v:253"
wire width 16 $sshr$boneless.v:253$363_Y
attribute \src "boneless.v:213"
wire width 17 $sub$boneless.v:213$308_Y
attribute \src "boneless.v:219"
wire width 17 $sub$boneless.v:219$322_Y
attribute \src "boneless.v:249"
wire width 32 $sub$boneless.v:249$355_Y
attribute \src "boneless.v:192"
wire width 16 $xor$boneless.v:192$288_Y
attribute \src "boneless.v:356"
wire $xor$boneless.v:356$474_Y
attribute \src "boneless.v:357"
wire $xor$boneless.v:357$476_Y
attribute \src "boneless.v:146"
wire width 16 \a_regX
attribute \src "boneless.v:147"
wire width 16 \a_regY
attribute \src "boneless.v:148"
wire width 16 \a_regZ
attribute \src "boneless.v:4"
wire input 1 \clk
attribute \src "boneless.v:19"
wire width 16 \ext_addr
attribute \src "boneless.v:20"
wire width 16 \ext_r_data
attribute \src "boneless.v:21"
wire \ext_r_en
attribute \src "boneless.v:22"
wire width 16 \ext_w_data
attribute \src "boneless.v:23"
wire \ext_w_en
attribute \src "boneless.v:32"
wire \fi_c
attribute \src "boneless.v:37"
wire width 16 \fi_ext_addr
attribute \src "boneless.v:38"
wire width 16 \fi_ext_r_data
attribute \src "boneless.v:39"
wire \fi_ext_r_en
attribute \src "boneless.v:40"
wire width 16 \fi_ext_w_data
attribute \src "boneless.v:41"
wire \fi_ext_w_en
attribute \src "boneless.v:31"
wire width 4 \fi_flags
attribute \src "boneless.v:33"
wire width 16 \fi_insn
attribute \src "boneless.v:34"
wire width 16 \fi_mem_w_addr
attribute \src "boneless.v:35"
wire width 16 \fi_mem_w_data
attribute \src "boneless.v:36"
wire \fi_mem_w_en
attribute \src "boneless.v:30"
wire width 16 \fi_pc
attribute \src "boneless.v:32"
wire \fi_s
attribute \src "boneless.v:29"
wire \fi_stb
attribute \src "boneless.v:32"
wire \fi_v
attribute \src "boneless.v:32"
wire \fi_z
attribute \src "boneless.v:151"
wire \fs_jumped
attribute \src "boneless.v:150"
wire width 16 \fs_next_pc
attribute \src "boneless.v:154"
wire \fs_past_ext_adr
attribute \src "boneless.v:152"
wire \fs_past_ext_r_en
attribute \src "boneless.v:153"
wire \fs_past_ext_w_en
attribute \src "boneless.v:97"
wire \i_clsA
attribute \src "boneless.v:101"
wire \i_clsC
attribute \src "boneless.v:100"
wire \i_clsI
attribute \src "boneless.v:99"
wire \i_clsM
attribute \src "boneless.v:98"
wire \i_clsS
attribute \src "boneless.v:81"
wire \i_code1
attribute \src "boneless.v:82"
wire width 2 \i_code2
attribute \src "boneless.v:83"
wire width 3 \i_code3
attribute \src "boneless.v:84"
wire width 4 \i_code4
attribute \src "boneless.v:85"
wire width 5 \i_code5
attribute \src "boneless.v:89"
wire width 3 \i_cond
attribute \src "boneless.v:88"
wire \i_flag
attribute \src "boneless.v:79"
wire width 11 \i_imm11
attribute \src "boneless.v:77"
wire width 5 \i_imm5
attribute \src "boneless.v:78"
wire width 8 \i_imm8
attribute \src "boneless.v:74"
wire width 3 \i_regX
attribute \src "boneless.v:75"
wire width 3 \i_regY
attribute \src "boneless.v:76"
wire width 3 \i_regZ
attribute \src "boneless.v:80"
wire width 4 \i_shift
attribute \src "boneless.v:86"
wire \i_type1
attribute \src "boneless.v:87"
wire width 2 \i_type2
attribute \src "boneless.v:7"
wire width 16 \mem_r_addr
attribute \src "boneless.v:8"
wire width 16 \mem_r_data
attribute \src "boneless.v:9"
wire \mem_r_en
attribute \src "boneless.v:10"
wire width 16 \mem_w_addr
attribute \src "boneless.v:11"
wire width 16 \mem_w_data
attribute \src "boneless.v:12"
wire \mem_w_en
attribute \src "boneless.v:44"
wire width 13 \r_win
attribute \src "boneless.v:305"
wire width 17 \stb.addi.res
attribute \src "boneless.v:304"
wire width 16 \stb.addi.tmp
attribute \src "boneless.v:306"
wire \stb.addi.v
attribute \src "boneless.v:204"
wire \stb.arith.c
attribute \src "boneless.v:203"
wire width 17 \stb.arith.res
attribute \src "boneless.v:204"
wire \stb.arith.v
attribute \src "boneless.v:18"
memory width 16 size 65536 \ext
attribute \src "boneless.v:6"
memory width 16 size 65536 \mem
attribute \src "boneless.v:207"
cell $add $add$boneless.v:207$296
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 17
connect \A $memrd$\mem$boneless.v:207$294_DATA
connect \B $memrd$\mem$boneless.v:207$295_DATA
connect \Y $add$boneless.v:207$296_Y
end
attribute \src "boneless.v:265"
cell $add $add$boneless.v:265$371
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $past$boneless.v:265$1$0
connect \B { \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 }
connect \Y $add$boneless.v:265$371_Y
end
attribute \src "boneless.v:270"
cell $add $add$boneless.v:270$376
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:270$375_DATA
connect \B { \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 }
connect \Y $add$boneless.v:270$376_Y
end
attribute \src "boneless.v:278"
cell $add $add$boneless.v:278$386
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:278$385_DATA
connect \B { \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 }
connect \Y $add$boneless.v:278$386_Y
end
attribute \src "boneless.v:285"
cell $add $add$boneless.v:285$393
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:285$392_DATA
connect \B { \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 }
connect \Y $add$boneless.v:285$393_Y
end
attribute \src "boneless.v:289"
cell $add $add$boneless.v:289$399
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:289$398_DATA
connect \B { \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 [4] \i_imm5 }
connect \Y $add$boneless.v:289$399_Y
end
attribute \src "boneless.v:300"
cell $add $add$boneless.v:300$415
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A \fi_pc
connect \B 16'0000000000000001
connect \Y $add$boneless.v:300$415_Y
end
attribute \src "boneless.v:300"
cell $add $add$boneless.v:300$416
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $add$boneless.v:300$415_Y
connect \B { \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 }
connect \Y $add$boneless.v:300$416_Y
end
attribute \src "boneless.v:308"
cell $add $add$boneless.v:308$421
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 17
connect \A $memrd$\mem$boneless.v:308$420_DATA
connect \B { \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 }
connect \Y $add$boneless.v:308$421_Y
end
attribute \src "boneless.v:322"
cell $add $add$boneless.v:322$439
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A \fi_pc
connect \B 16'0000000000000001
connect \Y $add$boneless.v:322$439_Y
end
attribute \src "boneless.v:322"
cell $add $add$boneless.v:322$440
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $add$boneless.v:322$439_Y
connect \B { \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 }
connect \Y $add$boneless.v:322$440_Y
end
attribute \src "boneless.v:327"
cell $add $add$boneless.v:327$444
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A \fi_pc
connect \B 16'0000000000000001
connect \Y $add$boneless.v:327$444_Y
end
attribute \src "boneless.v:327"
cell $add $add$boneless.v:327$445
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $add$boneless.v:327$444_Y
connect \B { \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 }
connect \Y $add$boneless.v:327$445_Y
end
attribute \src "boneless.v:334"
cell $add $add$boneless.v:334$452
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A \fi_pc
connect \B 16'0000000000000001
connect \Y $add$boneless.v:334$452_Y
end
attribute \src "boneless.v:336"
cell $add $add$boneless.v:336$455
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A \fi_pc
connect \B 16'0000000000000001
connect \Y $add$boneless.v:336$455_Y
end
attribute \src "boneless.v:336"
cell $add $add$boneless.v:336$456
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $add$boneless.v:336$455_Y
connect \B { \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 }
connect \Y $add$boneless.v:336$456_Y
end
attribute \src "boneless.v:342"
cell $add $add$boneless.v:342$461
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:342$460_DATA
connect \B { \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 }
connect \Y $add$boneless.v:342$461_Y
end
attribute \src "boneless.v:348"
cell $add $add$boneless.v:348$464
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A \fi_pc
connect \B 16'0000000000000001
connect \Y $add$boneless.v:348$464_Y
end
attribute \src "boneless.v:348"
cell $add $add$boneless.v:348$465
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 1
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $add$boneless.v:348$464_Y
connect \B { \i_imm11 [10] \i_imm11 [10] \i_imm11 [10] \i_imm11 [10] \i_imm11 [10] \i_imm11 }
connect \Y $add$boneless.v:348$465_Y
end
attribute \src "boneless.v:188"
cell $and $and$boneless.v:188$280
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:188$278_DATA
connect \B $memrd$\mem$boneless.v:188$279_DATA
connect \Y $and$boneless.v:188$280_Y
end
attribute \src "boneless.v:161"
cell $assert $assert$boneless.v:161$482
connect \A $formal$boneless.v:161$14_CHECK
connect \EN $formal$boneless.v:161$14_EN
end
attribute \src "boneless.v:169"
cell $assert $assert$boneless.v:169$483
connect \A $formal$boneless.v:169$15_CHECK
connect \EN $formal$boneless.v:169$15_EN
end
attribute \src "boneless.v:173"
cell $assert $assert$boneless.v:173$484
connect \A $formal$boneless.v:173$16_CHECK
connect \EN $formal$boneless.v:173$16_EN
end
attribute \src "boneless.v:179"
cell $assert $assert$boneless.v:179$485
connect \A $formal$boneless.v:179$17_CHECK
connect \EN $formal$boneless.v:179$17_EN
end
attribute \src "boneless.v:184"
cell $assert $assert$boneless.v:184$486
connect \A $formal$boneless.v:184$18_CHECK
connect \EN $formal$boneless.v:184$18_EN
end
attribute \src "boneless.v:185"
cell $assert $assert$boneless.v:185$487
connect \A $formal$boneless.v:185$19_CHECK
connect \EN $formal$boneless.v:185$19_EN
end
attribute \src "boneless.v:188"
cell $assert $assert$boneless.v:188$488
connect \A $formal$boneless.v:188$20_CHECK
connect \EN $formal$boneless.v:188$20_EN
end
attribute \src "boneless.v:190"
cell $assert $assert$boneless.v:190$489
connect \A $formal$boneless.v:190$21_CHECK
connect \EN $formal$boneless.v:190$21_EN
end
attribute \src "boneless.v:192"
cell $assert $assert$boneless.v:192$490
connect \A $formal$boneless.v:192$22_CHECK
connect \EN $formal$boneless.v:192$22_EN
end
attribute \src "boneless.v:194"
cell $assert $assert$boneless.v:194$491
connect \A $formal$boneless.v:194$23_CHECK
connect \EN $formal$boneless.v:194$23_EN
end
attribute \src "boneless.v:195"
cell $assert $assert$boneless.v:195$492
connect \A $formal$boneless.v:195$24_CHECK
connect \EN $formal$boneless.v:195$24_EN
end
attribute \src "boneless.v:227"
cell $assert $assert$boneless.v:227$493
connect \A $formal$boneless.v:227$25_CHECK
connect \EN $formal$boneless.v:227$25_EN
end
attribute \src "boneless.v:229"
cell $assert $assert$boneless.v:229$494
connect \A $formal$boneless.v:229$26_CHECK
connect \EN $formal$boneless.v:229$26_EN
end
attribute \src "boneless.v:230"
cell $assert $assert$boneless.v:230$495
connect \A $formal$boneless.v:230$27_CHECK
connect \EN $formal$boneless.v:230$27_EN
end
attribute \src "boneless.v:231"
cell $assert $assert$boneless.v:231$496
connect \A $formal$boneless.v:231$28_CHECK
connect \EN $formal$boneless.v:231$28_EN
end
attribute \src "boneless.v:233"
cell $assert $assert$boneless.v:233$497
connect \A $formal$boneless.v:233$29_CHECK
connect \EN $formal$boneless.v:233$29_EN
end
attribute \src "boneless.v:234"
cell $assert $assert$boneless.v:234$498
connect \A $formal$boneless.v:234$30_CHECK
connect \EN $formal$boneless.v:234$30_EN
end
attribute \src "boneless.v:235"
cell $assert $assert$boneless.v:235$499
connect \A $formal$boneless.v:235$31_CHECK
connect \EN $formal$boneless.v:235$31_EN
end
attribute \src "boneless.v:236"
cell $assert $assert$boneless.v:236$500
connect \A $formal$boneless.v:236$32_CHECK
connect \EN $formal$boneless.v:236$32_EN
end
attribute \src "boneless.v:242"
cell $assert $assert$boneless.v:242$501
connect \A $formal$boneless.v:242$33_CHECK
connect \EN $formal$boneless.v:242$33_EN
end
attribute \src "boneless.v:243"
cell $assert $assert$boneless.v:243$502
connect \A $formal$boneless.v:243$34_CHECK
connect \EN $formal$boneless.v:243$34_EN
end
attribute \src "boneless.v:246"
cell $assert $assert$boneless.v:246$503
connect \A $formal$boneless.v:246$35_CHECK
connect \EN $formal$boneless.v:246$35_EN
end
attribute \src "boneless.v:249"
cell $assert $assert$boneless.v:249$504
connect \A $formal$boneless.v:249$36_CHECK
connect \EN $formal$boneless.v:249$36_EN
end
attribute \src "boneless.v:251"
cell $assert $assert$boneless.v:251$505
connect \A $formal$boneless.v:251$37_CHECK
connect \EN $formal$boneless.v:251$37_EN
end
attribute \src "boneless.v:253"
cell $assert $assert$boneless.v:253$506
connect \A $formal$boneless.v:253$38_CHECK
connect \EN $formal$boneless.v:253$38_EN
end
attribute \src "boneless.v:255"
cell $assert $assert$boneless.v:255$507
connect \A $formal$boneless.v:255$39_CHECK
connect \EN $formal$boneless.v:255$39_EN
end
attribute \src "boneless.v:256"
cell $assert $assert$boneless.v:256$508
connect \A $formal$boneless.v:256$40_CHECK
connect \EN $formal$boneless.v:256$40_EN
end
attribute \src "boneless.v:261"
cell $assert $assert$boneless.v:261$509
connect \A $formal$boneless.v:261$41_CHECK
connect \EN $formal$boneless.v:261$41_EN
end
attribute \src "boneless.v:262"
cell $assert $assert$boneless.v:262$510
connect \A $formal$boneless.v:262$42_CHECK
connect \EN $formal$boneless.v:262$42_EN
end
attribute \src "boneless.v:265"
cell $assert $assert$boneless.v:265$511
connect \A $formal$boneless.v:265$43_CHECK
connect \EN $formal$boneless.v:265$43_EN
end
attribute \src "boneless.v:266"
cell $assert $assert$boneless.v:266$512
connect \A $formal$boneless.v:266$44_CHECK
connect \EN $formal$boneless.v:266$44_EN
end
attribute \src "boneless.v:269"
cell $assert $assert$boneless.v:269$513
connect \A $formal$boneless.v:269$45_CHECK
connect \EN $formal$boneless.v:269$45_EN
end
attribute \src "boneless.v:270"
cell $assert $assert$boneless.v:270$514
connect \A $formal$boneless.v:270$46_CHECK
connect \EN $formal$boneless.v:270$46_EN
end
attribute \src "boneless.v:271"
cell $assert $assert$boneless.v:271$515
connect \A $formal$boneless.v:271$47_CHECK
connect \EN $formal$boneless.v:271$47_EN
end
attribute \src "boneless.v:272"
cell $assert $assert$boneless.v:272$516
connect \A $formal$boneless.v:272$48_CHECK
connect \EN $formal$boneless.v:272$48_EN
end
attribute \src "boneless.v:275"
cell $assert $assert$boneless.v:275$517
connect \A $formal$boneless.v:275$49_CHECK
connect \EN $formal$boneless.v:275$49_EN
end
attribute \src "boneless.v:276"
cell $assert $assert$boneless.v:276$518
connect \A $formal$boneless.v:276$50_CHECK
connect \EN $formal$boneless.v:276$50_EN
end
attribute \src "boneless.v:277"
cell $assert $assert$boneless.v:277$519
connect \A $formal$boneless.v:277$51_CHECK
connect \EN $formal$boneless.v:277$51_EN
end
attribute \src "boneless.v:278"
cell $assert $assert$boneless.v:278$520
connect \A $formal$boneless.v:278$52_CHECK
connect \EN $formal$boneless.v:278$52_EN
end
attribute \src "boneless.v:279"
cell $assert $assert$boneless.v:279$521
connect \A $formal$boneless.v:279$53_CHECK
connect \EN $formal$boneless.v:279$53_EN
end
attribute \src "boneless.v:282"
cell $assert $assert$boneless.v:282$522
connect \A $formal$boneless.v:282$54_CHECK
connect \EN $formal$boneless.v:282$54_EN
end
attribute \src "boneless.v:283"
cell $assert $assert$boneless.v:283$523
connect \A $formal$boneless.v:283$55_CHECK
connect \EN $formal$boneless.v:283$55_EN
end
attribute \src "boneless.v:285"
cell $assert $assert$boneless.v:285$524
connect \A $formal$boneless.v:285$56_CHECK
connect \EN $formal$boneless.v:285$56_EN
end
attribute \src "boneless.v:286"
cell $assert $assert$boneless.v:286$525
connect \A $formal$boneless.v:286$57_CHECK
connect \EN $formal$boneless.v:286$57_EN
end
attribute \src "boneless.v:289"
cell $assert $assert$boneless.v:289$526
connect \A $formal$boneless.v:289$58_CHECK
connect \EN $formal$boneless.v:289$58_EN
end
attribute \src "boneless.v:290"
cell $assert $assert$boneless.v:290$527
connect \A $formal$boneless.v:290$59_CHECK
connect \EN $formal$boneless.v:290$59_EN
end
attribute \src "boneless.v:293"
cell $assert $assert$boneless.v:293$528
connect \A $formal$boneless.v:293$60_CHECK
connect \EN $formal$boneless.v:293$60_EN
end
attribute \src "boneless.v:294"
cell $assert $assert$boneless.v:294$529
connect \A $formal$boneless.v:294$61_CHECK
connect \EN $formal$boneless.v:294$61_EN
end
attribute \src "boneless.v:296"
cell $assert $assert$boneless.v:296$530
connect \A $formal$boneless.v:296$62_CHECK
connect \EN $formal$boneless.v:296$62_EN
end
attribute \src "boneless.v:298"
cell $assert $assert$boneless.v:298$531
connect \A $formal$boneless.v:298$63_CHECK
connect \EN $formal$boneless.v:298$63_EN
end
attribute \src "boneless.v:300"
cell $assert $assert$boneless.v:300$532
connect \A $formal$boneless.v:300$64_CHECK
connect \EN $formal$boneless.v:300$64_EN
end
attribute \src "boneless.v:301"
cell $assert $assert$boneless.v:301$533
connect \A $formal$boneless.v:301$65_CHECK
connect \EN $formal$boneless.v:301$65_EN
end
attribute \src "boneless.v:311"
cell $assert $assert$boneless.v:311$534
connect \A $formal$boneless.v:311$66_CHECK
connect \EN $formal$boneless.v:311$66_EN
end
attribute \src "boneless.v:312"
cell $assert $assert$boneless.v:312$535
connect \A $formal$boneless.v:312$67_CHECK
connect \EN $formal$boneless.v:312$67_EN
end
attribute \src "boneless.v:313"
cell $assert $assert$boneless.v:313$536
connect \A $formal$boneless.v:313$68_CHECK
connect \EN $formal$boneless.v:313$68_EN
end
attribute \src "boneless.v:314"
cell $assert $assert$boneless.v:314$537
connect \A $formal$boneless.v:314$69_CHECK
connect \EN $formal$boneless.v:314$69_EN
end
attribute \src "boneless.v:315"
cell $assert $assert$boneless.v:315$538
connect \A $formal$boneless.v:315$70_CHECK
connect \EN $formal$boneless.v:315$70_EN
end
attribute \src "boneless.v:316"
cell $assert $assert$boneless.v:316$539
connect \A $formal$boneless.v:316$71_CHECK
connect \EN $formal$boneless.v:316$71_EN
end
attribute \src "boneless.v:317"
cell $assert $assert$boneless.v:317$540
connect \A $formal$boneless.v:317$72_CHECK
connect \EN $formal$boneless.v:317$72_EN
end
attribute \src "boneless.v:320"
cell $assert $assert$boneless.v:320$541
connect \A $formal$boneless.v:320$73_CHECK
connect \EN $formal$boneless.v:320$73_EN
end
attribute \src "boneless.v:321"
cell $assert $assert$boneless.v:321$542
connect \A $formal$boneless.v:321$74_CHECK
connect \EN $formal$boneless.v:321$74_EN
end
attribute \src "boneless.v:322"
cell $assert $assert$boneless.v:322$543
connect \A $formal$boneless.v:322$75_CHECK
connect \EN $formal$boneless.v:322$75_EN
end
attribute \src "boneless.v:323"
cell $assert $assert$boneless.v:323$544
connect \A $formal$boneless.v:323$76_CHECK
connect \EN $formal$boneless.v:323$76_EN
end
attribute \src "boneless.v:326"
cell $assert $assert$boneless.v:326$545
connect \A $formal$boneless.v:326$77_CHECK
connect \EN $formal$boneless.v:326$77_EN
end
attribute \src "boneless.v:327"
cell $assert $assert$boneless.v:327$546
connect \A $formal$boneless.v:327$78_CHECK
connect \EN $formal$boneless.v:327$78_EN
end
attribute \src "boneless.v:328"
cell $assert $assert$boneless.v:328$547
connect \A $formal$boneless.v:328$79_CHECK
connect \EN $formal$boneless.v:328$79_EN
end
attribute \src "boneless.v:329"
cell $assert $assert$boneless.v:329$548
connect \A $formal$boneless.v:329$80_CHECK
connect \EN $formal$boneless.v:329$80_EN
end
attribute \src "boneless.v:332"
cell $assert $assert$boneless.v:332$549
connect \A $formal$boneless.v:332$81_CHECK
connect \EN $formal$boneless.v:332$81_EN
end
attribute \src "boneless.v:333"
cell $assert $assert$boneless.v:333$550
connect \A $formal$boneless.v:333$82_CHECK
connect \EN $formal$boneless.v:333$82_EN
end
attribute \src "boneless.v:334"
cell $assert $assert$boneless.v:334$551
connect \A $formal$boneless.v:334$83_CHECK
connect \EN $formal$boneless.v:334$83_EN
end
attribute \src "boneless.v:335"
cell $assert $assert$boneless.v:335$552
connect \A $formal$boneless.v:335$84_CHECK
connect \EN $formal$boneless.v:335$84_EN
end
attribute \src "boneless.v:340"
cell $assert $assert$boneless.v:340$553
connect \A $formal$boneless.v:340$85_CHECK
connect \EN $formal$boneless.v:340$85_EN
end
attribute \src "boneless.v:341"
cell $assert $assert$boneless.v:341$554
connect \A $formal$boneless.v:341$86_CHECK
connect \EN $formal$boneless.v:341$86_EN
end
attribute \src "boneless.v:346"
cell $assert $assert$boneless.v:346$555
connect \A $formal$boneless.v:346$87_CHECK
connect \EN $formal$boneless.v:346$87_EN
end
attribute \src "boneless.v:347"
cell $assert $assert$boneless.v:347$556
connect \A $formal$boneless.v:347$88_CHECK
connect \EN $formal$boneless.v:347$88_EN
end
attribute \src "boneless.v:100"
cell $eq $eq$boneless.v:100$102
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
connect \A \i_code5 [4:3]
connect \B 2'01
connect \Y $eq$boneless.v:100$102_Y
end
attribute \src "boneless.v:101"
cell $eq $eq$boneless.v:101$103
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i_code5 [4]
connect \B 1'1
connect \Y $eq$boneless.v:101$103_Y
end
attribute \src "boneless.v:169"
cell $eq $eq$boneless.v:169$271
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00110
connect \Y $eq$boneless.v:169$271_Y
end
attribute \src "boneless.v:173"
cell $eq $eq$boneless.v:173$273
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00111
connect \Y $eq$boneless.v:173$273_Y
end
attribute \src "boneless.v:179"
cell $eq $eq$boneless.v:179$274
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_pc
connect \B \fs_next_pc
connect \Y $eq$boneless.v:179$274_Y
end
attribute \src "boneless.v:182"
cell $eq $eq$boneless.v:182$275
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00000
connect \Y $eq$boneless.v:182$275_Y
end
attribute \src "boneless.v:185"
cell $eq $eq$boneless.v:185$277
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B \a_regZ
connect \Y $eq$boneless.v:185$277_Y
end
attribute \src "boneless.v:188"
cell $eq $eq$boneless.v:188$281
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $and$boneless.v:188$280_Y
connect \Y $eq$boneless.v:188$281_Y
end
attribute \src "boneless.v:190"
cell $eq $eq$boneless.v:190$285
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $or$boneless.v:190$284_Y
connect \Y $eq$boneless.v:190$285_Y
end
attribute \src "boneless.v:192"
cell $eq $eq$boneless.v:192$289
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $xor$boneless.v:192$288_Y
connect \Y $eq$boneless.v:192$289_Y
end
attribute \src "boneless.v:194"
cell $eq $eq$boneless.v:194$290
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B 0
connect \Y $eq$boneless.v:194$290_Y
end
attribute \src "boneless.v:194"
cell $eq $eq$boneless.v:194$291
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_z
connect \B $eq$boneless.v:194$290_Y
connect \Y $eq$boneless.v:194$291_Y
end
attribute \src "boneless.v:195"
cell $eq $eq$boneless.v:195$292
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_s
connect \B \fi_mem_w_data [15]
connect \Y $eq$boneless.v:195$292_Y
end
attribute \src "boneless.v:202"
cell $eq $eq$boneless.v:202$293
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00001
connect \Y $eq$boneless.v:202$293_Y
end
attribute \src "boneless.v:209"
cell $eq $eq$boneless.v:209$301
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:209$298_Y
connect \B $lt$boneless.v:209$300_Y
connect \Y $eq$boneless.v:209$301_Y
end
attribute \src "boneless.v:215"
cell $eq $eq$boneless.v:215$315
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:215$311_Y
connect \B $logic_not$boneless.v:215$314_Y
connect \Y $eq$boneless.v:215$315_Y
end
attribute \src "boneless.v:221"
cell $eq $eq$boneless.v:221$329
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:221$325_Y
connect \B $logic_not$boneless.v:221$328_Y
connect \Y $eq$boneless.v:221$329_Y
end
attribute \src "boneless.v:226"
cell $eq $eq$boneless.v:226$335
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
connect \A \i_type2
connect \B 2'10
connect \Y $eq$boneless.v:226$335_Y
end
attribute \src "boneless.v:230"
cell $eq $eq$boneless.v:230$337
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B \a_regZ
connect \Y $eq$boneless.v:230$337_Y
end
attribute \src "boneless.v:231"
cell $eq $eq$boneless.v:231$338
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $3\stb.arith.res[16:0] [15:0]
connect \Y $eq$boneless.v:231$338_Y
end
attribute \src "boneless.v:233"
cell $eq $eq$boneless.v:233$339
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A $3\stb.arith.res[16:0] [15:0]
connect \B 0
connect \Y $eq$boneless.v:233$339_Y
end
attribute \src "boneless.v:233"
cell $eq $eq$boneless.v:233$340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_z
connect \B $eq$boneless.v:233$339_Y
connect \Y $eq$boneless.v:233$340_Y
end
attribute \src "boneless.v:234"
cell $eq $eq$boneless.v:234$341
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_s
connect \B $3\stb.arith.res[16:0] [15]
connect \Y $eq$boneless.v:234$341_Y
end
attribute \src "boneless.v:235"
cell $eq $eq$boneless.v:235$342
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_c
connect \B $3\stb.arith.c[0:0]
connect \Y $eq$boneless.v:235$342_Y
end
attribute \src "boneless.v:236"
cell $eq $eq$boneless.v:236$343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_v
connect \B $3\stb.arith.v[0:0]
connect \Y $eq$boneless.v:236$343_Y
end
attribute \src "boneless.v:241"
cell $eq $eq$boneless.v:241$344
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00010
connect \Y $eq$boneless.v:241$344_Y
end
attribute \src "boneless.v:241"
cell $eq $eq$boneless.v:241$345
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00011
connect \Y $eq$boneless.v:241$345_Y
end
attribute \src "boneless.v:243"
cell $eq $eq$boneless.v:243$347
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B \a_regZ
connect \Y $eq$boneless.v:243$347_Y
end
attribute \src "boneless.v:246"
cell $eq $eq$boneless.v:246$350
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $shl$boneless.v:246$349_Y
connect \Y $eq$boneless.v:246$350_Y
end
attribute \src "boneless.v:248"
cell $eq $eq$boneless.v:248$353
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A \fi_mem_w_data
connect \B $shl$boneless.v:248$352_Y
connect \Y $eq$boneless.v:248$353_Y
end
attribute \src "boneless.v:251"
cell $eq $eq$boneless.v:251$361
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $shr$boneless.v:251$360_Y
connect \Y $eq$boneless.v:251$361_Y
end
attribute \src "boneless.v:253"
cell $eq $eq$boneless.v:253$364
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $sshr$boneless.v:253$363_Y
connect \Y $eq$boneless.v:253$364_Y
end
attribute \src "boneless.v:255"
cell $eq $eq$boneless.v:255$365
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B 0
connect \Y $eq$boneless.v:255$365_Y
end
attribute \src "boneless.v:255"
cell $eq $eq$boneless.v:255$366
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_z
connect \B $eq$boneless.v:255$365_Y
connect \Y $eq$boneless.v:255$366_Y
end
attribute \src "boneless.v:256"
cell $eq $eq$boneless.v:256$367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_s
connect \B \fi_mem_w_data [15]
connect \Y $eq$boneless.v:256$367_Y
end
attribute \src "boneless.v:260"
cell $eq $eq$boneless.v:260$368
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00100
connect \Y $eq$boneless.v:260$368_Y
end
attribute \src "boneless.v:262"
cell $eq $eq$boneless.v:262$369
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B \a_regZ
connect \Y $eq$boneless.v:262$369_Y
end
attribute \src "boneless.v:265"
cell $eq $eq$boneless.v:265$372
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $memrd$\mem$boneless.v:265$370_DATA
connect \Y $eq$boneless.v:265$372_Y
end
attribute \src "boneless.v:266"
cell $eq $eq$boneless.v:266$373
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:266$2$0
connect \Y $eq$boneless.v:266$373_Y
end
attribute \src "boneless.v:268"
cell $eq $eq$boneless.v:268$374
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00101
connect \Y $eq$boneless.v:268$374_Y
end
attribute \src "boneless.v:270"
cell $eq $eq$boneless.v:270$377
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B $add$boneless.v:270$376_Y
connect \Y $eq$boneless.v:270$377_Y
end
attribute \src "boneless.v:271"
cell $eq $eq$boneless.v:271$379
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $memrd$\mem$boneless.v:271$378_DATA
connect \Y $eq$boneless.v:271$379_Y
end
attribute \src "boneless.v:272"
cell $eq $eq$boneless.v:272$380
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:272$3$0
connect \Y $eq$boneless.v:272$380_Y
end
attribute \src "boneless.v:274"
cell $eq $eq$boneless.v:274$381
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00110
connect \Y $eq$boneless.v:274$381_Y
end
attribute \src "boneless.v:277"
cell $eq $eq$boneless.v:277$383
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B \a_regZ
connect \Y $eq$boneless.v:277$383_Y
end
attribute \src "boneless.v:278"
cell $eq $eq$boneless.v:278$387
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $memrd$\ext$boneless.v:278$384_DATA
connect \Y $eq$boneless.v:278$387_Y
end
attribute \src "boneless.v:279"
cell $eq $eq$boneless.v:279$388
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:279$4$0
connect \Y $eq$boneless.v:279$388_Y
end
attribute \src "boneless.v:281"
cell $eq $eq$boneless.v:281$389
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'00111
connect \Y $eq$boneless.v:281$389_Y
end
attribute \src "boneless.v:285"
cell $eq $eq$boneless.v:285$394
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_ext_addr
connect \B $add$boneless.v:285$393_Y
connect \Y $eq$boneless.v:285$394_Y
end
attribute \src "boneless.v:286"
cell $eq $eq$boneless.v:286$396
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_ext_w_data
connect \B $memrd$\mem$boneless.v:286$395_DATA
connect \Y $eq$boneless.v:286$396_Y
end
attribute \src "boneless.v:289"
cell $eq $eq$boneless.v:289$401
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A $memrd$\ext$boneless.v:289$397_DATA
connect \B $memrd$\mem$boneless.v:289$400_DATA
connect \Y $eq$boneless.v:289$401_Y
end
attribute \src "boneless.v:290"
cell $eq $eq$boneless.v:290$402
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:290$5$0
connect \Y $eq$boneless.v:290$402_Y
end
attribute \src "boneless.v:292"
cell $eq $eq$boneless.v:292$403
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01000
connect \Y $eq$boneless.v:292$403_Y
end
attribute \src "boneless.v:292"
cell $eq $eq$boneless.v:292$404
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01001
connect \Y $eq$boneless.v:292$404_Y
end
attribute \src "boneless.v:292"
cell $eq $eq$boneless.v:292$406
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01010
connect \Y $eq$boneless.v:292$406_Y
end
attribute \src "boneless.v:294"
cell $eq $eq$boneless.v:294$408
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B \a_regZ
connect \Y $eq$boneless.v:294$408_Y
end
attribute \src "boneless.v:295"
cell $eq $eq$boneless.v:295$409
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01000
connect \Y $eq$boneless.v:295$409_Y
end
attribute \src "boneless.v:296"
cell $eq $eq$boneless.v:296$410
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B \i_imm8
connect \Y $eq$boneless.v:296$410_Y
end
attribute \src "boneless.v:297"
cell $eq $eq$boneless.v:297$411
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01001
connect \Y $eq$boneless.v:297$411_Y
end
attribute \src "boneless.v:298"
cell $eq $eq$boneless.v:298$413
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $shl$boneless.v:298$412_Y
connect \Y $eq$boneless.v:298$413_Y
end
attribute \src "boneless.v:299"
cell $eq $eq$boneless.v:299$414
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01010
connect \Y $eq$boneless.v:299$414_Y
end
attribute \src "boneless.v:300"
cell $eq $eq$boneless.v:300$417
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $add$boneless.v:300$416_Y
connect \Y $eq$boneless.v:300$417_Y
end
attribute \src "boneless.v:301"
cell $eq $eq$boneless.v:301$418
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:301$6$0
connect \Y $eq$boneless.v:301$418_Y
end
attribute \src "boneless.v:303"
cell $eq $eq$boneless.v:303$419
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01011
connect \Y $eq$boneless.v:303$419_Y
end
attribute \src "boneless.v:309"
cell $eq $eq$boneless.v:309$424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:309$423_Y
connect \B \i_imm8 [7]
connect \Y $eq$boneless.v:309$424_Y
end
attribute \src "boneless.v:312"
cell $eq $eq$boneless.v:312$429
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B \a_regZ
connect \Y $eq$boneless.v:312$429_Y
end
attribute \src "boneless.v:313"
cell $eq $eq$boneless.v:313$430
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $add$boneless.v:308$421_Y [15:0]
connect \Y $eq$boneless.v:313$430_Y
end
attribute \src "boneless.v:314"
cell $eq $eq$boneless.v:314$431
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A $add$boneless.v:308$421_Y [15:0]
connect \B 0
connect \Y $eq$boneless.v:314$431_Y
end
attribute \src "boneless.v:314"
cell $eq $eq$boneless.v:314$432
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_z
connect \B $eq$boneless.v:314$431_Y
connect \Y $eq$boneless.v:314$432_Y
end
attribute \src "boneless.v:315"
cell $eq $eq$boneless.v:315$433
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_s
connect \B $add$boneless.v:308$421_Y [15]
connect \Y $eq$boneless.v:315$433_Y
end
attribute \src "boneless.v:316"
cell $eq $eq$boneless.v:316$434
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_c
connect \B $add$boneless.v:308$421_Y [16]
connect \Y $eq$boneless.v:316$434_Y
end
attribute \src "boneless.v:317"
cell $eq $eq$boneless.v:317$435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_v
connect \B $logic_and$boneless.v:310$428_Y
connect \Y $eq$boneless.v:317$435_Y
end
attribute \src "boneless.v:319"
cell $eq $eq$boneless.v:319$436
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01100
connect \Y $eq$boneless.v:319$436_Y
end
attribute \src "boneless.v:321"
cell $eq $eq$boneless.v:321$437
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B \a_regZ
connect \Y $eq$boneless.v:321$437_Y
end
attribute \src "boneless.v:322"
cell $eq $eq$boneless.v:322$441
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $memrd$\mem$boneless.v:322$438_DATA
connect \Y $eq$boneless.v:322$441_Y
end
attribute \src "boneless.v:323"
cell $eq $eq$boneless.v:323$442
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:323$7$0
connect \Y $eq$boneless.v:323$442_Y
end
attribute \src "boneless.v:325"
cell $eq $eq$boneless.v:325$443
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01101
connect \Y $eq$boneless.v:325$443_Y
end
attribute \src "boneless.v:327"
cell $eq $eq$boneless.v:327$446
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B $add$boneless.v:327$445_Y
connect \Y $eq$boneless.v:327$446_Y
end
attribute \src "boneless.v:328"
cell $eq $eq$boneless.v:328$448
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $memrd$\mem$boneless.v:328$447_DATA
connect \Y $eq$boneless.v:328$448_Y
end
attribute \src "boneless.v:329"
cell $eq $eq$boneless.v:329$449
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:329$8$0
connect \Y $eq$boneless.v:329$449_Y
end
attribute \src "boneless.v:331"
cell $eq $eq$boneless.v:331$450
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01110
connect \Y $eq$boneless.v:331$450_Y
end
attribute \src "boneless.v:333"
cell $eq $eq$boneless.v:333$451
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_addr
connect \B \a_regZ
connect \Y $eq$boneless.v:333$451_Y
end
attribute \src "boneless.v:334"
cell $eq $eq$boneless.v:334$453
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 1
connect \A \fi_mem_w_data
connect \B $add$boneless.v:334$452_Y
connect \Y $eq$boneless.v:334$453_Y
end
attribute \src "boneless.v:335"
cell $eq $eq$boneless.v:335$454
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:335$9$0
connect \Y $eq$boneless.v:335$454_Y
end
attribute \src "boneless.v:339"
cell $eq $eq$boneless.v:339$457
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 1
connect \A \i_code5
connect \B 5'01111
connect \Y $eq$boneless.v:339$457_Y
end
attribute \src "boneless.v:341"
cell $eq $eq$boneless.v:341$459
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:341$10$0
connect \Y $eq$boneless.v:341$459_Y
end
attribute \src "boneless.v:347"
cell $eq $eq$boneless.v:347$463
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \fi_flags
connect \B $past$boneless.v:347$11$0
connect \Y $eq$boneless.v:347$463_Y
end
attribute \src "boneless.v:350"
cell $eq $eq$boneless.v:350$466
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A \i_flag
connect \B 0
connect \Y $eq$boneless.v:350$466_Y
end
attribute \src "boneless.v:351"
cell $eq $eq$boneless.v:351$467
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i_flag
connect \B \fi_z
connect \Y $eq$boneless.v:351$467_Y
end
attribute \src "boneless.v:352"
cell $eq $eq$boneless.v:352$468
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i_flag
connect \B \fi_s
connect \Y $eq$boneless.v:352$468_Y
end
attribute \src "boneless.v:353"
cell $eq $eq$boneless.v:353$469
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i_flag
connect \B \fi_c
connect \Y $eq$boneless.v:353$469_Y
end
attribute \src "boneless.v:354"
cell $eq $eq$boneless.v:354$470
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i_flag
connect \B \fi_v
connect \Y $eq$boneless.v:354$470_Y
end
attribute \src "boneless.v:355"
cell $eq $eq$boneless.v:355$473
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i_flag
connect \B $or$boneless.v:355$472_Y
connect \Y $eq$boneless.v:355$473_Y
end
attribute \src "boneless.v:356"
cell $eq $eq$boneless.v:356$475
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i_flag
connect \B $xor$boneless.v:356$474_Y
connect \Y $eq$boneless.v:356$475_Y
end
attribute \src "boneless.v:357"
cell $eq $eq$boneless.v:357$478
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \i_flag
connect \B $or$boneless.v:357$477_Y
connect \Y $eq$boneless.v:357$478_Y
end
attribute \src "boneless.v:97"
cell $eq $eq$boneless.v:97$99
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \i_code5 [4:1]
connect \B 4'0000
connect \Y $eq$boneless.v:97$99_Y
end
attribute \src "boneless.v:98"
cell $eq $eq$boneless.v:98$100
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 1
connect \A \i_code5 [4:1]
connect \B 4'0001
connect \Y $eq$boneless.v:98$100_Y
end
attribute \src "boneless.v:99"
cell $eq $eq$boneless.v:99$101
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 1
connect \A \i_code5 [4:2]
connect \B 3'001
connect \Y $eq$boneless.v:99$101_Y
end
attribute \src "boneless.v:161"
cell $logic_and $logic_and$boneless.v:161$269
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $logic_not$boneless.v:161$267_Y
connect \B $logic_not$boneless.v:161$268_Y
connect \Y $logic_and$boneless.v:161$269_Y
end
attribute \src "boneless.v:210"
cell $logic_and $logic_and$boneless.v:210$305
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $eq$boneless.v:209$301_Y
connect \B $ne$boneless.v:210$304_Y
connect \Y $logic_and$boneless.v:210$305_Y
end
attribute \src "boneless.v:216"
cell $logic_and $logic_and$boneless.v:216$319
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $eq$boneless.v:215$315_Y
connect \B $ne$boneless.v:216$318_Y
connect \Y $logic_and$boneless.v:216$319_Y
end
attribute \src "boneless.v:222"
cell $logic_and $logic_and$boneless.v:222$333
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $eq$boneless.v:221$329_Y
connect \B $ne$boneless.v:222$332_Y
connect \Y $logic_and$boneless.v:222$333_Y
end
attribute \src "boneless.v:310"
cell $logic_and $logic_and$boneless.v:310$428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $eq$boneless.v:309$424_Y
connect \B $ne$boneless.v:310$427_Y
connect \Y $logic_and$boneless.v:310$428_Y
end
attribute \src "boneless.v:161"
cell $logic_not $logic_not$boneless.v:161$267
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fs_past_ext_r_en
connect \Y $logic_not$boneless.v:161$267_Y
end
attribute \src "boneless.v:161"
cell $logic_not $logic_not$boneless.v:161$268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fs_past_ext_w_en
connect \Y $logic_not$boneless.v:161$268_Y
end
attribute \src "boneless.v:215"
cell $logic_not $logic_not$boneless.v:215$314
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:215$313_Y
connect \Y $logic_not$boneless.v:215$314_Y
end
attribute \src "boneless.v:221"
cell $logic_not $logic_not$boneless.v:221$328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:221$327_Y
connect \Y $logic_not$boneless.v:221$328_Y
end
attribute \src "boneless.v:227"
cell $logic_not $logic_not$boneless.v:227$336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_mem_w_en
connect \Y $logic_not$boneless.v:227$336_Y
end
attribute \src "boneless.v:282"
cell $logic_not $logic_not$boneless.v:282$390
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_mem_w_en
connect \Y $logic_not$boneless.v:282$390_Y
end
attribute \src "boneless.v:340"
cell $logic_not $logic_not$boneless.v:340$458
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_mem_w_en
connect \Y $logic_not$boneless.v:340$458_Y
end
attribute \src "boneless.v:346"
cell $logic_not $logic_not$boneless.v:346$462
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_mem_w_en
connect \Y $logic_not$boneless.v:346$462_Y
end
attribute \src "boneless.v:355"
cell $logic_not $logic_not$boneless.v:355$471
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_c
connect \Y $logic_not$boneless.v:355$471_Y
end
attribute \src "boneless.v:160"
cell $logic_or $logic_or$boneless.v:160$266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_ext_r_en
connect \B \fi_ext_w_en
connect \Y $logic_or$boneless.v:160$266_Y
end
attribute \src "boneless.v:168"
cell $logic_or $logic_or$boneless.v:168$270
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_ext_r_en
connect \B \fs_past_ext_r_en
connect \Y $logic_or$boneless.v:168$270_Y
end
attribute \src "boneless.v:172"
cell $logic_or $logic_or$boneless.v:172$272
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_ext_w_en
connect \B \fs_past_ext_w_en
connect \Y $logic_or$boneless.v:172$272_Y
end
attribute \src "boneless.v:241"
cell $logic_or $logic_or$boneless.v:241$346
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $eq$boneless.v:241$344_Y
connect \B $eq$boneless.v:241$345_Y
connect \Y $logic_or$boneless.v:241$346_Y
end
attribute \src "boneless.v:276"
cell $logic_or $logic_or$boneless.v:276$382
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_ext_r_en
connect \B \fs_past_ext_r_en
connect \Y $logic_or$boneless.v:276$382_Y
end
attribute \src "boneless.v:283"
cell $logic_or $logic_or$boneless.v:283$391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_ext_w_en
connect \B \fs_past_ext_w_en
connect \Y $logic_or$boneless.v:283$391_Y
end
attribute \src "boneless.v:292"
cell $logic_or $logic_or$boneless.v:292$405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $eq$boneless.v:292$403_Y
connect \B $eq$boneless.v:292$404_Y
connect \Y $logic_or$boneless.v:292$405_Y
end
attribute \src "boneless.v:292"
cell $logic_or $logic_or$boneless.v:292$407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $logic_or$boneless.v:292$405_Y
connect \B $eq$boneless.v:292$406_Y
connect \Y $logic_or$boneless.v:292$407_Y
end
attribute \src "boneless.v:209"
cell $lt $lt$boneless.v:209$298
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA [15] $memrd$\mem$boneless.v:209$297_DATA }
connect \B 0
connect \Y $lt$boneless.v:209$298_Y
end
attribute \src "boneless.v:209"
cell $lt $lt$boneless.v:209$300
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA [15] $memrd$\mem$boneless.v:209$299_DATA }
connect \B 0
connect \Y $lt$boneless.v:209$300_Y
end
attribute \src "boneless.v:210"
cell $lt $lt$boneless.v:210$303
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA [15] $memrd$\mem$boneless.v:210$302_DATA }
connect \B 0
connect \Y $lt$boneless.v:210$303_Y
end
attribute \src "boneless.v:215"
cell $lt $lt$boneless.v:215$311
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA [15] $memrd$\mem$boneless.v:215$310_DATA }
connect \B 0
connect \Y $lt$boneless.v:215$311_Y
end
attribute \src "boneless.v:215"
cell $lt $lt$boneless.v:215$313
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA [15] $memrd$\mem$boneless.v:215$312_DATA }
connect \B 0
connect \Y $lt$boneless.v:215$313_Y
end
attribute \src "boneless.v:216"
cell $lt $lt$boneless.v:216$317
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA [15] $memrd$\mem$boneless.v:216$316_DATA }
connect \B 0
connect \Y $lt$boneless.v:216$317_Y
end
attribute \src "boneless.v:221"
cell $lt $lt$boneless.v:221$325
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA [15] $memrd$\mem$boneless.v:221$324_DATA }
connect \B 0
connect \Y $lt$boneless.v:221$325_Y
end
attribute \src "boneless.v:221"
cell $lt $lt$boneless.v:221$327
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA [15] $memrd$\mem$boneless.v:221$326_DATA }
connect \B 0
connect \Y $lt$boneless.v:221$327_Y
end
attribute \src "boneless.v:222"
cell $lt $lt$boneless.v:222$331
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA [15] $memrd$\mem$boneless.v:222$330_DATA }
connect \B 0
connect \Y $lt$boneless.v:222$331_Y
end
attribute \src "boneless.v:309"
cell $lt $lt$boneless.v:309$423
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA [15] $memrd$\mem$boneless.v:309$422_DATA }
connect \B 0
connect \Y $lt$boneless.v:309$423_Y
end
attribute \src "boneless.v:310"
cell $lt $lt$boneless.v:310$426
parameter \A_SIGNED 1
parameter \A_WIDTH 32
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 1
connect \A { $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA [15] $memrd$\mem$boneless.v:310$425_DATA }
connect \B 0
connect \Y $lt$boneless.v:310$426_Y
end
attribute \src "boneless.v:25"
cell $memrd $memrd$\ext$boneless.v:25$98
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\ext"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \ext_addr
connect \CLK 1'x
connect \DATA $memrd$\ext$boneless.v:25$98_DATA
connect \EN 1'x
end
attribute \src "boneless.v:278"
cell $memrd $memrd$\ext$boneless.v:278$384
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\ext"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR $add$boneless.v:278$386_Y
connect \CLK 1'x
connect \DATA $memrd$\ext$boneless.v:278$384_DATA
connect \EN 1'x
end
attribute \src "boneless.v:289"
cell $memrd $memrd$\ext$boneless.v:289$397
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\ext"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR $add$boneless.v:289$399_Y
connect \CLK 1'x
connect \DATA $memrd$\ext$boneless.v:289$397_DATA
connect \EN 1'x
end
attribute \src "boneless.v:14"
cell $memrd $memrd$\mem$boneless.v:14$93
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \mem_r_addr
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:14$93_DATA
connect \EN 1'x
end
attribute \src "boneless.v:188"
cell $memrd $memrd$\mem$boneless.v:188$278
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:188$278_DATA
connect \EN 1'x
end
attribute \src "boneless.v:188"
cell $memrd $memrd$\mem$boneless.v:188$279
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regX
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:188$279_DATA
connect \EN 1'x
end
attribute \src "boneless.v:190"
cell $memrd $memrd$\mem$boneless.v:190$282
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:190$282_DATA
connect \EN 1'x
end
attribute \src "boneless.v:190"
cell $memrd $memrd$\mem$boneless.v:190$283
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regX
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:190$283_DATA
connect \EN 1'x
end
attribute \src "boneless.v:192"
cell $memrd $memrd$\mem$boneless.v:192$286
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:192$286_DATA
connect \EN 1'x
end
attribute \src "boneless.v:192"
cell $memrd $memrd$\mem$boneless.v:192$287
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regX
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:192$287_DATA
connect \EN 1'x
end
attribute \src "boneless.v:207"
cell $memrd $memrd$\mem$boneless.v:207$294
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:207$294_DATA
connect \EN 1'x
end
attribute \src "boneless.v:207"
cell $memrd $memrd$\mem$boneless.v:207$295
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regX
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:207$295_DATA
connect \EN 1'x
end
attribute \src "boneless.v:209"
cell $memrd $memrd$\mem$boneless.v:209$297
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:209$297_DATA
connect \EN 1'x
end
attribute \src "boneless.v:209"
cell $memrd $memrd$\mem$boneless.v:209$299
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regX
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:209$299_DATA
connect \EN 1'x
end
attribute \src "boneless.v:210"
cell $memrd $memrd$\mem$boneless.v:210$302
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:210$302_DATA
connect \EN 1'x
end
attribute \src "boneless.v:213"
cell $memrd $memrd$\mem$boneless.v:213$306
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:213$306_DATA
connect \EN 1'x
end
attribute \src "boneless.v:213"
cell $memrd $memrd$\mem$boneless.v:213$307
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regX
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:213$307_DATA
connect \EN 1'x
end
attribute \src "boneless.v:215"
cell $memrd $memrd$\mem$boneless.v:215$310
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:215$310_DATA
connect \EN 1'x
end
attribute \src "boneless.v:215"
cell $memrd $memrd$\mem$boneless.v:215$312
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regX
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:215$312_DATA
connect \EN 1'x
end
attribute \src "boneless.v:216"
cell $memrd $memrd$\mem$boneless.v:216$316
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:216$316_DATA
connect \EN 1'x
end
attribute \src "boneless.v:219"
cell $memrd $memrd$\mem$boneless.v:219$320
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:219$320_DATA
connect \EN 1'x
end
attribute \src "boneless.v:219"
cell $memrd $memrd$\mem$boneless.v:219$321
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regX
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:219$321_DATA
connect \EN 1'x
end
attribute \src "boneless.v:221"
cell $memrd $memrd$\mem$boneless.v:221$324
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:221$324_DATA
connect \EN 1'x
end
attribute \src "boneless.v:221"
cell $memrd $memrd$\mem$boneless.v:221$326
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regX
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:221$326_DATA
connect \EN 1'x
end
attribute \src "boneless.v:222"
cell $memrd $memrd$\mem$boneless.v:222$330
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:222$330_DATA
connect \EN 1'x
end
attribute \src "boneless.v:246"
cell $memrd $memrd$\mem$boneless.v:246$348
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:246$348_DATA
connect \EN 1'x
end
attribute \src "boneless.v:248"
cell $memrd $memrd$\mem$boneless.v:248$351
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:248$351_DATA
connect \EN 1'x
end
attribute \src "boneless.v:249"
cell $memrd $memrd$\mem$boneless.v:249$354
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:249$354_DATA
connect \EN 1'x
end
attribute \src "boneless.v:251"
cell $memrd $memrd$\mem$boneless.v:251$359
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:251$359_DATA
connect \EN 1'x
end
attribute \src "boneless.v:253"
cell $memrd $memrd$\mem$boneless.v:253$362
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:253$362_DATA
connect \EN 1'x
end
attribute \src "boneless.v:265"
cell $memrd $memrd$\mem$boneless.v:265$370
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR $add$boneless.v:265$371_Y
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:265$370_DATA
connect \EN 1'x
end
attribute \src "boneless.v:265"
cell $memrd $memrd$\mem$boneless.v:265$479
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:265$479_DATA
connect \EN 1'x
end
attribute \src "boneless.v:270"
cell $memrd $memrd$\mem$boneless.v:270$375
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:270$375_DATA
connect \EN 1'x
end
attribute \src "boneless.v:271"
cell $memrd $memrd$\mem$boneless.v:271$378
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regZ
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:271$378_DATA
connect \EN 1'x
end
attribute \src "boneless.v:278"
cell $memrd $memrd$\mem$boneless.v:278$385
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:278$385_DATA
connect \EN 1'x
end
attribute \src "boneless.v:285"
cell $memrd $memrd$\mem$boneless.v:285$392
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:285$392_DATA
connect \EN 1'x
end
attribute \src "boneless.v:286"
cell $memrd $memrd$\mem$boneless.v:286$395
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regZ
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:286$395_DATA
connect \EN 1'x
end
attribute \src "boneless.v:289"
cell $memrd $memrd$\mem$boneless.v:289$398
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regY
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:289$398_DATA
connect \EN 1'x
end
attribute \src "boneless.v:289"
cell $memrd $memrd$\mem$boneless.v:289$400
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regZ
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:289$400_DATA
connect \EN 1'x
end
attribute \src "boneless.v:308"
cell $memrd $memrd$\mem$boneless.v:308$420
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regZ
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:308$420_DATA
connect \EN 1'x
end
attribute \src "boneless.v:309"
cell $memrd $memrd$\mem$boneless.v:309$422
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regZ
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:309$422_DATA
connect \EN 1'x
end
attribute \src "boneless.v:310"
cell $memrd $memrd$\mem$boneless.v:310$425
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regZ
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:310$425_DATA
connect \EN 1'x
end
attribute \src "boneless.v:322"
cell $memrd $memrd$\mem$boneless.v:322$438
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR $add$boneless.v:322$440_Y
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:322$438_DATA
connect \EN 1'x
end
attribute \src "boneless.v:328"
cell $memrd $memrd$\mem$boneless.v:328$447
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regZ
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:328$447_DATA
connect \EN 1'x
end
attribute \src "boneless.v:342"
cell $memrd $memrd$\mem$boneless.v:342$460
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \TRANSPARENT 0
parameter \WIDTH 16
connect \ADDR \a_regZ
connect \CLK 1'x
connect \DATA $memrd$\mem$boneless.v:342$460_DATA
connect \EN 1'x
end
attribute \src "boneless.v:26"
cell $memwr $memwr$\ext$boneless.v:26$481
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\ext"
parameter \PRIORITY 481
parameter \WIDTH 16
connect \ADDR $memwr$\ext$boneless.v:26$13_ADDR
connect \CLK 1'x
connect \DATA $memwr$\ext$boneless.v:26$13_DATA
connect \EN $memwr$\ext$boneless.v:26$13_EN
end
attribute \src "boneless.v:15"
cell $memwr $memwr$\mem$boneless.v:15$480
parameter \ABITS 16
parameter \CLK_ENABLE 0
parameter \CLK_POLARITY 0
parameter \MEMID "\\mem"
parameter \PRIORITY 480
parameter \WIDTH 16
connect \ADDR $memwr$\mem$boneless.v:15$12_ADDR
connect \CLK 1'x
connect \DATA $memwr$\mem$boneless.v:15$12_DATA
connect \EN $memwr$\mem$boneless.v:15$12_EN
end
attribute \src "boneless.v:183"
cell $ne $ne$boneless.v:183$276
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
connect \A \i_type2
connect \B 2'11
connect \Y $ne$boneless.v:183$276_Y
end
attribute \src "boneless.v:210"
cell $ne $ne$boneless.v:210$304
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:210$303_Y
connect \B $add$boneless.v:207$296_Y [15]
connect \Y $ne$boneless.v:210$304_Y
end
attribute \src "boneless.v:216"
cell $ne $ne$boneless.v:216$318
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:216$317_Y
connect \B $sub$boneless.v:213$308_Y [15]
connect \Y $ne$boneless.v:216$318_Y
end
attribute \src "boneless.v:222"
cell $ne $ne$boneless.v:222$332
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:222$331_Y
connect \B $sub$boneless.v:219$322_Y [15]
connect \Y $ne$boneless.v:222$332_Y
end
attribute \src "boneless.v:225"
cell $ne $ne$boneless.v:225$334
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 1
connect \A \i_type2
connect \B 2'11
connect \Y $ne$boneless.v:225$334_Y
end
attribute \src "boneless.v:310"
cell $ne $ne$boneless.v:310$427
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $lt$boneless.v:310$426_Y
connect \B $add$boneless.v:308$421_Y [15]
connect \Y $ne$boneless.v:310$427_Y
end
attribute \src "boneless.v:214"
cell $not $not$boneless.v:214$309
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A $sub$boneless.v:213$308_Y [16]
connect \Y $not$boneless.v:214$309_Y
end
attribute \src "boneless.v:220"
cell $not $not$boneless.v:220$323
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A $sub$boneless.v:219$322_Y [16]
connect \Y $not$boneless.v:220$323_Y
end
attribute \src "boneless.v:190"
cell $or $or$boneless.v:190$284
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:190$282_DATA
connect \B $memrd$\mem$boneless.v:190$283_DATA
connect \Y $or$boneless.v:190$284_Y
end
attribute \src "boneless.v:249"
cell $or $or$boneless.v:249$357
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $eq$boneless.v:248$353_Y
connect \B $shr$boneless.v:249$356_Y
connect \Y $or$boneless.v:249$357_Y
end
attribute \src "boneless.v:355"
cell $or $or$boneless.v:355$472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $logic_not$boneless.v:355$471_Y
connect \B \fi_z
connect \Y $or$boneless.v:355$472_Y
end
attribute \src "boneless.v:357"
cell $or $or$boneless.v:357$477
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A $xor$boneless.v:357$476_Y
connect \B \fi_z
connect \Y $or$boneless.v:357$477_Y
end
attribute \src "boneless.v:249"
cell $reduce_bool $reduce_bool$boneless.v:249$358
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \Y_WIDTH 1
connect \A $or$boneless.v:249$357_Y
connect \Y $reduce_bool$boneless.v:249$358_Y
end
attribute \src "boneless.v:246"
cell $shl $shl$boneless.v:246$349
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:246$348_DATA
connect \B \i_shift
connect \Y $shl$boneless.v:246$349_Y
end
attribute \src "boneless.v:248"
cell $shl $shl$boneless.v:248$352
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:248$351_DATA
connect \B \i_shift
connect \Y $shl$boneless.v:248$352_Y
end
attribute \src "boneless.v:298"
cell $shl $shl$boneless.v:298$412
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 1
parameter \B_WIDTH 32
parameter \Y_WIDTH 16
connect \A \i_imm8
connect \B 8
connect \Y $shl$boneless.v:298$412_Y
end
attribute \src "boneless.v:249"
cell $shr $shr$boneless.v:249$356
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 32
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:249$354_DATA
connect \B $sub$boneless.v:249$355_Y
connect \Y $shr$boneless.v:249$356_Y
end
attribute \src "boneless.v:251"
cell $shr $shr$boneless.v:251$360
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:251$359_DATA
connect \B \i_shift
connect \Y $shr$boneless.v:251$360_Y
end
attribute \src "boneless.v:253"
cell $sshr $sshr$boneless.v:253$363
parameter \A_SIGNED 1
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:253$362_DATA
connect \B \i_shift
connect \Y $sshr$boneless.v:253$363_Y
end
attribute \src "boneless.v:213"
cell $sub $sub$boneless.v:213$308
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 17
connect \A $memrd$\mem$boneless.v:213$306_DATA
connect \B $memrd$\mem$boneless.v:213$307_DATA
connect \Y $sub$boneless.v:213$308_Y
end
attribute \src "boneless.v:219"
cell $sub $sub$boneless.v:219$322
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 17
connect \A $memrd$\mem$boneless.v:219$320_DATA
connect \B $memrd$\mem$boneless.v:219$321_DATA
connect \Y $sub$boneless.v:219$322_Y
end
attribute \src "boneless.v:249"
cell $sub $sub$boneless.v:249$355
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 32
connect \A 16
connect \B \i_shift
connect \Y $sub$boneless.v:249$355_Y
end
attribute \src "boneless.v:192"
cell $xor $xor$boneless.v:192$288
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \B_WIDTH 16
parameter \Y_WIDTH 16
connect \A $memrd$\mem$boneless.v:192$286_DATA
connect \B $memrd$\mem$boneless.v:192$287_DATA
connect \Y $xor$boneless.v:192$288_Y
end
attribute \src "boneless.v:356"
cell $xor $xor$boneless.v:356$474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_s
connect \B \fi_v
connect \Y $xor$boneless.v:356$474_Y
end
attribute \src "boneless.v:357"
cell $xor $xor$boneless.v:357$476
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \fi_s
connect \B \fi_v
connect \Y $xor$boneless.v:357$476_Y
end
attribute \module_not_derived 1
attribute \src "boneless.v:45"
cell \boneless \cpu
connect \clk \clk
connect \ext_addr \ext_addr
connect \ext_r_data \ext_r_data
connect \ext_r_en \ext_r_en
connect \ext_w_data \ext_w_data
connect \ext_w_en \ext_w_en
connect \fi_ext_addr \fi_ext_addr
connect \fi_ext_r_data \fi_ext_r_data
connect \fi_ext_r_en \fi_ext_r_en
connect \fi_ext_w_data \fi_ext_w_data
connect \fi_ext_w_en \fi_ext_w_en
connect \fi_flags \fi_flags
connect \fi_insn \fi_insn
connect \fi_mem_w_addr \fi_mem_w_addr
connect \fi_mem_w_data \fi_mem_w_data
connect \fi_mem_w_en \fi_mem_w_en
connect \fi_pc \fi_pc
connect \fi_stb \fi_stb
connect \mem_r_addr \mem_r_addr
connect \mem_r_data \mem_r_data
connect \mem_r_en \mem_r_en
connect \mem_w_addr \mem_w_addr
connect \mem_w_data \mem_w_data
connect \mem_w_en \mem_w_en
connect \r_win \r_win
connect \rst 0
end
attribute \src "boneless.v:13"
process $proc$boneless.v:13$89
assign $0\mem_r_data[15:0] \mem_r_data
assign { } { }
assign { } { }
assign { } { }
assign $0$memwr$\mem$boneless.v:15$12_ADDR[15:0]$90 16'xxxxxxxxxxxxxxxx
assign $0$memwr$\mem$boneless.v:15$12_DATA[15:0]$91 16'xxxxxxxxxxxxxxxx
assign $0$memwr$\mem$boneless.v:15$12_EN[15:0]$92 16'0000000000000000
attribute \src "boneless.v:14"
switch \mem_r_en
case 1'1
assign $0\mem_r_data[15:0] $memrd$\mem$boneless.v:14$93_DATA
case
end
attribute \src "boneless.v:15"
switch \mem_w_en
case 1'1
assign $0$memwr$\mem$boneless.v:15$12_ADDR[15:0]$90 \mem_w_addr
assign $0$memwr$\mem$boneless.v:15$12_DATA[15:0]$91 \mem_w_data
assign $0$memwr$\mem$boneless.v:15$12_EN[15:0]$92 16'1111111111111111
case
end
sync posedge \clk
update \mem_r_data $0\mem_r_data[15:0]
update $memwr$\mem$boneless.v:15$12_ADDR $0$memwr$\mem$boneless.v:15$12_ADDR[15:0]$90
update $memwr$\mem$boneless.v:15$12_DATA $0$memwr$\mem$boneless.v:15$12_DATA[15:0]$91
update $memwr$\mem$boneless.v:15$12_EN $0$memwr$\mem$boneless.v:15$12_EN[15:0]$92
end
attribute \src "boneless.v:151"
process $proc$boneless.v:151$558
assign { } { }
assign $1\fs_jumped[0:0] 1'0
sync always
sync init
update \fs_jumped $1\fs_jumped[0:0]
end
attribute \src "boneless.v:152"
process $proc$boneless.v:152$559
assign { } { }
assign $1\fs_past_ext_r_en[0:0] 1'0
sync always
sync init
update \fs_past_ext_r_en $1\fs_past_ext_r_en[0:0]
end
attribute \src "boneless.v:153"
process $proc$boneless.v:153$560
assign { } { }
assign $1\fs_past_ext_w_en[0:0] 1'0
sync always
sync init
update \fs_past_ext_w_en $1\fs_past_ext_w_en[0:0]
end
attribute \src "boneless.v:154"
process $proc$boneless.v:154$561
assign { } { }
assign $1\fs_past_ext_adr[0:0] 1'0
sync always
sync init
update \fs_past_ext_adr $1\fs_past_ext_adr[0:0]
end
attribute \src "boneless.v:155"
process $proc$boneless.v:155$104
assign $0\fs_next_pc[15:0] \fs_next_pc
assign $0\fs_jumped[0:0] \fs_jumped
assign $0\fs_past_ext_r_en[0:0] \fs_past_ext_r_en
assign $0\fs_past_ext_w_en[0:0] \fs_past_ext_w_en
assign $0\fs_past_ext_adr[0:0] \fs_past_ext_adr
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
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assign { } { }
assign $0$formal$boneless.v:347$88_CHECK[0:0]$264 1'x
assign $0$formal$boneless.v:347$88_EN[0:0]$265 1'0
assign $0$formal$boneless.v:346$87_CHECK[0:0]$262 1'x
assign $0$formal$boneless.v:346$87_EN[0:0]$263 1'0
assign $0$formal$boneless.v:341$86_CHECK[0:0]$260 1'x
assign $0$formal$boneless.v:341$86_EN[0:0]$261 1'0
assign $0$formal$boneless.v:340$85_CHECK[0:0]$258 1'x
assign $0$formal$boneless.v:340$85_EN[0:0]$259 1'0
assign $0$formal$boneless.v:335$84_CHECK[0:0]$256 1'x
assign $0$formal$boneless.v:335$84_EN[0:0]$257 1'0
assign $0$formal$boneless.v:334$83_CHECK[0:0]$254 1'x
assign $0$formal$boneless.v:334$83_EN[0:0]$255 1'0
assign $0$formal$boneless.v:333$82_CHECK[0:0]$252 1'x
assign $0$formal$boneless.v:333$82_EN[0:0]$253 1'0
assign $0$formal$boneless.v:332$81_CHECK[0:0]$250 1'x
assign $0$formal$boneless.v:332$81_EN[0:0]$251 1'0
assign $0$formal$boneless.v:329$80_CHECK[0:0]$248 1'x
assign $0$formal$boneless.v:329$80_EN[0:0]$249 1'0
assign $0$formal$boneless.v:328$79_CHECK[0:0]$246 1'x
assign $0$formal$boneless.v:328$79_EN[0:0]$247 1'0
assign $0$formal$boneless.v:327$78_CHECK[0:0]$244 1'x
assign $0$formal$boneless.v:327$78_EN[0:0]$245 1'0
assign $0$formal$boneless.v:326$77_CHECK[0:0]$242 1'x
assign $0$formal$boneless.v:326$77_EN[0:0]$243 1'0
assign $0$formal$boneless.v:323$76_CHECK[0:0]$240 1'x
assign $0$formal$boneless.v:323$76_EN[0:0]$241 1'0
assign $0$formal$boneless.v:322$75_CHECK[0:0]$238 1'x
assign $0$formal$boneless.v:322$75_EN[0:0]$239 1'0
assign $0$formal$boneless.v:321$74_CHECK[0:0]$236 1'x
assign $0$formal$boneless.v:321$74_EN[0:0]$237 1'0
assign $0$formal$boneless.v:320$73_CHECK[0:0]$234 1'x
assign $0$formal$boneless.v:320$73_EN[0:0]$235 1'0
assign $0$formal$boneless.v:317$72_CHECK[0:0]$232 1'x
assign $0$formal$boneless.v:317$72_EN[0:0]$233 1'0
assign $0$formal$boneless.v:316$71_CHECK[0:0]$230 1'x
assign $0$formal$boneless.v:316$71_EN[0:0]$231 1'0
assign $0$formal$boneless.v:315$70_CHECK[0:0]$228 1'x
assign $0$formal$boneless.v:315$70_EN[0:0]$229 1'0
assign $0$formal$boneless.v:314$69_CHECK[0:0]$226 1'x
assign $0$formal$boneless.v:314$69_EN[0:0]$227 1'0
assign $0$formal$boneless.v:313$68_CHECK[0:0]$224 1'x
assign $0$formal$boneless.v:313$68_EN[0:0]$225 1'0
assign $0$formal$boneless.v:312$67_CHECK[0:0]$222 1'x
assign $0$formal$boneless.v:312$67_EN[0:0]$223 1'0
assign $0$formal$boneless.v:311$66_CHECK[0:0]$220 1'x
assign $0$formal$boneless.v:311$66_EN[0:0]$221 1'0
assign $0$formal$boneless.v:301$65_CHECK[0:0]$218 1'x
assign $0$formal$boneless.v:301$65_EN[0:0]$219 1'0
assign $0$formal$boneless.v:300$64_CHECK[0:0]$216 1'x
assign $0$formal$boneless.v:300$64_EN[0:0]$217 1'0
assign $0$formal$boneless.v:298$63_CHECK[0:0]$214 1'x
assign $0$formal$boneless.v:298$63_EN[0:0]$215 1'0
assign $0$formal$boneless.v:296$62_CHECK[0:0]$212 1'x
assign $0$formal$boneless.v:296$62_EN[0:0]$213 1'0
assign $0$formal$boneless.v:294$61_CHECK[0:0]$210 1'x
assign $0$formal$boneless.v:294$61_EN[0:0]$211 1'0
assign $0$formal$boneless.v:293$60_CHECK[0:0]$208 1'x
assign $0$formal$boneless.v:293$60_EN[0:0]$209 1'0
assign $0$formal$boneless.v:290$59_CHECK[0:0]$206 1'x
assign $0$formal$boneless.v:290$59_EN[0:0]$207 1'0
assign $0$formal$boneless.v:289$58_CHECK[0:0]$204 1'x
assign $0$formal$boneless.v:289$58_EN[0:0]$205 1'0
assign $0$formal$boneless.v:286$57_CHECK[0:0]$202 1'x
assign $0$formal$boneless.v:286$57_EN[0:0]$203 1'0
assign $0$formal$boneless.v:285$56_CHECK[0:0]$200 1'x
assign $0$formal$boneless.v:285$56_EN[0:0]$201 1'0
assign $0$formal$boneless.v:283$55_CHECK[0:0]$198 1'x
assign $0$formal$boneless.v:283$55_EN[0:0]$199 1'0
assign $0$formal$boneless.v:282$54_CHECK[0:0]$196 1'x
assign $0$formal$boneless.v:282$54_EN[0:0]$197 1'0
assign $0$formal$boneless.v:279$53_CHECK[0:0]$194 1'x
assign $0$formal$boneless.v:279$53_EN[0:0]$195 1'0
assign $0$formal$boneless.v:278$52_CHECK[0:0]$192 1'x
assign $0$formal$boneless.v:278$52_EN[0:0]$193 1'0
assign $0$formal$boneless.v:277$51_CHECK[0:0]$190 1'x
assign $0$formal$boneless.v:277$51_EN[0:0]$191 1'0
assign $0$formal$boneless.v:276$50_CHECK[0:0]$188 1'x
assign $0$formal$boneless.v:276$50_EN[0:0]$189 1'0
assign $0$formal$boneless.v:275$49_CHECK[0:0]$186 1'x
assign $0$formal$boneless.v:275$49_EN[0:0]$187 1'0
assign $0$formal$boneless.v:272$48_CHECK[0:0]$184 1'x
assign $0$formal$boneless.v:272$48_EN[0:0]$185 1'0
assign $0$formal$boneless.v:271$47_CHECK[0:0]$182 1'x
assign $0$formal$boneless.v:271$47_EN[0:0]$183 1'0
assign $0$formal$boneless.v:270$46_CHECK[0:0]$180 1'x
assign $0$formal$boneless.v:270$46_EN[0:0]$181 1'0
assign $0$formal$boneless.v:269$45_CHECK[0:0]$178 1'x
assign $0$formal$boneless.v:269$45_EN[0:0]$179 1'0
assign $0$formal$boneless.v:266$44_CHECK[0:0]$176 1'x
assign $0$formal$boneless.v:266$44_EN[0:0]$177 1'0
assign $0$formal$boneless.v:265$43_CHECK[0:0]$174 1'x
assign $0$formal$boneless.v:265$43_EN[0:0]$175 1'0
assign $0$formal$boneless.v:262$42_CHECK[0:0]$172 1'x
assign $0$formal$boneless.v:262$42_EN[0:0]$173 1'0
assign $0$formal$boneless.v:261$41_CHECK[0:0]$170 1'x
assign $0$formal$boneless.v:261$41_EN[0:0]$171 1'0
assign $0$formal$boneless.v:256$40_CHECK[0:0]$168 1'x
assign $0$formal$boneless.v:256$40_EN[0:0]$169 1'0
assign $0$formal$boneless.v:255$39_CHECK[0:0]$166 1'x
assign $0$formal$boneless.v:255$39_EN[0:0]$167 1'0
assign $0$formal$boneless.v:253$38_CHECK[0:0]$164 1'x
assign $0$formal$boneless.v:253$38_EN[0:0]$165 1'0
assign $0$formal$boneless.v:251$37_CHECK[0:0]$162 1'x
assign $0$formal$boneless.v:251$37_EN[0:0]$163 1'0
assign $0$formal$boneless.v:249$36_CHECK[0:0]$160 1'x
assign $0$formal$boneless.v:249$36_EN[0:0]$161 1'0
assign $0$formal$boneless.v:246$35_CHECK[0:0]$158 1'x
assign $0$formal$boneless.v:246$35_EN[0:0]$159 1'0
assign $0$formal$boneless.v:243$34_CHECK[0:0]$156 1'x
assign $0$formal$boneless.v:243$34_EN[0:0]$157 1'0
assign $0$formal$boneless.v:242$33_CHECK[0:0]$154 1'x
assign $0$formal$boneless.v:242$33_EN[0:0]$155 1'0
assign $0$formal$boneless.v:236$32_CHECK[0:0]$152 1'x
assign $0$formal$boneless.v:236$32_EN[0:0]$153 1'0
assign $0$formal$boneless.v:235$31_CHECK[0:0]$150 1'x
assign $0$formal$boneless.v:235$31_EN[0:0]$151 1'0
assign $0$formal$boneless.v:234$30_CHECK[0:0]$148 1'x
assign $0$formal$boneless.v:234$30_EN[0:0]$149 1'0
assign $0$formal$boneless.v:233$29_CHECK[0:0]$146 1'x
assign $0$formal$boneless.v:233$29_EN[0:0]$147 1'0
assign $0$formal$boneless.v:231$28_CHECK[0:0]$144 1'x
assign $0$formal$boneless.v:231$28_EN[0:0]$145 1'0
assign $0$formal$boneless.v:230$27_CHECK[0:0]$142 1'x
assign $0$formal$boneless.v:230$27_EN[0:0]$143 1'0
assign $0$formal$boneless.v:229$26_CHECK[0:0]$140 1'x
assign $0$formal$boneless.v:229$26_EN[0:0]$141 1'0
assign $0$formal$boneless.v:227$25_CHECK[0:0]$138 1'x
assign $0$formal$boneless.v:227$25_EN[0:0]$139 1'0
assign $0$formal$boneless.v:195$24_CHECK[0:0]$136 1'x
assign $0$formal$boneless.v:195$24_EN[0:0]$137 1'0
assign $0$formal$boneless.v:194$23_CHECK[0:0]$134 1'x
assign $0$formal$boneless.v:194$23_EN[0:0]$135 1'0
assign $0$formal$boneless.v:192$22_CHECK[0:0]$132 1'x
assign $0$formal$boneless.v:192$22_EN[0:0]$133 1'0
assign $0$formal$boneless.v:190$21_CHECK[0:0]$130 1'x
assign $0$formal$boneless.v:190$21_EN[0:0]$131 1'0
assign $0$formal$boneless.v:188$20_CHECK[0:0]$128 1'x
assign $0$formal$boneless.v:188$20_EN[0:0]$129 1'0
assign $0$formal$boneless.v:185$19_CHECK[0:0]$126 1'x
assign $0$formal$boneless.v:185$19_EN[0:0]$127 1'0
assign $0$formal$boneless.v:184$18_CHECK[0:0]$124 1'x
assign $0$formal$boneless.v:184$18_EN[0:0]$125 1'0
assign $0$formal$boneless.v:179$17_CHECK[0:0]$122 1'x
assign $0$formal$boneless.v:179$17_EN[0:0]$123 1'0
assign $0$formal$boneless.v:173$16_CHECK[0:0]$120 1'x
assign $0$formal$boneless.v:173$16_EN[0:0]$121 1'0
assign $0$formal$boneless.v:169$15_CHECK[0:0]$118 1'x
assign $0$formal$boneless.v:169$15_EN[0:0]$119 1'0
assign $0$formal$boneless.v:161$14_CHECK[0:0]$116 1'x
assign $0$formal$boneless.v:161$14_EN[0:0]$117 1'0
assign $0\stb.arith.res[16:0] $1\stb.arith.res[16:0]
assign $0\stb.arith.c[0:0] $1\stb.arith.c[0:0]
assign $0\stb.arith.v[0:0] $1\stb.arith.v[0:0]
assign $0\stb.addi.tmp[15:0] $1\stb.addi.tmp[15:0]
assign $0\stb.addi.res[16:0] $1\stb.addi.res[16:0]
assign $0\stb.addi.v[0:0] $1\stb.addi.v[0:0]
assign $0$past$boneless.v:265$1$0[15:0]$105 $memrd$\mem$boneless.v:265$479_DATA
assign $0$past$boneless.v:266$2$0[3:0]$106 \fi_flags
assign $0$past$boneless.v:272$3$0[3:0]$107 \fi_flags
assign $0$past$boneless.v:279$4$0[3:0]$108 \fi_flags
assign $0$past$boneless.v:290$5$0[3:0]$109 \fi_flags
assign $0$past$boneless.v:301$6$0[3:0]$110 \fi_flags
assign $0$past$boneless.v:323$7$0[3:0]$111 \fi_flags
assign $0$past$boneless.v:329$8$0[3:0]$112 \fi_flags
assign $0$past$boneless.v:335$9$0[3:0]$113 \fi_flags
assign $0$past$boneless.v:341$10$0[3:0]$114 \fi_flags
assign $0$past$boneless.v:347$11$0[3:0]$115 \fi_flags
attribute \src "boneless.v:160"
switch $logic_or$boneless.v:160$266_Y
case 1'1
assign $0$formal$boneless.v:161$14_CHECK[0:0]$116 $logic_and$boneless.v:161$269_Y
assign $0$formal$boneless.v:161$14_EN[0:0]$117 1'1
assign $0\fs_past_ext_r_en[0:0] \fi_ext_r_en
assign $0\fs_past_ext_w_en[0:0] \fi_ext_w_en
assign $0\fs_past_ext_adr[0:0] \fi_ext_addr [0]
case
end
attribute \src "boneless.v:167"
switch \fi_stb
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign $1\stb.arith.res[16:0] $2\stb.arith.res[16:0]
assign $1\stb.arith.c[0:0] $2\stb.arith.c[0:0]
assign $1\stb.arith.v[0:0] $2\stb.arith.v[0:0]
assign $1\stb.addi.tmp[15:0] $2\stb.addi.tmp[15:0]
assign $1\stb.addi.res[16:0] $2\stb.addi.res[16:0]
assign $1\stb.addi.v[0:0] $2\stb.addi.v[0:0]
attribute \src "boneless.v:168"
switch $logic_or$boneless.v:168$270_Y
case 1'1
assign $0$formal$boneless.v:169$15_CHECK[0:0]$118 $eq$boneless.v:169$271_Y
assign $0$formal$boneless.v:169$15_EN[0:0]$119 1'1
assign $0\fs_past_ext_r_en[0:0] 1'0
case
end
attribute \src "boneless.v:172"
switch $logic_or$boneless.v:172$272_Y
case 1'1
assign $0$formal$boneless.v:173$16_CHECK[0:0]$120 $eq$boneless.v:173$273_Y
assign $0$formal$boneless.v:173$16_EN[0:0]$121 1'1
assign $0\fs_past_ext_w_en[0:0] 1'0
case
end
attribute \src "boneless.v:177"
switch \fs_jumped
case 1'1
assign $0\fs_jumped[0:0] 1'0
assign $0$formal$boneless.v:179$17_CHECK[0:0]$122 $eq$boneless.v:179$274_Y
assign $0$formal$boneless.v:179$17_EN[0:0]$123 1'1
case
end
attribute \src "boneless.v:182"
switch $eq$boneless.v:182$275_Y
case 1'1
attribute \src "boneless.v:183"
switch $ne$boneless.v:183$276_Y
case 1'1
assign $0$formal$boneless.v:184$18_CHECK[0:0]$124 \fi_mem_w_en
assign $0$formal$boneless.v:184$18_EN[0:0]$125 1'1
assign $0$formal$boneless.v:185$19_CHECK[0:0]$126 $eq$boneless.v:185$277_Y
assign $0$formal$boneless.v:185$19_EN[0:0]$127 1'1
assign $0$formal$boneless.v:194$23_CHECK[0:0]$134 $eq$boneless.v:194$291_Y
assign $0$formal$boneless.v:194$23_EN[0:0]$135 1'1
assign $0$formal$boneless.v:195$24_CHECK[0:0]$136 $eq$boneless.v:195$292_Y
assign $0$formal$boneless.v:195$24_EN[0:0]$137 1'1
attribute \src "boneless.v:186"
switch \i_type2
case 2'00
assign $0$formal$boneless.v:188$20_CHECK[0:0]$128 $eq$boneless.v:188$281_Y
assign $0$formal$boneless.v:188$20_EN[0:0]$129 1'1
case 2'01
assign $0$formal$boneless.v:190$21_CHECK[0:0]$130 $eq$boneless.v:190$285_Y
assign $0$formal$boneless.v:190$21_EN[0:0]$131 1'1
case 2'10
assign $0$formal$boneless.v:192$22_CHECK[0:0]$132 $eq$boneless.v:192$289_Y
assign $0$formal$boneless.v:192$22_EN[0:0]$133 1'1
case
end
case
end
case
end
attribute \src "boneless.v:202"
switch $eq$boneless.v:202$293_Y
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign $2\stb.arith.res[16:0] $3\stb.arith.res[16:0]
assign $2\stb.arith.c[0:0] $3\stb.arith.c[0:0]
assign $2\stb.arith.v[0:0] $3\stb.arith.v[0:0]
attribute \src "boneless.v:205"
switch \i_type2
case 2'00
assign { } { }
assign { } { }
assign { } { }
assign $3\stb.arith.res[16:0] $add$boneless.v:207$296_Y
assign $3\stb.arith.c[0:0] $add$boneless.v:207$296_Y [16]
assign $3\stb.arith.v[0:0] $logic_and$boneless.v:210$305_Y
case 2'01
assign { } { }
assign { } { }
assign { } { }
assign $3\stb.arith.res[16:0] $sub$boneless.v:213$308_Y
assign $3\stb.arith.c[0:0] $not$boneless.v:214$309_Y
assign $3\stb.arith.v[0:0] $logic_and$boneless.v:216$319_Y
case 2'10
assign { } { }
assign { } { }
assign { } { }
assign $3\stb.arith.res[16:0] $sub$boneless.v:219$322_Y
assign $3\stb.arith.c[0:0] $not$boneless.v:220$323_Y
assign $3\stb.arith.v[0:0] $logic_and$boneless.v:222$333_Y
case
assign $3\stb.arith.res[16:0] \stb.arith.res
assign $3\stb.arith.c[0:0] \stb.arith.c
assign $3\stb.arith.v[0:0] \stb.arith.v
end
attribute \src "boneless.v:225"
switch $ne$boneless.v:225$334_Y
case 1'1
assign $0$formal$boneless.v:233$29_CHECK[0:0]$146 $eq$boneless.v:233$340_Y
assign $0$formal$boneless.v:233$29_EN[0:0]$147 1'1
assign $0$formal$boneless.v:234$30_CHECK[0:0]$148 $eq$boneless.v:234$341_Y
assign $0$formal$boneless.v:234$30_EN[0:0]$149 1'1
assign $0$formal$boneless.v:235$31_CHECK[0:0]$150 $eq$boneless.v:235$342_Y
assign $0$formal$boneless.v:235$31_EN[0:0]$151 1'1
assign $0$formal$boneless.v:236$32_CHECK[0:0]$152 $eq$boneless.v:236$343_Y
assign $0$formal$boneless.v:236$32_EN[0:0]$153 1'1
attribute \src "boneless.v:226"
switch $eq$boneless.v:226$335_Y
case 1'1
assign $0$formal$boneless.v:227$25_CHECK[0:0]$138 $logic_not$boneless.v:227$336_Y
assign $0$formal$boneless.v:227$25_EN[0:0]$139 1'1
case
assign $0$formal$boneless.v:229$26_CHECK[0:0]$140 \fi_mem_w_en
assign $0$formal$boneless.v:229$26_EN[0:0]$141 1'1
assign $0$formal$boneless.v:230$27_CHECK[0:0]$142 $eq$boneless.v:230$337_Y
assign $0$formal$boneless.v:230$27_EN[0:0]$143 1'1
assign $0$formal$boneless.v:231$28_CHECK[0:0]$144 $eq$boneless.v:231$338_Y
assign $0$formal$boneless.v:231$28_EN[0:0]$145 1'1
end
case
end
case
assign $2\stb.arith.res[16:0] \stb.arith.res
assign $2\stb.arith.c[0:0] \stb.arith.c
assign $2\stb.arith.v[0:0] \stb.arith.v
end
attribute \src "boneless.v:241"
switch $logic_or$boneless.v:241$346_Y
case 1'1
assign $0$formal$boneless.v:242$33_CHECK[0:0]$154 \fi_mem_w_en
assign $0$formal$boneless.v:242$33_EN[0:0]$155 1'1
assign $0$formal$boneless.v:243$34_CHECK[0:0]$156 $eq$boneless.v:243$347_Y
assign $0$formal$boneless.v:243$34_EN[0:0]$157 1'1
assign $0$formal$boneless.v:255$39_CHECK[0:0]$166 $eq$boneless.v:255$366_Y
assign $0$formal$boneless.v:255$39_EN[0:0]$167 1'1
assign $0$formal$boneless.v:256$40_CHECK[0:0]$168 $eq$boneless.v:256$367_Y
assign $0$formal$boneless.v:256$40_EN[0:0]$169 1'1
attribute \src "boneless.v:244"
switch { \i_code5 \i_type1 }
case 6'000010, 6'000000
assign $0$formal$boneless.v:246$35_CHECK[0:0]$158 $eq$boneless.v:246$350_Y
assign $0$formal$boneless.v:246$35_EN[0:0]$159 1'1
case 6'000010, 6'000001
assign $0$formal$boneless.v:249$36_CHECK[0:0]$160 $reduce_bool$boneless.v:249$358_Y
assign $0$formal$boneless.v:249$36_EN[0:0]$161 1'1
case 6'000011, 6'000000
assign $0$formal$boneless.v:251$37_CHECK[0:0]$162 $eq$boneless.v:251$361_Y
assign $0$formal$boneless.v:251$37_EN[0:0]$163 1'1
case 6'000011, 6'000001
assign $0$formal$boneless.v:253$38_CHECK[0:0]$164 $eq$boneless.v:253$364_Y
assign $0$formal$boneless.v:253$38_EN[0:0]$165 1'1
case
end
case
end
attribute \src "boneless.v:260"
switch $eq$boneless.v:260$368_Y
case 1'1
assign $0$formal$boneless.v:261$41_CHECK[0:0]$170 \fi_mem_w_en
assign $0$formal$boneless.v:261$41_EN[0:0]$171 1'1
assign $0$formal$boneless.v:262$42_CHECK[0:0]$172 $eq$boneless.v:262$369_Y
assign $0$formal$boneless.v:262$42_EN[0:0]$173 1'1
assign $0$formal$boneless.v:265$43_CHECK[0:0]$174 $eq$boneless.v:265$372_Y
assign $0$formal$boneless.v:265$43_EN[0:0]$175 1'1
assign $0$formal$boneless.v:266$44_CHECK[0:0]$176 $eq$boneless.v:266$373_Y
assign $0$formal$boneless.v:266$44_EN[0:0]$177 1'1
case
end
attribute \src "boneless.v:268"
switch $eq$boneless.v:268$374_Y
case 1'1
assign $0$formal$boneless.v:269$45_CHECK[0:0]$178 \fi_mem_w_en
assign $0$formal$boneless.v:269$45_EN[0:0]$179 1'1
assign $0$formal$boneless.v:270$46_CHECK[0:0]$180 $eq$boneless.v:270$377_Y
assign $0$formal$boneless.v:270$46_EN[0:0]$181 1'1
assign $0$formal$boneless.v:271$47_CHECK[0:0]$182 $eq$boneless.v:271$379_Y
assign $0$formal$boneless.v:271$47_EN[0:0]$183 1'1
assign $0$formal$boneless.v:272$48_CHECK[0:0]$184 $eq$boneless.v:272$380_Y
assign $0$formal$boneless.v:272$48_EN[0:0]$185 1'1
case
end
attribute \src "boneless.v:274"
switch $eq$boneless.v:274$381_Y
case 1'1
assign $0$formal$boneless.v:275$49_CHECK[0:0]$186 \fi_mem_w_en
assign $0$formal$boneless.v:275$49_EN[0:0]$187 1'1
assign $0$formal$boneless.v:276$50_CHECK[0:0]$188 $logic_or$boneless.v:276$382_Y
assign $0$formal$boneless.v:276$50_EN[0:0]$189 1'1
assign $0$formal$boneless.v:277$51_CHECK[0:0]$190 $eq$boneless.v:277$383_Y
assign $0$formal$boneless.v:277$51_EN[0:0]$191 1'1
assign $0$formal$boneless.v:278$52_CHECK[0:0]$192 $eq$boneless.v:278$387_Y
assign $0$formal$boneless.v:278$52_EN[0:0]$193 1'1
assign $0$formal$boneless.v:279$53_CHECK[0:0]$194 $eq$boneless.v:279$388_Y
assign $0$formal$boneless.v:279$53_EN[0:0]$195 1'1
case
end
attribute \src "boneless.v:281"
switch $eq$boneless.v:281$389_Y
case 1'1
assign $0$formal$boneless.v:282$54_CHECK[0:0]$196 $logic_not$boneless.v:282$390_Y
assign $0$formal$boneless.v:282$54_EN[0:0]$197 1'1
assign $0$formal$boneless.v:283$55_CHECK[0:0]$198 $logic_or$boneless.v:283$391_Y
assign $0$formal$boneless.v:283$55_EN[0:0]$199 1'1
assign $0$formal$boneless.v:290$59_CHECK[0:0]$206 $eq$boneless.v:290$402_Y
assign $0$formal$boneless.v:290$59_EN[0:0]$207 1'1
attribute \src "boneless.v:284"
switch \fi_ext_w_en
case 1'1
assign $0$formal$boneless.v:285$56_CHECK[0:0]$200 $eq$boneless.v:285$394_Y
assign $0$formal$boneless.v:285$56_EN[0:0]$201 1'1
assign $0$formal$boneless.v:286$57_CHECK[0:0]$202 $eq$boneless.v:286$396_Y
assign $0$formal$boneless.v:286$57_EN[0:0]$203 1'1
case
end
attribute \src "boneless.v:288"
switch \fs_past_ext_w_en
case 1'1
assign $0$formal$boneless.v:289$58_CHECK[0:0]$204 $eq$boneless.v:289$401_Y
assign $0$formal$boneless.v:289$58_EN[0:0]$205 1'1
case
end
case
end
attribute \src "boneless.v:292"
switch $logic_or$boneless.v:292$407_Y
case 1'1
assign $0$formal$boneless.v:293$60_CHECK[0:0]$208 \fi_mem_w_en
assign $0$formal$boneless.v:293$60_EN[0:0]$209 1'1
assign $0$formal$boneless.v:294$61_CHECK[0:0]$210 $eq$boneless.v:294$408_Y
assign $0$formal$boneless.v:294$61_EN[0:0]$211 1'1
assign $0$formal$boneless.v:301$65_CHECK[0:0]$218 $eq$boneless.v:301$418_Y
assign $0$formal$boneless.v:301$65_EN[0:0]$219 1'1
attribute \src "boneless.v:295"
switch $eq$boneless.v:295$409_Y
case 1'1
assign $0$formal$boneless.v:296$62_CHECK[0:0]$212 $eq$boneless.v:296$410_Y
assign $0$formal$boneless.v:296$62_EN[0:0]$213 1'1
case
end
attribute \src "boneless.v:297"
switch $eq$boneless.v:297$411_Y
case 1'1
assign $0$formal$boneless.v:298$63_CHECK[0:0]$214 $eq$boneless.v:298$413_Y
assign $0$formal$boneless.v:298$63_EN[0:0]$215 1'1
case
end
attribute \src "boneless.v:299"
switch $eq$boneless.v:299$414_Y
case 1'1
assign $0$formal$boneless.v:300$64_CHECK[0:0]$216 $eq$boneless.v:300$417_Y
assign $0$formal$boneless.v:300$64_EN[0:0]$217 1'1
case
end
case
end
attribute \src "boneless.v:303"
switch $eq$boneless.v:303$419_Y
case 1'1
assign { } { }
assign { } { }
assign { } { }
assign $2\stb.addi.tmp[15:0] { \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 [7] \i_imm8 }
assign $2\stb.addi.res[16:0] $add$boneless.v:308$421_Y
assign $2\stb.addi.v[0:0] $logic_and$boneless.v:310$428_Y
assign $0$formal$boneless.v:311$66_CHECK[0:0]$220 \fi_mem_w_en
assign $0$formal$boneless.v:311$66_EN[0:0]$221 1'1
assign $0$formal$boneless.v:312$67_CHECK[0:0]$222 $eq$boneless.v:312$429_Y
assign $0$formal$boneless.v:312$67_EN[0:0]$223 1'1
assign $0$formal$boneless.v:313$68_CHECK[0:0]$224 $eq$boneless.v:313$430_Y
assign $0$formal$boneless.v:313$68_EN[0:0]$225 1'1
assign $0$formal$boneless.v:314$69_CHECK[0:0]$226 $eq$boneless.v:314$432_Y
assign $0$formal$boneless.v:314$69_EN[0:0]$227 1'1
assign $0$formal$boneless.v:315$70_CHECK[0:0]$228 $eq$boneless.v:315$433_Y
assign $0$formal$boneless.v:315$70_EN[0:0]$229 1'1
assign $0$formal$boneless.v:316$71_CHECK[0:0]$230 $eq$boneless.v:316$434_Y
assign $0$formal$boneless.v:316$71_EN[0:0]$231 1'1
assign $0$formal$boneless.v:317$72_CHECK[0:0]$232 $eq$boneless.v:317$435_Y
assign $0$formal$boneless.v:317$72_EN[0:0]$233 1'1
case
assign $2\stb.addi.tmp[15:0] \stb.addi.tmp
assign $2\stb.addi.res[16:0] \stb.addi.res
assign $2\stb.addi.v[0:0] \stb.addi.v
end
attribute \src "boneless.v:319"
switch $eq$boneless.v:319$436_Y
case 1'1
assign $0$formal$boneless.v:320$73_CHECK[0:0]$234 \fi_mem_w_en
assign $0$formal$boneless.v:320$73_EN[0:0]$235 1'1
assign $0$formal$boneless.v:321$74_CHECK[0:0]$236 $eq$boneless.v:321$437_Y
assign $0$formal$boneless.v:321$74_EN[0:0]$237 1'1
assign $0$formal$boneless.v:322$75_CHECK[0:0]$238 $eq$boneless.v:322$441_Y
assign $0$formal$boneless.v:322$75_EN[0:0]$239 1'1
assign $0$formal$boneless.v:323$76_CHECK[0:0]$240 $eq$boneless.v:323$442_Y
assign $0$formal$boneless.v:323$76_EN[0:0]$241 1'1
case
end
attribute \src "boneless.v:325"
switch $eq$boneless.v:325$443_Y
case 1'1
assign $0$formal$boneless.v:326$77_CHECK[0:0]$242 \fi_mem_w_en
assign $0$formal$boneless.v:326$77_EN[0:0]$243 1'1
assign $0$formal$boneless.v:327$78_CHECK[0:0]$244 $eq$boneless.v:327$446_Y
assign $0$formal$boneless.v:327$78_EN[0:0]$245 1'1
assign $0$formal$boneless.v:328$79_CHECK[0:0]$246 $eq$boneless.v:328$448_Y
assign $0$formal$boneless.v:328$79_EN[0:0]$247 1'1
assign $0$formal$boneless.v:329$80_CHECK[0:0]$248 $eq$boneless.v:329$449_Y
assign $0$formal$boneless.v:329$80_EN[0:0]$249 1'1
case
end
attribute \src "boneless.v:331"
switch $eq$boneless.v:331$450_Y
case 1'1
assign $0$formal$boneless.v:332$81_CHECK[0:0]$250 \fi_mem_w_en
assign $0$formal$boneless.v:332$81_EN[0:0]$251 1'1
assign $0$formal$boneless.v:333$82_CHECK[0:0]$252 $eq$boneless.v:333$451_Y
assign $0$formal$boneless.v:333$82_EN[0:0]$253 1'1
assign $0$formal$boneless.v:334$83_CHECK[0:0]$254 $eq$boneless.v:334$453_Y
assign $0$formal$boneless.v:334$83_EN[0:0]$255 1'1
assign $0$formal$boneless.v:335$84_CHECK[0:0]$256 $eq$boneless.v:335$454_Y
assign $0$formal$boneless.v:335$84_EN[0:0]$257 1'1
assign $0\fs_next_pc[15:0] $add$boneless.v:336$456_Y
assign $0\fs_jumped[0:0] 1'1
case
end
attribute \src "boneless.v:339"
switch $eq$boneless.v:339$457_Y
case 1'1
assign $0$formal$boneless.v:340$85_CHECK[0:0]$258 $logic_not$boneless.v:340$458_Y
assign $0$formal$boneless.v:340$85_EN[0:0]$259 1'1
assign $0$formal$boneless.v:341$86_CHECK[0:0]$260 $eq$boneless.v:341$459_Y
assign $0$formal$boneless.v:341$86_EN[0:0]$261 1'1
assign $0\fs_next_pc[15:0] $add$boneless.v:342$461_Y
assign $0\fs_jumped[0:0] 1'1
case
end
attribute \src "boneless.v:345"
switch \i_clsC
case 1'1
assign $0$formal$boneless.v:346$87_CHECK[0:0]$262 $logic_not$boneless.v:346$462_Y
assign $0$formal$boneless.v:346$87_EN[0:0]$263 1'1
assign $0$formal$boneless.v:347$88_CHECK[0:0]$264 $eq$boneless.v:347$463_Y
assign $0$formal$boneless.v:347$88_EN[0:0]$265 1'1
assign $0\fs_next_pc[15:0] $add$boneless.v:348$465_Y
attribute \src "boneless.v:349"
switch \i_cond
case 3'000
assign $0\fs_jumped[0:0] $eq$boneless.v:350$466_Y
case 3'001
assign $0\fs_jumped[0:0] $eq$boneless.v:351$467_Y
case 3'010
assign $0\fs_jumped[0:0] $eq$boneless.v:352$468_Y
case 3'011
assign $0\fs_jumped[0:0] $eq$boneless.v:353$469_Y
case 3'100
assign $0\fs_jumped[0:0] $eq$boneless.v:354$470_Y
case 3'101
assign $0\fs_jumped[0:0] $eq$boneless.v:355$473_Y
case 3'110
assign $0\fs_jumped[0:0] $eq$boneless.v:356$475_Y
case 3'111
assign $0\fs_jumped[0:0] $eq$boneless.v:357$478_Y
case
end
case
end
case
assign $1\stb.arith.res[16:0] \stb.arith.res
assign $1\stb.arith.c[0:0] \stb.arith.c
assign $1\stb.arith.v[0:0] \stb.arith.v
assign $1\stb.addi.tmp[15:0] \stb.addi.tmp
assign $1\stb.addi.res[16:0] \stb.addi.res
assign $1\stb.addi.v[0:0] \stb.addi.v
end
sync posedge \clk
update \fs_next_pc $0\fs_next_pc[15:0]
update \fs_jumped $0\fs_jumped[0:0]
update \fs_past_ext_r_en $0\fs_past_ext_r_en[0:0]
update \fs_past_ext_w_en $0\fs_past_ext_w_en[0:0]
update \fs_past_ext_adr $0\fs_past_ext_adr[0:0]
update \stb.arith.res $0\stb.arith.res[16:0]
update \stb.arith.c $0\stb.arith.c[0:0]
update \stb.arith.v $0\stb.arith.v[0:0]
update $past$boneless.v:265$1$0 $0$past$boneless.v:265$1$0[15:0]$105
update $past$boneless.v:266$2$0 $0$past$boneless.v:266$2$0[3:0]$106
update $past$boneless.v:272$3$0 $0$past$boneless.v:272$3$0[3:0]$107
update $past$boneless.v:279$4$0 $0$past$boneless.v:279$4$0[3:0]$108
update $past$boneless.v:290$5$0 $0$past$boneless.v:290$5$0[3:0]$109
update $past$boneless.v:301$6$0 $0$past$boneless.v:301$6$0[3:0]$110
update \stb.addi.tmp $0\stb.addi.tmp[15:0]
update \stb.addi.res $0\stb.addi.res[16:0]
update \stb.addi.v $0\stb.addi.v[0:0]
update $past$boneless.v:323$7$0 $0$past$boneless.v:323$7$0[3:0]$111
update $past$boneless.v:329$8$0 $0$past$boneless.v:329$8$0[3:0]$112
update $past$boneless.v:335$9$0 $0$past$boneless.v:335$9$0[3:0]$113
update $past$boneless.v:341$10$0 $0$past$boneless.v:341$10$0[3:0]$114
update $past$boneless.v:347$11$0 $0$past$boneless.v:347$11$0[3:0]$115
update $formal$boneless.v:161$14_CHECK $0$formal$boneless.v:161$14_CHECK[0:0]$116
update $formal$boneless.v:161$14_EN $0$formal$boneless.v:161$14_EN[0:0]$117
update $formal$boneless.v:169$15_CHECK $0$formal$boneless.v:169$15_CHECK[0:0]$118
update $formal$boneless.v:169$15_EN $0$formal$boneless.v:169$15_EN[0:0]$119
update $formal$boneless.v:173$16_CHECK $0$formal$boneless.v:173$16_CHECK[0:0]$120
update $formal$boneless.v:173$16_EN $0$formal$boneless.v:173$16_EN[0:0]$121
update $formal$boneless.v:179$17_CHECK $0$formal$boneless.v:179$17_CHECK[0:0]$122
update $formal$boneless.v:179$17_EN $0$formal$boneless.v:179$17_EN[0:0]$123
update $formal$boneless.v:184$18_CHECK $0$formal$boneless.v:184$18_CHECK[0:0]$124
update $formal$boneless.v:184$18_EN $0$formal$boneless.v:184$18_EN[0:0]$125
update $formal$boneless.v:185$19_CHECK $0$formal$boneless.v:185$19_CHECK[0:0]$126
update $formal$boneless.v:185$19_EN $0$formal$boneless.v:185$19_EN[0:0]$127
update $formal$boneless.v:188$20_CHECK $0$formal$boneless.v:188$20_CHECK[0:0]$128
update $formal$boneless.v:188$20_EN $0$formal$boneless.v:188$20_EN[0:0]$129
update $formal$boneless.v:190$21_CHECK $0$formal$boneless.v:190$21_CHECK[0:0]$130
update $formal$boneless.v:190$21_EN $0$formal$boneless.v:190$21_EN[0:0]$131
update $formal$boneless.v:192$22_CHECK $0$formal$boneless.v:192$22_CHECK[0:0]$132
update $formal$boneless.v:192$22_EN $0$formal$boneless.v:192$22_EN[0:0]$133
update $formal$boneless.v:194$23_CHECK $0$formal$boneless.v:194$23_CHECK[0:0]$134
update $formal$boneless.v:194$23_EN $0$formal$boneless.v:194$23_EN[0:0]$135
update $formal$boneless.v:195$24_CHECK $0$formal$boneless.v:195$24_CHECK[0:0]$136
update $formal$boneless.v:195$24_EN $0$formal$boneless.v:195$24_EN[0:0]$137
update $formal$boneless.v:227$25_CHECK $0$formal$boneless.v:227$25_CHECK[0:0]$138
update $formal$boneless.v:227$25_EN $0$formal$boneless.v:227$25_EN[0:0]$139
update $formal$boneless.v:229$26_CHECK $0$formal$boneless.v:229$26_CHECK[0:0]$140
update $formal$boneless.v:229$26_EN $0$formal$boneless.v:229$26_EN[0:0]$141
update $formal$boneless.v:230$27_CHECK $0$formal$boneless.v:230$27_CHECK[0:0]$142
update $formal$boneless.v:230$27_EN $0$formal$boneless.v:230$27_EN[0:0]$143
update $formal$boneless.v:231$28_CHECK $0$formal$boneless.v:231$28_CHECK[0:0]$144
update $formal$boneless.v:231$28_EN $0$formal$boneless.v:231$28_EN[0:0]$145
update $formal$boneless.v:233$29_CHECK $0$formal$boneless.v:233$29_CHECK[0:0]$146
update $formal$boneless.v:233$29_EN $0$formal$boneless.v:233$29_EN[0:0]$147
update $formal$boneless.v:234$30_CHECK $0$formal$boneless.v:234$30_CHECK[0:0]$148
update $formal$boneless.v:234$30_EN $0$formal$boneless.v:234$30_EN[0:0]$149
update $formal$boneless.v:235$31_CHECK $0$formal$boneless.v:235$31_CHECK[0:0]$150
update $formal$boneless.v:235$31_EN $0$formal$boneless.v:235$31_EN[0:0]$151
update $formal$boneless.v:236$32_CHECK $0$formal$boneless.v:236$32_CHECK[0:0]$152
update $formal$boneless.v:236$32_EN $0$formal$boneless.v:236$32_EN[0:0]$153
update $formal$boneless.v:242$33_CHECK $0$formal$boneless.v:242$33_CHECK[0:0]$154
update $formal$boneless.v:242$33_EN $0$formal$boneless.v:242$33_EN[0:0]$155
update $formal$boneless.v:243$34_CHECK $0$formal$boneless.v:243$34_CHECK[0:0]$156
update $formal$boneless.v:243$34_EN $0$formal$boneless.v:243$34_EN[0:0]$157
update $formal$boneless.v:246$35_CHECK $0$formal$boneless.v:246$35_CHECK[0:0]$158
update $formal$boneless.v:246$35_EN $0$formal$boneless.v:246$35_EN[0:0]$159
update $formal$boneless.v:249$36_CHECK $0$formal$boneless.v:249$36_CHECK[0:0]$160
update $formal$boneless.v:249$36_EN $0$formal$boneless.v:249$36_EN[0:0]$161
update $formal$boneless.v:251$37_CHECK $0$formal$boneless.v:251$37_CHECK[0:0]$162
update $formal$boneless.v:251$37_EN $0$formal$boneless.v:251$37_EN[0:0]$163
update $formal$boneless.v:253$38_CHECK $0$formal$boneless.v:253$38_CHECK[0:0]$164
update $formal$boneless.v:253$38_EN $0$formal$boneless.v:253$38_EN[0:0]$165
update $formal$boneless.v:255$39_CHECK $0$formal$boneless.v:255$39_CHECK[0:0]$166
update $formal$boneless.v:255$39_EN $0$formal$boneless.v:255$39_EN[0:0]$167
update $formal$boneless.v:256$40_CHECK $0$formal$boneless.v:256$40_CHECK[0:0]$168
update $formal$boneless.v:256$40_EN $0$formal$boneless.v:256$40_EN[0:0]$169
update $formal$boneless.v:261$41_CHECK $0$formal$boneless.v:261$41_CHECK[0:0]$170
update $formal$boneless.v:261$41_EN $0$formal$boneless.v:261$41_EN[0:0]$171
update $formal$boneless.v:262$42_CHECK $0$formal$boneless.v:262$42_CHECK[0:0]$172
update $formal$boneless.v:262$42_EN $0$formal$boneless.v:262$42_EN[0:0]$173
update $formal$boneless.v:265$43_CHECK $0$formal$boneless.v:265$43_CHECK[0:0]$174
update $formal$boneless.v:265$43_EN $0$formal$boneless.v:265$43_EN[0:0]$175
update $formal$boneless.v:266$44_CHECK $0$formal$boneless.v:266$44_CHECK[0:0]$176
update $formal$boneless.v:266$44_EN $0$formal$boneless.v:266$44_EN[0:0]$177
update $formal$boneless.v:269$45_CHECK $0$formal$boneless.v:269$45_CHECK[0:0]$178
update $formal$boneless.v:269$45_EN $0$formal$boneless.v:269$45_EN[0:0]$179
update $formal$boneless.v:270$46_CHECK $0$formal$boneless.v:270$46_CHECK[0:0]$180
update $formal$boneless.v:270$46_EN $0$formal$boneless.v:270$46_EN[0:0]$181
update $formal$boneless.v:271$47_CHECK $0$formal$boneless.v:271$47_CHECK[0:0]$182
update $formal$boneless.v:271$47_EN $0$formal$boneless.v:271$47_EN[0:0]$183
update $formal$boneless.v:272$48_CHECK $0$formal$boneless.v:272$48_CHECK[0:0]$184
update $formal$boneless.v:272$48_EN $0$formal$boneless.v:272$48_EN[0:0]$185
update $formal$boneless.v:275$49_CHECK $0$formal$boneless.v:275$49_CHECK[0:0]$186
update $formal$boneless.v:275$49_EN $0$formal$boneless.v:275$49_EN[0:0]$187
update $formal$boneless.v:276$50_CHECK $0$formal$boneless.v:276$50_CHECK[0:0]$188
update $formal$boneless.v:276$50_EN $0$formal$boneless.v:276$50_EN[0:0]$189
update $formal$boneless.v:277$51_CHECK $0$formal$boneless.v:277$51_CHECK[0:0]$190
update $formal$boneless.v:277$51_EN $0$formal$boneless.v:277$51_EN[0:0]$191
update $formal$boneless.v:278$52_CHECK $0$formal$boneless.v:278$52_CHECK[0:0]$192
update $formal$boneless.v:278$52_EN $0$formal$boneless.v:278$52_EN[0:0]$193
update $formal$boneless.v:279$53_CHECK $0$formal$boneless.v:279$53_CHECK[0:0]$194
update $formal$boneless.v:279$53_EN $0$formal$boneless.v:279$53_EN[0:0]$195
update $formal$boneless.v:282$54_CHECK $0$formal$boneless.v:282$54_CHECK[0:0]$196
update $formal$boneless.v:282$54_EN $0$formal$boneless.v:282$54_EN[0:0]$197
update $formal$boneless.v:283$55_CHECK $0$formal$boneless.v:283$55_CHECK[0:0]$198
update $formal$boneless.v:283$55_EN $0$formal$boneless.v:283$55_EN[0:0]$199
update $formal$boneless.v:285$56_CHECK $0$formal$boneless.v:285$56_CHECK[0:0]$200
update $formal$boneless.v:285$56_EN $0$formal$boneless.v:285$56_EN[0:0]$201
update $formal$boneless.v:286$57_CHECK $0$formal$boneless.v:286$57_CHECK[0:0]$202
update $formal$boneless.v:286$57_EN $0$formal$boneless.v:286$57_EN[0:0]$203
update $formal$boneless.v:289$58_CHECK $0$formal$boneless.v:289$58_CHECK[0:0]$204
update $formal$boneless.v:289$58_EN $0$formal$boneless.v:289$58_EN[0:0]$205
update $formal$boneless.v:290$59_CHECK $0$formal$boneless.v:290$59_CHECK[0:0]$206
update $formal$boneless.v:290$59_EN $0$formal$boneless.v:290$59_EN[0:0]$207
update $formal$boneless.v:293$60_CHECK $0$formal$boneless.v:293$60_CHECK[0:0]$208
update $formal$boneless.v:293$60_EN $0$formal$boneless.v:293$60_EN[0:0]$209
update $formal$boneless.v:294$61_CHECK $0$formal$boneless.v:294$61_CHECK[0:0]$210
update $formal$boneless.v:294$61_EN $0$formal$boneless.v:294$61_EN[0:0]$211
update $formal$boneless.v:296$62_CHECK $0$formal$boneless.v:296$62_CHECK[0:0]$212
update $formal$boneless.v:296$62_EN $0$formal$boneless.v:296$62_EN[0:0]$213
update $formal$boneless.v:298$63_CHECK $0$formal$boneless.v:298$63_CHECK[0:0]$214
update $formal$boneless.v:298$63_EN $0$formal$boneless.v:298$63_EN[0:0]$215
update $formal$boneless.v:300$64_CHECK $0$formal$boneless.v:300$64_CHECK[0:0]$216
update $formal$boneless.v:300$64_EN $0$formal$boneless.v:300$64_EN[0:0]$217
update $formal$boneless.v:301$65_CHECK $0$formal$boneless.v:301$65_CHECK[0:0]$218
update $formal$boneless.v:301$65_EN $0$formal$boneless.v:301$65_EN[0:0]$219
update $formal$boneless.v:311$66_CHECK $0$formal$boneless.v:311$66_CHECK[0:0]$220
update $formal$boneless.v:311$66_EN $0$formal$boneless.v:311$66_EN[0:0]$221
update $formal$boneless.v:312$67_CHECK $0$formal$boneless.v:312$67_CHECK[0:0]$222
update $formal$boneless.v:312$67_EN $0$formal$boneless.v:312$67_EN[0:0]$223
update $formal$boneless.v:313$68_CHECK $0$formal$boneless.v:313$68_CHECK[0:0]$224
update $formal$boneless.v:313$68_EN $0$formal$boneless.v:313$68_EN[0:0]$225
update $formal$boneless.v:314$69_CHECK $0$formal$boneless.v:314$69_CHECK[0:0]$226
update $formal$boneless.v:314$69_EN $0$formal$boneless.v:314$69_EN[0:0]$227
update $formal$boneless.v:315$70_CHECK $0$formal$boneless.v:315$70_CHECK[0:0]$228
update $formal$boneless.v:315$70_EN $0$formal$boneless.v:315$70_EN[0:0]$229
update $formal$boneless.v:316$71_CHECK $0$formal$boneless.v:316$71_CHECK[0:0]$230
update $formal$boneless.v:316$71_EN $0$formal$boneless.v:316$71_EN[0:0]$231
update $formal$boneless.v:317$72_CHECK $0$formal$boneless.v:317$72_CHECK[0:0]$232
update $formal$boneless.v:317$72_EN $0$formal$boneless.v:317$72_EN[0:0]$233
update $formal$boneless.v:320$73_CHECK $0$formal$boneless.v:320$73_CHECK[0:0]$234
update $formal$boneless.v:320$73_EN $0$formal$boneless.v:320$73_EN[0:0]$235
update $formal$boneless.v:321$74_CHECK $0$formal$boneless.v:321$74_CHECK[0:0]$236
update $formal$boneless.v:321$74_EN $0$formal$boneless.v:321$74_EN[0:0]$237
update $formal$boneless.v:322$75_CHECK $0$formal$boneless.v:322$75_CHECK[0:0]$238
update $formal$boneless.v:322$75_EN $0$formal$boneless.v:322$75_EN[0:0]$239
update $formal$boneless.v:323$76_CHECK $0$formal$boneless.v:323$76_CHECK[0:0]$240
update $formal$boneless.v:323$76_EN $0$formal$boneless.v:323$76_EN[0:0]$241
update $formal$boneless.v:326$77_CHECK $0$formal$boneless.v:326$77_CHECK[0:0]$242
update $formal$boneless.v:326$77_EN $0$formal$boneless.v:326$77_EN[0:0]$243
update $formal$boneless.v:327$78_CHECK $0$formal$boneless.v:327$78_CHECK[0:0]$244
update $formal$boneless.v:327$78_EN $0$formal$boneless.v:327$78_EN[0:0]$245
update $formal$boneless.v:328$79_CHECK $0$formal$boneless.v:328$79_CHECK[0:0]$246
update $formal$boneless.v:328$79_EN $0$formal$boneless.v:328$79_EN[0:0]$247
update $formal$boneless.v:329$80_CHECK $0$formal$boneless.v:329$80_CHECK[0:0]$248
update $formal$boneless.v:329$80_EN $0$formal$boneless.v:329$80_EN[0:0]$249
update $formal$boneless.v:332$81_CHECK $0$formal$boneless.v:332$81_CHECK[0:0]$250
update $formal$boneless.v:332$81_EN $0$formal$boneless.v:332$81_EN[0:0]$251
update $formal$boneless.v:333$82_CHECK $0$formal$boneless.v:333$82_CHECK[0:0]$252
update $formal$boneless.v:333$82_EN $0$formal$boneless.v:333$82_EN[0:0]$253
update $formal$boneless.v:334$83_CHECK $0$formal$boneless.v:334$83_CHECK[0:0]$254
update $formal$boneless.v:334$83_EN $0$formal$boneless.v:334$83_EN[0:0]$255
update $formal$boneless.v:335$84_CHECK $0$formal$boneless.v:335$84_CHECK[0:0]$256
update $formal$boneless.v:335$84_EN $0$formal$boneless.v:335$84_EN[0:0]$257
update $formal$boneless.v:340$85_CHECK $0$formal$boneless.v:340$85_CHECK[0:0]$258
update $formal$boneless.v:340$85_EN $0$formal$boneless.v:340$85_EN[0:0]$259
update $formal$boneless.v:341$86_CHECK $0$formal$boneless.v:341$86_CHECK[0:0]$260
update $formal$boneless.v:341$86_EN $0$formal$boneless.v:341$86_EN[0:0]$261
update $formal$boneless.v:346$87_CHECK $0$formal$boneless.v:346$87_CHECK[0:0]$262
update $formal$boneless.v:346$87_EN $0$formal$boneless.v:346$87_EN[0:0]$263
update $formal$boneless.v:347$88_CHECK $0$formal$boneless.v:347$88_CHECK[0:0]$264
update $formal$boneless.v:347$88_EN $0$formal$boneless.v:347$88_EN[0:0]$265
end
attribute \src "boneless.v:161"
process $proc$boneless.v:161$562
assign { } { }
assign $0$formal$boneless.v:161$14_EN[0:0]$563 1'0
sync always
sync init
update $formal$boneless.v:161$14_EN $0$formal$boneless.v:161$14_EN[0:0]$563
end
attribute \src "boneless.v:169"
process $proc$boneless.v:169$564
assign { } { }
assign $0$formal$boneless.v:169$15_EN[0:0]$565 1'0
sync always
sync init
update $formal$boneless.v:169$15_EN $0$formal$boneless.v:169$15_EN[0:0]$565
end
attribute \src "boneless.v:173"
process $proc$boneless.v:173$566
assign { } { }
assign $0$formal$boneless.v:173$16_EN[0:0]$567 1'0
sync always
sync init
update $formal$boneless.v:173$16_EN $0$formal$boneless.v:173$16_EN[0:0]$567
end
attribute \src "boneless.v:179"
process $proc$boneless.v:179$568
assign { } { }
assign $0$formal$boneless.v:179$17_EN[0:0]$569 1'0
sync always
sync init
update $formal$boneless.v:179$17_EN $0$formal$boneless.v:179$17_EN[0:0]$569
end
attribute \src "boneless.v:184"
process $proc$boneless.v:184$570
assign { } { }
assign $0$formal$boneless.v:184$18_EN[0:0]$571 1'0
sync always
sync init
update $formal$boneless.v:184$18_EN $0$formal$boneless.v:184$18_EN[0:0]$571
end
attribute \src "boneless.v:185"
process $proc$boneless.v:185$572
assign { } { }
assign $0$formal$boneless.v:185$19_EN[0:0]$573 1'0
sync always
sync init
update $formal$boneless.v:185$19_EN $0$formal$boneless.v:185$19_EN[0:0]$573
end
attribute \src "boneless.v:188"
process $proc$boneless.v:188$574
assign { } { }
assign $0$formal$boneless.v:188$20_EN[0:0]$575 1'0
sync always
sync init
update $formal$boneless.v:188$20_EN $0$formal$boneless.v:188$20_EN[0:0]$575
end
attribute \src "boneless.v:190"
process $proc$boneless.v:190$576
assign { } { }
assign $0$formal$boneless.v:190$21_EN[0:0]$577 1'0
sync always
sync init
update $formal$boneless.v:190$21_EN $0$formal$boneless.v:190$21_EN[0:0]$577
end
attribute \src "boneless.v:192"
process $proc$boneless.v:192$578
assign { } { }
assign $0$formal$boneless.v:192$22_EN[0:0]$579 1'0
sync always
sync init
update $formal$boneless.v:192$22_EN $0$formal$boneless.v:192$22_EN[0:0]$579
end
attribute \src "boneless.v:194"
process $proc$boneless.v:194$580
assign { } { }
assign $0$formal$boneless.v:194$23_EN[0:0]$581 1'0
sync always
sync init
update $formal$boneless.v:194$23_EN $0$formal$boneless.v:194$23_EN[0:0]$581
end
attribute \src "boneless.v:195"
process $proc$boneless.v:195$582
assign { } { }
assign $0$formal$boneless.v:195$24_EN[0:0]$583 1'0
sync always
sync init
update $formal$boneless.v:195$24_EN $0$formal$boneless.v:195$24_EN[0:0]$583
end
attribute \src "boneless.v:227"
process $proc$boneless.v:227$584
assign { } { }
assign $0$formal$boneless.v:227$25_EN[0:0]$585 1'0
sync always
sync init
update $formal$boneless.v:227$25_EN $0$formal$boneless.v:227$25_EN[0:0]$585
end
attribute \src "boneless.v:229"
process $proc$boneless.v:229$586
assign { } { }
assign $0$formal$boneless.v:229$26_EN[0:0]$587 1'0
sync always
sync init
update $formal$boneless.v:229$26_EN $0$formal$boneless.v:229$26_EN[0:0]$587
end
attribute \src "boneless.v:230"
process $proc$boneless.v:230$588
assign { } { }
assign $0$formal$boneless.v:230$27_EN[0:0]$589 1'0
sync always
sync init
update $formal$boneless.v:230$27_EN $0$formal$boneless.v:230$27_EN[0:0]$589
end
attribute \src "boneless.v:231"
process $proc$boneless.v:231$590
assign { } { }
assign $0$formal$boneless.v:231$28_EN[0:0]$591 1'0
sync always
sync init
update $formal$boneless.v:231$28_EN $0$formal$boneless.v:231$28_EN[0:0]$591
end
attribute \src "boneless.v:233"
process $proc$boneless.v:233$592
assign { } { }
assign $0$formal$boneless.v:233$29_EN[0:0]$593 1'0
sync always
sync init
update $formal$boneless.v:233$29_EN $0$formal$boneless.v:233$29_EN[0:0]$593
end
attribute \src "boneless.v:234"
process $proc$boneless.v:234$594
assign { } { }
assign $0$formal$boneless.v:234$30_EN[0:0]$595 1'0
sync always
sync init
update $formal$boneless.v:234$30_EN $0$formal$boneless.v:234$30_EN[0:0]$595
end
attribute \src "boneless.v:235"
process $proc$boneless.v:235$596
assign { } { }
assign $0$formal$boneless.v:235$31_EN[0:0]$597 1'0
sync always
sync init
update $formal$boneless.v:235$31_EN $0$formal$boneless.v:235$31_EN[0:0]$597
end
attribute \src "boneless.v:236"
process $proc$boneless.v:236$598
assign { } { }
assign $0$formal$boneless.v:236$32_EN[0:0]$599 1'0
sync always
sync init
update $formal$boneless.v:236$32_EN $0$formal$boneless.v:236$32_EN[0:0]$599
end
attribute \src "boneless.v:24"
process $proc$boneless.v:24$94
assign $0\ext_r_data[15:0] \ext_r_data
assign { } { }
assign { } { }
assign { } { }
assign $0$memwr$\ext$boneless.v:26$13_ADDR[15:0]$95 16'xxxxxxxxxxxxxxxx
assign $0$memwr$\ext$boneless.v:26$13_DATA[15:0]$96 16'xxxxxxxxxxxxxxxx
assign $0$memwr$\ext$boneless.v:26$13_EN[15:0]$97 16'0000000000000000
attribute \src "boneless.v:25"
switch \ext_r_en
case 1'1
assign $0\ext_r_data[15:0] $memrd$\ext$boneless.v:25$98_DATA
case
end
attribute \src "boneless.v:26"
switch \ext_w_en
case 1'1
assign $0$memwr$\ext$boneless.v:26$13_ADDR[15:0]$95 \ext_addr
assign $0$memwr$\ext$boneless.v:26$13_DATA[15:0]$96 \ext_w_data
assign $0$memwr$\ext$boneless.v:26$13_EN[15:0]$97 16'1111111111111111
case
end
sync posedge \clk
update \ext_r_data $0\ext_r_data[15:0]
update $memwr$\ext$boneless.v:26$13_ADDR $0$memwr$\ext$boneless.v:26$13_ADDR[15:0]$95
update $memwr$\ext$boneless.v:26$13_DATA $0$memwr$\ext$boneless.v:26$13_DATA[15:0]$96
update $memwr$\ext$boneless.v:26$13_EN $0$memwr$\ext$boneless.v:26$13_EN[15:0]$97
end
attribute \src "boneless.v:242"
process $proc$boneless.v:242$600
assign { } { }
assign $0$formal$boneless.v:242$33_EN[0:0]$601 1'0
sync always
sync init
update $formal$boneless.v:242$33_EN $0$formal$boneless.v:242$33_EN[0:0]$601
end
attribute \src "boneless.v:243"
process $proc$boneless.v:243$602
assign { } { }
assign $0$formal$boneless.v:243$34_EN[0:0]$603 1'0
sync always
sync init
update $formal$boneless.v:243$34_EN $0$formal$boneless.v:243$34_EN[0:0]$603
end
attribute \src "boneless.v:246"
process $proc$boneless.v:246$604
assign { } { }
assign $0$formal$boneless.v:246$35_EN[0:0]$605 1'0
sync always
sync init
update $formal$boneless.v:246$35_EN $0$formal$boneless.v:246$35_EN[0:0]$605
end
attribute \src "boneless.v:249"
process $proc$boneless.v:249$606
assign { } { }
assign $0$formal$boneless.v:249$36_EN[0:0]$607 1'0
sync always
sync init
update $formal$boneless.v:249$36_EN $0$formal$boneless.v:249$36_EN[0:0]$607
end
attribute \src "boneless.v:251"
process $proc$boneless.v:251$608
assign { } { }
assign $0$formal$boneless.v:251$37_EN[0:0]$609 1'0
sync always
sync init
update $formal$boneless.v:251$37_EN $0$formal$boneless.v:251$37_EN[0:0]$609
end
attribute \src "boneless.v:253"
process $proc$boneless.v:253$610
assign { } { }
assign $0$formal$boneless.v:253$38_EN[0:0]$611 1'0
sync always
sync init
update $formal$boneless.v:253$38_EN $0$formal$boneless.v:253$38_EN[0:0]$611
end
attribute \src "boneless.v:255"
process $proc$boneless.v:255$612
assign { } { }
assign $0$formal$boneless.v:255$39_EN[0:0]$613 1'0
sync always
sync init
update $formal$boneless.v:255$39_EN $0$formal$boneless.v:255$39_EN[0:0]$613
end
attribute \src "boneless.v:256"
process $proc$boneless.v:256$614
assign { } { }
assign $0$formal$boneless.v:256$40_EN[0:0]$615 1'0
sync always
sync init
update $formal$boneless.v:256$40_EN $0$formal$boneless.v:256$40_EN[0:0]$615
end
attribute \src "boneless.v:261"
process $proc$boneless.v:261$616
assign { } { }
assign $0$formal$boneless.v:261$41_EN[0:0]$617 1'0
sync always
sync init
update $formal$boneless.v:261$41_EN $0$formal$boneless.v:261$41_EN[0:0]$617
end
attribute \src "boneless.v:262"
process $proc$boneless.v:262$618
assign { } { }
assign $0$formal$boneless.v:262$42_EN[0:0]$619 1'0
sync always
sync init
update $formal$boneless.v:262$42_EN $0$formal$boneless.v:262$42_EN[0:0]$619
end
attribute \src "boneless.v:265"
process $proc$boneless.v:265$620
assign { } { }
assign $0$formal$boneless.v:265$43_EN[0:0]$621 1'0
sync always
sync init
update $formal$boneless.v:265$43_EN $0$formal$boneless.v:265$43_EN[0:0]$621
end
attribute \src "boneless.v:266"
process $proc$boneless.v:266$622
assign { } { }
assign $0$formal$boneless.v:266$44_EN[0:0]$623 1'0
sync always
sync init
update $formal$boneless.v:266$44_EN $0$formal$boneless.v:266$44_EN[0:0]$623
end
attribute \src "boneless.v:269"
process $proc$boneless.v:269$624
assign { } { }
assign $0$formal$boneless.v:269$45_EN[0:0]$625 1'0
sync always
sync init
update $formal$boneless.v:269$45_EN $0$formal$boneless.v:269$45_EN[0:0]$625
end
attribute \src "boneless.v:270"
process $proc$boneless.v:270$626
assign { } { }
assign $0$formal$boneless.v:270$46_EN[0:0]$627 1'0
sync always
sync init
update $formal$boneless.v:270$46_EN $0$formal$boneless.v:270$46_EN[0:0]$627
end
attribute \src "boneless.v:271"
process $proc$boneless.v:271$628
assign { } { }
assign $0$formal$boneless.v:271$47_EN[0:0]$629 1'0
sync always
sync init
update $formal$boneless.v:271$47_EN $0$formal$boneless.v:271$47_EN[0:0]$629
end
attribute \src "boneless.v:272"
process $proc$boneless.v:272$630
assign { } { }
assign $0$formal$boneless.v:272$48_EN[0:0]$631 1'0
sync always
sync init
update $formal$boneless.v:272$48_EN $0$formal$boneless.v:272$48_EN[0:0]$631
end
attribute \src "boneless.v:275"
process $proc$boneless.v:275$632
assign { } { }
assign $0$formal$boneless.v:275$49_EN[0:0]$633 1'0
sync always
sync init
update $formal$boneless.v:275$49_EN $0$formal$boneless.v:275$49_EN[0:0]$633
end
attribute \src "boneless.v:276"
process $proc$boneless.v:276$634
assign { } { }
assign $0$formal$boneless.v:276$50_EN[0:0]$635 1'0
sync always
sync init
update $formal$boneless.v:276$50_EN $0$formal$boneless.v:276$50_EN[0:0]$635
end
attribute \src "boneless.v:277"
process $proc$boneless.v:277$636
assign { } { }
assign $0$formal$boneless.v:277$51_EN[0:0]$637 1'0
sync always
sync init
update $formal$boneless.v:277$51_EN $0$formal$boneless.v:277$51_EN[0:0]$637
end
attribute \src "boneless.v:278"
process $proc$boneless.v:278$638
assign { } { }
assign $0$formal$boneless.v:278$52_EN[0:0]$639 1'0
sync always
sync init
update $formal$boneless.v:278$52_EN $0$formal$boneless.v:278$52_EN[0:0]$639
end
attribute \src "boneless.v:279"
process $proc$boneless.v:279$640
assign { } { }
assign $0$formal$boneless.v:279$53_EN[0:0]$641 1'0
sync always
sync init
update $formal$boneless.v:279$53_EN $0$formal$boneless.v:279$53_EN[0:0]$641
end
attribute \src "boneless.v:282"
process $proc$boneless.v:282$642
assign { } { }
assign $0$formal$boneless.v:282$54_EN[0:0]$643 1'0
sync always
sync init
update $formal$boneless.v:282$54_EN $0$formal$boneless.v:282$54_EN[0:0]$643
end
attribute \src "boneless.v:283"
process $proc$boneless.v:283$644
assign { } { }
assign $0$formal$boneless.v:283$55_EN[0:0]$645 1'0
sync always
sync init
update $formal$boneless.v:283$55_EN $0$formal$boneless.v:283$55_EN[0:0]$645
end
attribute \src "boneless.v:285"
process $proc$boneless.v:285$646
assign { } { }
assign $0$formal$boneless.v:285$56_EN[0:0]$647 1'0
sync always
sync init
update $formal$boneless.v:285$56_EN $0$formal$boneless.v:285$56_EN[0:0]$647
end
attribute \src "boneless.v:286"
process $proc$boneless.v:286$648
assign { } { }
assign $0$formal$boneless.v:286$57_EN[0:0]$649 1'0
sync always
sync init
update $formal$boneless.v:286$57_EN $0$formal$boneless.v:286$57_EN[0:0]$649
end
attribute \src "boneless.v:289"
process $proc$boneless.v:289$650
assign { } { }
assign $0$formal$boneless.v:289$58_EN[0:0]$651 1'0
sync always
sync init
update $formal$boneless.v:289$58_EN $0$formal$boneless.v:289$58_EN[0:0]$651
end
attribute \src "boneless.v:290"
process $proc$boneless.v:290$652
assign { } { }
assign $0$formal$boneless.v:290$59_EN[0:0]$653 1'0
sync always
sync init
update $formal$boneless.v:290$59_EN $0$formal$boneless.v:290$59_EN[0:0]$653
end
attribute \src "boneless.v:293"
process $proc$boneless.v:293$654
assign { } { }
assign $0$formal$boneless.v:293$60_EN[0:0]$655 1'0
sync always
sync init
update $formal$boneless.v:293$60_EN $0$formal$boneless.v:293$60_EN[0:0]$655
end
attribute \src "boneless.v:294"
process $proc$boneless.v:294$656
assign { } { }
assign $0$formal$boneless.v:294$61_EN[0:0]$657 1'0
sync always
sync init
update $formal$boneless.v:294$61_EN $0$formal$boneless.v:294$61_EN[0:0]$657
end
attribute \src "boneless.v:296"
process $proc$boneless.v:296$658
assign { } { }
assign $0$formal$boneless.v:296$62_EN[0:0]$659 1'0
sync always
sync init
update $formal$boneless.v:296$62_EN $0$formal$boneless.v:296$62_EN[0:0]$659
end
attribute \src "boneless.v:298"
process $proc$boneless.v:298$660
assign { } { }
assign $0$formal$boneless.v:298$63_EN[0:0]$661 1'0
sync always
sync init
update $formal$boneless.v:298$63_EN $0$formal$boneless.v:298$63_EN[0:0]$661
end
attribute \src "boneless.v:300"
process $proc$boneless.v:300$662
assign { } { }
assign $0$formal$boneless.v:300$64_EN[0:0]$663 1'0
sync always
sync init
update $formal$boneless.v:300$64_EN $0$formal$boneless.v:300$64_EN[0:0]$663
end
attribute \src "boneless.v:301"
process $proc$boneless.v:301$664
assign { } { }
assign $0$formal$boneless.v:301$65_EN[0:0]$665 1'0
sync always
sync init
update $formal$boneless.v:301$65_EN $0$formal$boneless.v:301$65_EN[0:0]$665
end
attribute \src "boneless.v:311"
process $proc$boneless.v:311$666
assign { } { }
assign $0$formal$boneless.v:311$66_EN[0:0]$667 1'0
sync always
sync init
update $formal$boneless.v:311$66_EN $0$formal$boneless.v:311$66_EN[0:0]$667
end
attribute \src "boneless.v:312"
process $proc$boneless.v:312$668
assign { } { }
assign $0$formal$boneless.v:312$67_EN[0:0]$669 1'0
sync always
sync init
update $formal$boneless.v:312$67_EN $0$formal$boneless.v:312$67_EN[0:0]$669
end
attribute \src "boneless.v:313"
process $proc$boneless.v:313$670
assign { } { }
assign $0$formal$boneless.v:313$68_EN[0:0]$671 1'0
sync always
sync init
update $formal$boneless.v:313$68_EN $0$formal$boneless.v:313$68_EN[0:0]$671
end
attribute \src "boneless.v:314"
process $proc$boneless.v:314$672
assign { } { }
assign $0$formal$boneless.v:314$69_EN[0:0]$673 1'0
sync always
sync init
update $formal$boneless.v:314$69_EN $0$formal$boneless.v:314$69_EN[0:0]$673
end
attribute \src "boneless.v:315"
process $proc$boneless.v:315$674
assign { } { }
assign $0$formal$boneless.v:315$70_EN[0:0]$675 1'0
sync always
sync init
update $formal$boneless.v:315$70_EN $0$formal$boneless.v:315$70_EN[0:0]$675
end
attribute \src "boneless.v:316"
process $proc$boneless.v:316$676
assign { } { }
assign $0$formal$boneless.v:316$71_EN[0:0]$677 1'0
sync always
sync init
update $formal$boneless.v:316$71_EN $0$formal$boneless.v:316$71_EN[0:0]$677
end
attribute \src "boneless.v:317"
process $proc$boneless.v:317$678
assign { } { }
assign $0$formal$boneless.v:317$72_EN[0:0]$679 1'0
sync always
sync init
update $formal$boneless.v:317$72_EN $0$formal$boneless.v:317$72_EN[0:0]$679
end
attribute \src "boneless.v:320"
process $proc$boneless.v:320$680
assign { } { }
assign $0$formal$boneless.v:320$73_EN[0:0]$681 1'0
sync always
sync init
update $formal$boneless.v:320$73_EN $0$formal$boneless.v:320$73_EN[0:0]$681
end
attribute \src "boneless.v:321"
process $proc$boneless.v:321$682
assign { } { }
assign $0$formal$boneless.v:321$74_EN[0:0]$683 1'0
sync always
sync init
update $formal$boneless.v:321$74_EN $0$formal$boneless.v:321$74_EN[0:0]$683
end
attribute \src "boneless.v:322"
process $proc$boneless.v:322$684
assign { } { }
assign $0$formal$boneless.v:322$75_EN[0:0]$685 1'0
sync always
sync init
update $formal$boneless.v:322$75_EN $0$formal$boneless.v:322$75_EN[0:0]$685
end
attribute \src "boneless.v:323"
process $proc$boneless.v:323$686
assign { } { }
assign $0$formal$boneless.v:323$76_EN[0:0]$687 1'0
sync always
sync init
update $formal$boneless.v:323$76_EN $0$formal$boneless.v:323$76_EN[0:0]$687
end
attribute \src "boneless.v:326"
process $proc$boneless.v:326$688
assign { } { }
assign $0$formal$boneless.v:326$77_EN[0:0]$689 1'0
sync always
sync init
update $formal$boneless.v:326$77_EN $0$formal$boneless.v:326$77_EN[0:0]$689
end
attribute \src "boneless.v:327"
process $proc$boneless.v:327$690
assign { } { }
assign $0$formal$boneless.v:327$78_EN[0:0]$691 1'0
sync always
sync init
update $formal$boneless.v:327$78_EN $0$formal$boneless.v:327$78_EN[0:0]$691
end
attribute \src "boneless.v:328"
process $proc$boneless.v:328$692
assign { } { }
assign $0$formal$boneless.v:328$79_EN[0:0]$693 1'0
sync always
sync init
update $formal$boneless.v:328$79_EN $0$formal$boneless.v:328$79_EN[0:0]$693
end
attribute \src "boneless.v:329"
process $proc$boneless.v:329$694
assign { } { }
assign $0$formal$boneless.v:329$80_EN[0:0]$695 1'0
sync always
sync init
update $formal$boneless.v:329$80_EN $0$formal$boneless.v:329$80_EN[0:0]$695
end
attribute \src "boneless.v:332"
process $proc$boneless.v:332$696
assign { } { }
assign $0$formal$boneless.v:332$81_EN[0:0]$697 1'0
sync always
sync init
update $formal$boneless.v:332$81_EN $0$formal$boneless.v:332$81_EN[0:0]$697
end
attribute \src "boneless.v:333"
process $proc$boneless.v:333$698
assign { } { }
assign $0$formal$boneless.v:333$82_EN[0:0]$699 1'0
sync always
sync init
update $formal$boneless.v:333$82_EN $0$formal$boneless.v:333$82_EN[0:0]$699
end
attribute \src "boneless.v:334"
process $proc$boneless.v:334$700
assign { } { }
assign $0$formal$boneless.v:334$83_EN[0:0]$701 1'0
sync always
sync init
update $formal$boneless.v:334$83_EN $0$formal$boneless.v:334$83_EN[0:0]$701
end
attribute \src "boneless.v:335"
process $proc$boneless.v:335$702
assign { } { }
assign $0$formal$boneless.v:335$84_EN[0:0]$703 1'0
sync always
sync init
update $formal$boneless.v:335$84_EN $0$formal$boneless.v:335$84_EN[0:0]$703
end
attribute \src "boneless.v:340"
process $proc$boneless.v:340$704
assign { } { }
assign $0$formal$boneless.v:340$85_EN[0:0]$705 1'0
sync always
sync init
update $formal$boneless.v:340$85_EN $0$formal$boneless.v:340$85_EN[0:0]$705
end
attribute \src "boneless.v:341"
process $proc$boneless.v:341$706
assign { } { }
assign $0$formal$boneless.v:341$86_EN[0:0]$707 1'0
sync always
sync init
update $formal$boneless.v:341$86_EN $0$formal$boneless.v:341$86_EN[0:0]$707
end
attribute \src "boneless.v:346"
process $proc$boneless.v:346$708
assign { } { }
assign $0$formal$boneless.v:346$87_EN[0:0]$709 1'0
sync always
sync init
update $formal$boneless.v:346$87_EN $0$formal$boneless.v:346$87_EN[0:0]$709
end
attribute \src "boneless.v:347"
process $proc$boneless.v:347$710
assign { } { }
assign $0$formal$boneless.v:347$88_EN[0:0]$711 1'0
sync always
sync init
update $formal$boneless.v:347$88_EN $0$formal$boneless.v:347$88_EN[0:0]$711
end
attribute \src "boneless.v:44"
process $proc$boneless.v:44$557
assign { } { }
assign $0\r_win[12:0] 13'0000000000000
sync always
update \r_win $0\r_win[12:0]
sync init
end
connect { \fi_v \fi_c \fi_s \fi_z } \fi_flags
connect \i_regX \fi_insn [4:2]
connect \i_regY \fi_insn [7:5]
connect \i_regZ \fi_insn [10:8]
connect \i_imm5 \fi_insn [4:0]
connect \i_imm8 \fi_insn [7:0]
connect \i_imm11 \fi_insn [10:0]
connect \i_shift \fi_insn [4:1]
connect \i_code1 \fi_insn [11]
connect \i_code2 \fi_insn [12:11]
connect \i_code3 \fi_insn [13:11]
connect \i_code4 \fi_insn [14:11]
connect \i_code5 \fi_insn [15:11]
connect \i_type1 \fi_insn [0]
connect \i_type2 \fi_insn [1:0]
connect \i_flag \fi_insn [11]
connect \i_cond \fi_insn [14:12]
connect \i_clsA $eq$boneless.v:97$99_Y
connect \i_clsS $eq$boneless.v:98$100_Y
connect \i_clsM $eq$boneless.v:99$101_Y
connect \i_clsI $eq$boneless.v:100$102_Y
connect \i_clsC $eq$boneless.v:101$103_Y
connect \a_regX { \r_win \i_regX }
connect \a_regY { \r_win \i_regY }
connect \a_regZ { \r_win \i_regZ }
end
`define sign(x) ($signed(x) < 0)
module boneless_formal(
input clk,
);
reg [15:0] mem [65535:0];
wire [15:0] mem_r_addr;
reg [15:0] mem_r_data;
wire mem_r_en;
wire [15:0] mem_w_addr;
wire [15:0] mem_w_data;
wire mem_w_en;
always @(posedge clk) begin
if (mem_r_en) mem_r_data <= mem[mem_r_addr];
if (mem_w_en) mem[mem_w_addr] <= mem_w_data;
end
reg [15:0] ext [65535:0];
wire [15:0] ext_addr;
reg [15:0] ext_r_data;
wire ext_r_en;
wire [15:0] ext_w_data;
wire ext_w_en;
always @(posedge clk) begin
if (ext_r_en) ext_r_data <= ext[ext_addr];
if (ext_w_en) ext[ext_addr] <= ext_w_data;
end
wire fi_stb;
wire [15:0] fi_pc;
wire [3:0] fi_flags;
wire fi_z, fi_s, fi_c, fi_v;
wire [15:0] fi_insn;
wire [15:0] fi_mem_w_addr;
wire [15:0] fi_mem_w_data;
wire fi_mem_w_en;
wire [15:0] fi_ext_addr;
wire [15:0] fi_ext_r_data;
wire fi_ext_r_en;
wire [15:0] fi_ext_w_data;
wire fi_ext_w_en;
assign {fi_v, fi_c, fi_s, fi_z} = fi_flags;
reg [12:0] r_win = 0;
boneless cpu(
.rst(0),
.clk(clk),
.r_win(r_win),
.mem_r_addr(mem_r_addr),
.mem_r_data(mem_r_data),
.mem_r_en(mem_r_en),
.mem_w_addr(mem_w_addr),
.mem_w_data(mem_w_data),
.mem_w_en(mem_w_en),
.ext_addr(ext_addr),
.ext_r_data(ext_r_data),
.ext_r_en(ext_r_en),
.ext_w_data(ext_w_data),
.ext_w_en(ext_w_en),
.fi_stb(fi_stb),
.fi_pc(fi_pc),
.fi_flags(fi_flags),
.fi_insn(fi_insn),
.fi_mem_w_addr(fi_mem_w_addr),
.fi_mem_w_data(fi_mem_w_data),
.fi_mem_w_en(fi_mem_w_en),
.fi_ext_addr(fi_ext_addr),
.fi_ext_r_data(fi_ext_r_data),
.fi_ext_r_en(fi_ext_r_en),
.fi_ext_w_data(fi_ext_w_data),
.fi_ext_w_en(fi_ext_w_en),
);
wire [2:0] i_regX = fi_insn[4:2];
wire [2:0] i_regY = fi_insn[7:5];
wire [2:0] i_regZ = fi_insn[10:8];
wire [4:0] i_imm5 = fi_insn[4:0];
wire [7:0] i_imm8 = fi_insn[7:0];
wire [10:0] i_imm11 = fi_insn[10:0];
wire [3:0] i_shift = fi_insn[4:1];
wire [0:0] i_code1 = fi_insn[11];
wire [1:0] i_code2 = fi_insn[12:11];
wire [2:0] i_code3 = fi_insn[13:11];
wire [3:0] i_code4 = fi_insn[14:11];
wire [4:0] i_code5 = fi_insn[15:11];
wire [0:0] i_type1 = fi_insn[0];
wire [1:0] i_type2 = fi_insn[1:0];
wire i_flag = fi_insn[11];
wire [2:0] i_cond = fi_insn[14:12];
localparam OPCLASS_A = 4'b0000;
localparam OPCLASS_S = 4'b0001;
localparam OPCLASS_M = 3'b001;
localparam OPCLASS_I = 2'b01;
localparam OPCLASS_C = 1'b1;
wire i_clsA = (i_code5[4:1] == OPCLASS_A);
wire i_clsS = (i_code5[4:1] == OPCLASS_S);
wire i_clsM = (i_code5[4:2] == OPCLASS_M);
wire i_clsI = (i_code5[4:3] == OPCLASS_I);
wire i_clsC = (i_code5[4:4] == OPCLASS_C);
localparam OPCODE_LOGIC = 5'b00000;
localparam OPTYPE_AND = 2'b00;
localparam OPTYPE_OR = 2'b01;
localparam OPTYPE_XOR = 2'b10;
localparam OPCODE_ARITH = 5'b00001;
localparam OPTYPE_ADD = 2'b00;
localparam OPTYPE_SUB = 2'b01;
localparam OPTYPE_CMP = 2'b10;
localparam OPCODE_SHIFT_L = 5'b00010;
localparam OPTYPE_SLL = 1'b0;
localparam OPTYPE_ROT = 1'b1;
localparam OPCODE_SHIFT_R = 5'b00011;
localparam OPTYPE_SRL = 1'b0;
localparam OPTYPE_SRA = 1'b1;
localparam OPCODE_LD = 5'b00100;
localparam OPCODE_ST = 5'b00101;
localparam OPCODE_LDX = 5'b00110;
localparam OPCODE_STX = 5'b00111;
localparam OPCODE_MOVL = 5'b01000;
localparam OPCODE_MOVH = 5'b01001;
localparam OPCODE_MOVA = 5'b01010;
localparam OPCODE_ADDI = 5'b01011;
localparam OPCODE_LDI = 5'b01100;
localparam OPCODE_STI = 5'b01101;
localparam OPCODE_JAL = 5'b01110;
localparam OPCODE_JR = 5'b01111;
localparam COND_F_0 = 3'b000;
localparam COND_F_Z = 3'b001;
localparam COND_F_S = 3'b010;
localparam COND_F_C = 3'b011;
localparam COND_F_V = 3'b100;
localparam COND_F_NCoZ = 3'b101;
localparam COND_F_SxV = 3'b110;
localparam COND_F_SxVoZ = 3'b111;
localparam OPCODE_J = (OPCODE_F_0<<1)|0;
wire [15:0] a_regX = {r_win, i_regX};
wire [15:0] a_regY = {r_win, i_regY};
wire [15:0] a_regZ = {r_win, i_regZ};
reg [15:0] fs_next_pc;
reg fs_jumped = 0;
reg fs_past_ext_r_en = 0;
reg fs_past_ext_w_en = 0;
reg fs_past_ext_adr = 0;
always @(posedge clk) begin
// TODO: assert that no instruction takes more than <n> clock cycles
// TODO: below, instead of $past(fi_flags), what should be used is something like
// $prev(fi_stb, fi_flags).
if (fi_ext_r_en || fi_ext_w_en) begin
assert (!fs_past_ext_r_en && !fs_past_ext_w_en);
fs_past_ext_r_en <= fi_ext_r_en;
fs_past_ext_w_en <= fi_ext_w_en;
fs_past_ext_adr <= fi_ext_addr;
end
if (fi_stb) begin :stb
if (fi_ext_r_en || fs_past_ext_r_en) begin
assert (i_code5 == OPCODE_LDX);
fs_past_ext_r_en <= 0;
end
if (fi_ext_w_en || fs_past_ext_w_en) begin
assert (i_code5 == OPCODE_STX);
fs_past_ext_w_en <= 0;
end
if (fs_jumped) begin
fs_jumped <= 0;
assert (fi_pc == fs_next_pc);
end
if (i_code5 == OPCODE_LOGIC) begin
if (i_type2 != 2'b11) begin
assert (fi_mem_w_en);
assert (fi_mem_w_addr == a_regZ);
case (i_type2)
OPTYPE_AND:
assert (fi_mem_w_data == (mem[a_regY] & mem[a_regX]));
OPTYPE_OR:
assert (fi_mem_w_data == (mem[a_regY] | mem[a_regX]));
OPTYPE_XOR:
assert (fi_mem_w_data == (mem[a_regY] ^ mem[a_regX]));
endcase
assert (fi_z == (fi_mem_w_data == 0));
assert (fi_s == fi_mem_w_data[15]);
// fi_c is undefined
// fi_v is undefined
end else begin
// opcode=logic optype=11 is undefined
end
end
if (i_code5 == OPCODE_ARITH) begin :arith
reg [16:0] res;
reg c, v;
case (i_type2)
OPTYPE_ADD: begin
res = mem[a_regY] + mem[a_regX];
c = res[16];
v = (`sign(mem[a_regY]) == `sign(mem[a_regX])) &&
(`sign(mem[a_regY]) != res[15]);
end
OPTYPE_SUB: begin
res = mem[a_regY] - mem[a_regX];
c = ~res[16];
v = (`sign(mem[a_regY]) == !`sign(mem[a_regX])) &&
(`sign(mem[a_regY]) != res[15]);
end
OPTYPE_CMP: begin
res = mem[a_regY] - mem[a_regX];
c = ~res[16];
v = (`sign(mem[a_regY]) == !`sign(mem[a_regX])) &&
(`sign(mem[a_regY]) != res[15]);
end
endcase
if (i_type2 != 2'b11) begin
if (i_type2 == OPTYPE_CMP) begin
assert (!fi_mem_w_en);
end else begin
assert (fi_mem_w_en);
assert (fi_mem_w_addr == a_regZ);
assert (fi_mem_w_data == res[15:0]);
end
assert (fi_z == (res[15:0] == 0));
assert (fi_s == res[15]);
assert (fi_c == c);
assert (fi_v == v);
end else begin
// opcode=arith optype=11 is undefined
end
end
if (i_code5 == OPCODE_SHIFT_L || i_code5 == OPCODE_SHIFT_R) begin
assert (fi_mem_w_en);
assert (fi_mem_w_addr == a_regZ);
case ({ i_code5, i_type1 })
OPCODE_SHIFT_L, OPTYPE_SLL:
assert (fi_mem_w_data == (mem[a_regY] << i_shift));
OPCODE_SHIFT_L, OPTYPE_ROT:
assert (fi_mem_w_data == (mem[a_regY] << i_shift) |
(mem[a_regY] >> (16 - i_shift)));
OPCODE_SHIFT_R, OPTYPE_SRL:
assert (fi_mem_w_data == (mem[a_regY] >> i_shift));
OPCODE_SHIFT_R, OPTYPE_SRA:
assert (fi_mem_w_data == {$signed(mem[a_regY]) >>> i_shift});
endcase
assert (fi_z == (fi_mem_w_data == 0));
assert (fi_s == fi_mem_w_data[15]);
// fi_c is undefined
// fi_v is undefined
end
if (i_code5 == OPCODE_LD) begin
assert (fi_mem_w_en);
assert (fi_mem_w_addr == a_regZ);
// FIXME: $past is a workaround for a false logic loop detected by Yosys
// because of the way multiport memories are represented by $mem cells.
assert (fi_mem_w_data == mem[$signed($past(mem[a_regY])) + $signed(i_imm5)]);
assert (fi_flags == $past(fi_flags));
end
if (i_code5 == OPCODE_ST) begin
assert (fi_mem_w_en);
assert (fi_mem_w_addr == {$signed(mem[a_regY]) + $signed(i_imm5)});
assert (fi_mem_w_data == mem[a_regZ]);
assert (fi_flags == $past(fi_flags));
end
if (i_code5 == OPCODE_LDX) begin
assert (fi_mem_w_en);
assert (fi_ext_r_en || fs_past_ext_r_en);
assert (fi_mem_w_addr == a_regZ);
assert (fi_mem_w_data == ext[$signed(mem[a_regY]) + $signed(i_imm5)]);
assert (fi_flags == $past(fi_flags));
end
if (i_code5 == OPCODE_STX) begin
assert (!fi_mem_w_en);
assert (fi_ext_w_en || fs_past_ext_w_en);
if (fi_ext_w_en) begin
assert (fi_ext_addr == {$signed(mem[a_regY]) + $signed(i_imm5)});
assert (fi_ext_w_data == mem[a_regZ]);
end
if (fs_past_ext_w_en)
assert (ext[$signed(mem[a_regY]) + $signed(i_imm5)] == mem[a_regZ]);
assert (fi_flags == $past(fi_flags));
end
if (i_code5 == OPCODE_MOVL || i_code5 == OPCODE_MOVH || i_code5 == OPCODE_MOVA) begin
assert (fi_mem_w_en);
assert (fi_mem_w_addr == a_regZ);
if (i_code5 == OPCODE_MOVL)
assert (fi_mem_w_data == i_imm8);
if (i_code5 == OPCODE_MOVH)
assert (fi_mem_w_data == i_imm8 << 8);
if (i_code5 == OPCODE_MOVA)
assert (fi_mem_w_data == {$signed(fi_pc) + 16'sd1 + $signed(i_imm8)});
assert (fi_flags == $past(fi_flags));
end
if (i_code5 == OPCODE_ADDI) begin :addi
reg [15:0] tmp;
reg [16:0] res;
reg v;
tmp = $signed(i_imm8);
res = mem[a_regZ] + tmp;
v = (`sign(mem[a_regZ]) == tmp[15]) &&
(`sign(mem[a_regZ]) != res[15]);
assert (fi_mem_w_en);
assert (fi_mem_w_addr == a_regZ);
assert (fi_mem_w_data == res[15:0]);
assert (fi_z == (res[15:0] == 0));
assert (fi_s == res[15]);
assert (fi_c == res[16]);
assert (fi_v == v);
end
if (i_code5 == OPCODE_LDI) begin
assert (fi_mem_w_en);
assert (fi_mem_w_addr == a_regZ);
assert (fi_mem_w_data == mem[$signed(fi_pc) + 16'sd1 + $signed(i_imm8)]);
assert (fi_flags == $past(fi_flags));
end
if (i_code5 == OPCODE_STI) begin
assert (fi_mem_w_en);
assert (fi_mem_w_addr == {$signed(fi_pc) + 16'sd1 + $signed(i_imm8)});
assert (fi_mem_w_data == mem[a_regZ]);
assert (fi_flags == $past(fi_flags));
end
if (i_code5 == OPCODE_JAL) begin
assert (fi_mem_w_en);
assert (fi_mem_w_addr == a_regZ);
assert (fi_mem_w_data == {$signed(fi_pc) + 16'sd1});
assert (fi_flags == $past(fi_flags));
fs_next_pc <= $signed($signed(fi_pc) + 16'sd1 + $signed(i_imm8));
fs_jumped <= 1;
end
if (i_code5 == OPCODE_JR) begin
assert (!fi_mem_w_en);
assert (fi_flags == $past(fi_flags));
fs_next_pc <= $signed($signed(mem[a_regZ]) + $signed(i_imm8));
fs_jumped <= 1;
end
if (i_clsC) begin
assert (!fi_mem_w_en);
assert (fi_flags == $past(fi_flags));
fs_next_pc <= {$signed(fi_pc) + 16'sd1 + $signed(i_imm11)};
case (i_cond)
COND_F_0: fs_jumped <= i_flag == (0);
COND_F_Z: fs_jumped <= i_flag == (fi_z);
COND_F_S: fs_jumped <= i_flag == (fi_s);
COND_F_C: fs_jumped <= i_flag == (fi_c);
COND_F_V: fs_jumped <= i_flag == (fi_v);
COND_F_NCoZ: fs_jumped <= i_flag == (!fi_c | fi_z);
COND_F_SxV: fs_jumped <= i_flag == (fi_s ^ fi_v);
COND_F_SxVoZ: fs_jumped <= i_flag == ((fi_s ^ fi_v) | fi_z);
endcase
end
end
end
endmodule
read_verilog -formal boneless.v
write_ilang boneless.rtlil
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