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@cr1901
Created November 7, 2017 02:35
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IceStorm Improvements Test File
#!/usr/bin/env python3
from migen import *
from migen.build.platforms import icestick
from migen.build.generic_platform import *
from migen.genlib.io import DifferentialOutput
from migen.genlib.resetsync import AsyncResetSynchronizer
class Rot(Module):
def __init__(self):
self.clk_freq = 12000000
self.ready = Signal()
self.rot = Signal(4)
self.divider = Signal(max=self.clk_freq)
self.d1 = Signal()
self.d2 = Signal()
self.d3 = Signal()
self.d4 = Signal()
self.d5 = Signal()
self.dummy = Signal()
self.dummy.attr.add("keep")
###
self.comb += [j.eq(self.rot[i]) for i, j in enumerate([self.d1, self.d2, self.d3, self.d4])]
self.comb += [self.d5.eq(1)]
self.comb += [self.dummy.eq(1)]
self.sync += [
If(self.ready,
If(self.divider == int(self.clk_freq) - 1,
self.divider.eq(0),
self.rot.eq(Cat(self.rot[-1], self.rot[:-1]))
).Else(
self.divider.eq(self.divider + 1)
)
).Else(
self.ready.eq(1),
self.rot.eq(1),
self.divider.eq(0)
)
]
self.clock_domains.cd_sys = ClockDomain()
if __name__ == "__main__":
plat = icestick.Platform()
m = Rot()
plat.add_extension([("rst", 0, Pins("PMOD:0"), IOStandard("LVCMOS33"))])
m.comb += [plat.request("user_led").eq(m.d1)]
m.comb += [plat.request("user_led").eq(m.d2)]
m.comb += [plat.request("user_led").eq(m.d3)]
led4 = plat.request("user_led")
led5 = plat.request("user_led")
m.specials += [DifferentialOutput(m.d4, led4, led5)]
rst = plat.request("rst")
clk12 = plat.request("clk12")
m.specials += [AsyncResetSynchronizer(m.cd_sys, rst)]
# m.specials += [AsyncResetSynchronizer(ClockDomain("sys"), rst)]
m.comb += [m.cd_sys.clk.eq(clk12)]
plat.toolchain.pre_synthesis_commands.append("hierarchy -top top")
# plat.toolchain.synthesis_commands.append("synth_ice40 -blif {build_name}.blif")
plat.toolchain.post_synthesis_commands.append("show top")
plat.build(m, run=True, build_dir="rot", build_name="rot_migen")
plat.create_programmer().flash(0, "rot/rot_migen.bin")
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