- Declaring a clock domain:
self.clock_domains.cd_mycd = ClockDomain()
- Referencing a clock domain:
self.sync.mycd += []ClockSignal("mycd")
- Requesting an I/O signal:
platform.request("clk12")
If you declare a clock domain cd_mycd in a Module, references to mycd
in sync/ClockSignal statements in the current Module refer to the mycd
declared in the current Module.
If you didn't declare a clock domain cd_mycd in your current Module,
references to mycd reference whichever Module has declared a clock
domain called mycd, if the clock domain name mycd can be uniquely
resolved to said Module.
If a clock domain name mycd can't be resolved uniquely,
(i.e. two Modules that are the immediate submodules of another Module
declared mycd), the offending clock domains will be deterministically renamed
(see manual for rename algorithm). The renamed clock domains are considered
unique and distinct clock domains from each other and distinct from the clock
domain called mycd.
In this case, you must either declare mycd manually in the current module
("Local Clock Domains" section applies), declare mycd in a submodule at a depth where no
naming conflict occurs ("Global Clock Domains" section applies), or the Verilog
generator will create "mycd" for you (if create_clock_domains=True).
If create_clock_domains=False, all clocks that are referenced in sync or
ClockSignal statements, even the default sys clock domain, must be
manually declared.
If create_clock_domains=True, verilog.convert will
automatically add any clocks that were not declared in the input Module
(including constituent submodules) to the output Verilog port list.
For clock domains which were manually declared, verilog.convert will not
add such clk and rst signals to the output port list. It is up to the user
to remember to add these clock domain signals (ios parameter
to verilog.convert).
If using the migen.build classes, create_clock_domains=False
by necessity. However GenericPlatform.build will create a default sys clock
domain (and I/O signal via GenericPlatform.request) in the simple case where
the user has not declared any ClockDomains in the input Module and
its corresponding submodules. In all other cases, the user must route clock
and reset signals manually to the platform's I/O signals.