AVMM Register Map

avmm_regmap.v

`default_nettype none

// cclayton - simple/generic AVMM regmap

module avmm_regmap #(
    NUM_READ_ONLY_REG  = 10,
    NUM_READ_WRITE_REG = 10,
    DATA_WIDTH         = 32,
    ADDRESS_STEP       = 5
)(

	// clock and reset for component
	input  wire        clk,
	input  wire        reset,

	// avmm slave interface, sl
	input  wire          sl_read,
	input  wire          sl_write,
	input  wire  [4-1:0] sl_byteenable,
	input  wire [32-1:0] sl_address,
	input  wire [32-1:0] sl_writedata,
	output reg  [32-1:0] sl_readdata,
	output wire          sl_waitrequest,
	output reg           sl_readdatavalid,

    input wire  [NUM_READ_ONLY_REG*DATA_WIDTH-1:0] i_read_only,
    output reg [NUM_READ_WRITE_REG*DATA_WIDTH-1:0] o_read_write

);

integer i;
assign sl_waitrequest = 1'b0;

always @ (posedge clk) begin
    if(reset) begin

        sl_readdata <= 32'd0;
        sl_readdatavalid <= 1'd0;
        o_read_write <= 'd0;

    end else begin 
        sl_readdatavalid <= 1'b0;
        if(sl_write) begin
            for (i = 0; i < NUM_READ_WRITE_REG; i = i + 1) begin
                if (sl_address == i*ADDRESS_STEP) begin
                    o_read_write[i*DATA_WIDTH +: DATA_WIDTH] <= sl_writedata;
                end
            end
        end

        if(sl_read) begin
            sl_readdatavalid <= 1'b1;
            sl_readdata <= {DATA_WIDTH{1'b0}};
            for (i = 0; i < NUM_READ_WRITE_REG; i = i + 1) begin
                if (sl_address == i*ADDRESS_STEP) begin
                    sl_readdata <= o_read_write[i*DATA_WIDTH +: DATA_WIDTH];
                end
            end
            for (i = NUM_READ_WRITE_REG; i < NUM_READ_WRITE_REG + NUM_READ_ONLY_REG; i = i + 1) begin
                if (sl_address == i*ADDRESS_STEP) begin
                    sl_readdata <= i_read_only[(i-NUM_READ_WRITE_REG)*DATA_WIDTH +: DATA_WIDTH];
                end
            end
    
	    end
    end
end

endmodule

From here: https://www.youtube.com/watch?v=UHffcN5YVoI