PSHDL sim runner for lilHarv

runner.go

package main

// simulateC.c comes from api.pshdl.org
// http://api.pshdl.org/api/v0.1/workspace/3978D82198FB1F6B
// in this case

// #include "simulateC.h"
import "C"

import (
	"fmt"
	"os"
	"strconv"
	"time"
)

func printState() {
	fmt.Printf("\nInstruction:\t Addr[%03d]\tCode:[%05X]\n",
		C.de_tuhh_hbubert_lilHarv_system_cpu_InstrAddr,
		C.de_tuhh_hbubert_lilHarv_system_cpu_InstrIn)

	fmt.Printf("Registers:\tIn[%03d]  0[%03d]  1[%03d]  2[%03d]  3[%03d]\n",
		// fmt.Printf("Regs[In: %2X 0:%2X 1:%2X 2:%2X 3:%2X]\n",
		C.de_tuhh_hbubert_lilHarv_system_cpu_regIn,
		C.de_tuhh_hbubert_lilHarv_system_cpu_reg0,
		C.de_tuhh_hbubert_lilHarv_system_cpu_reg1,
		C.de_tuhh_hbubert_lilHarv_system_cpu_reg2,
		C.de_tuhh_hbubert_lilHarv_system_cpu_reg3)

	fmt.Printf("Ram\t[")
	for _, v := range C.de_tuhh_hbubert_lilHarv_system_blockRam_memory {
		fmt.Printf("%d ", v)
	}
	fmt.Printf("]\n")

}

func main() {
	start := time.Now()

	cycles := 25
	if len(os.Args) == 1 {
		fmt.Fprintf(os.Stderr, "usage: %s <#cycles>\nusing default: %d\n\n", os.Args[0], cycles)
	} else {
		cycles, _ = strconv.Atoi(os.Args[1])
	}

	// reset
	C.run()
	C.de_tuhh_hbubert_lilHarv_system_clk = 1
	C.de_tuhh_hbubert_lilHarv_system_rst = 1
	C.run()

	afterReset := time.Now()
	fmt.Printf("Reset took:%v\n", afterReset.Sub(start))

	printState()
	C.de_tuhh_hbubert_lilHarv_system_rst = 0

	post := time.Now()
	pre := afterReset
	for cycles > 0 {

		// eval one cycle
		C.de_tuhh_hbubert_lilHarv_system_clk = 0
		C.run()
		C.de_tuhh_hbubert_lilHarv_system_clk = 1
		C.run()

		//clear screen
		// printf("\033[H\033[J");

		printState()
		// getchar();

		fmt.Printf("delta\t[%v]\n", post.Sub(pre))
		pre, post = post, time.Now()
		cycles -= 1
	}

	done := time.Now()
	fmt.Printf("\n\nDone. Simulation took:%v\n", done.Sub(start))
}