Configuring stm32f7 for 216MHz using svd2rust api

system.rs

///This configures the clock for full 216mHz performace. Copied from SystemClock_Config() in ST hal examples
  fn configure_clock(&self, rcc: &RCC, pwr: &PWR, flash: &FLASH) {
    /* Enable HSE Oscillator and activate PLL with HSE as source */
    //Enable the HSE
    rcc.cr.modify(|_, w| w.hseon().enabled());

    //Wait till HSE is ready (should add a timeout comparing to HSE_STARTUP_TIMEOUT
    //hprintln!("Waiting for HSE to be ready");
    wait_until_true(&|| rcc.cr.read().hserdy().bit_is_set());
    //hprintln!("HSE is ready");

    //Disable the main PLL before configuring it
    rcc.cr.modify(|_, w| w.pllon().disabled());
    //Wait till PLL is disabled (should add a timout comparing to PLL_STARTUP_TIMEOUT)
    //hprintln!("Waiting for PLL to be disabled");
    wait_until_true(&|| rcc.cr.read().pllrdy().bit_is_clear());
    //hprintln!("PLL is disabled");

    //Configure the PLL for 216mHz (25mHz HSE / 25 = 1 * 432 = 432 / 2 = 216. PllQ gives 216 / 9 = 24mHz for USB, SD card and RNG clocks
    rcc.pllcfgr.write(|w| w.pllm().bits(25)
                           .pllp().div2()
                           .plln().bits(432)
                           .pllq().bits(9)
                           .pllsrc().hse());


    //Enable the pll
    rcc.cr.modify(|_, w| w.pllon().enabled());
    //Wait till PLL is enabled (should add a timeout comparing to PLL_STARTUP_TIMEOUT)
    //hprintln!("Waiting for PLL to be ready");
    wait_until_true(&|| rcc.cr.read().pllrdy().bit_is_set());
    //hprintln!("PLL is ready");

    //Activate OverDrive to reach 216 Mhz Frequency
    //Enable power interface clock
    rcc.apb1enr.modify(|_, w| w.pwren().enabled());

    //Enable OverDrive
    pwr.cr1.modify(|_, w| w.oden().enabled());
    //Wait till OD is enabled (should add a timeout comparing to PWR_OVERDRIVE_TIMEOUT_VALUE)
    //hprintln!("Waiting for OD to be ready");
    wait_until_true(&|| pwr.csr1.read().odrdy().bit_is_set());
    //hprintln!("OD is ready");

    //Enable OverDrive switching
    pwr.cr1.modify(|_, w| w.odswen().enabled());
    //Wait till ODSW is enabled (should add a timeout comparing to PWR_OVERDRIVE_TIMEOUT_VALUE)
    //hprintln!("Waiting for ODSW to be ready");
    wait_until_true(&|| pwr.csr1.read().odswrdy().bit_is_set());
    //hprintln!("ODSW is ready");

    //Switch to the PLL as system clock source and configure the various clocks for this
    //Program the new number of wait states to the LATENCY bits in the FLASH_ACR register
    flash.acr.modify(|_, w| w.latency().bits(7));
    //Check this was applied correctly
    if flash.acr.read().latency().bits() != 7 {
      //hprintln!("Flash latency wasn't applied correctly");
    } else {
      //hprintln!("Flash latency was applied correctly");
    }

    //Change AHB prescaler to not divided (AHB = 216mHz)
    rcc.cfgr.modify(|_, w| w.hpre().not_divided());

    //Switch the system clock to PLL
    rcc.cfgr.modify(|_, w| w.sw().pll());

    //Wait till system clock switches (should add a timeout comparing to CLOCKSWITCH_TIMEOUT_VALUE)
    //hprintln!("Waiting for SWS to be PLL");
    wait_until_true(&|| rcc.cfgr.read().sws().is_pll());
    //hprintln!("SWS is PLL");

    //Set the APB low speed (APB1) prescaler
    rcc.cfgr.modify(|_, w| w.ppre1().div4());

    //Set the APB high speed (APB2) prescaler
    rcc.cfgr.modify(|_, w| w.ppre2().div2());
  }