cyring/gist:131f2c549fd6c8a8274e4e9e6c15015a

Created October 12, 2021 05:11

Star () You must be signed in to star a gist
Fork () You must be signed in to fork a gist

Learn more about clone URLs
Clone this repository at <script src="https://gist.github.com/cyring/131f2c549fd6c8a8274e4e9e6c15015a.js"></script>
Save cyring/131f2c549fd6c8a8274e4e9e6c15015a to your computer and use it in GitHub Desktop.

Download ZIP

AMD Ryzen Threadripper 3960X

Raw

gistfile1.txt

Courtesy @Chlorophytus

Author

cyring commented Jul 31, 2022 •

edited

Loading

Courtesy @Chlorophytus

System Information

Processor                       [AMD Ryzen Threadripper 3960X 24-Core Processor]
|- Architecture                                               [Zen2/Castle Peak]
|- Vendor ID                                                      [AuthenticAMD]
|- Firmware                                                         [ 36.34.0-2]
|- Microcode                                                        [0x08301055]
|- Signature                                                           [  8F_31]
|- Stepping                                                            [      0]
|- Online CPU                                                          [ 48/ 48]
|- Base Clock                                                          [100.000]
|- Frequency            (MHz)                      Ratio                        
                 Min   2200.04                    <  22 >                       
                 Max   3800.06                    <  38 >                       
|- Factory                                                             [100.000]
                       3800                       [  38 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT   3800.06                    <  38 >                       
|- Turbo Boost                                                         [ UNLOCK]
                 XFR   4600.07                    [  46 ]                       
                 CPB   4500.07                    [  45 ]                       
                  1C   2800.05                    <  28 >                       
                  2C   2200.04                    <  22 >                       
|- Uncore                                                              [   LOCK]
|- TDP                                                           Level [  0:0  ]
   |- Programmable                                                     [   LOCK]
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNNI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N] AVX-VNNI-VEX [N]    AVX-FP128 [N]   AVX-FP256 [Y] 
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [N]        UMIP [N] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Missing]
|- Fast-String Operation                                        ERMS   [Missing]
|- Fused Multiply Add                                     FMA | FMA4   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Missing]
|- Instruction INVPCID                                       INVPCID   [Missing]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Capable]
|- Memory Protection Extensions                                  MPX   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Missing]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Missing]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Missing]
   |- IBRS Always-On preferred by processor                            [Missing]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT SPEC_CTRL register                                 [Missing]
   |- SSBD not needed on this processor                                [Missing]
|- Architectural - Predictive Store Forwarding                  PSFD   [Missing]
                                                                                
Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [OFF]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   < ON>
|- Virtualization                                                    SVM   [ ON]
   |- I/O MMU                                                      AMD-V   [ ON]
   |- Version                                                     [         0.1]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [N/A]
|- Counters:          General                   Fixed                           
|           {  6,  6,  4 } x 48 bits            3 x 64 bits                     
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       <OFF>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       <OFF>
|- Package C6 State                                              PC6       < ON>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Collaborative Processor Performance Control                  CPPC       [N/A]
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x813 ]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     1     1     0     0     0     0     0     0              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Global Time Stamp Counter                                           [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax [ 49: 12 C]
|- CPPC Energy Preference                                       CPPC   [Missing]
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [  480 W]
   |- Minimum Power                                              Min   [  104 W]
   |- Maximum Power                                              Max   [  258 W]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <  280 W>
   |- Time Window                                                TW1   <   0 ns>
   |- Power Limit                                                PL2   < 1000 W>
   |- Time Window                                                TW2   <   0 ns>
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [    4 W]
|- Electrical Design Current                                     EDC   [  384 A]
|- Thermal Design Current                                        TDC   [   96 A]
|- Core Thermal Point                                                           
|- Package Thermal Point                                                        
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [  127 C]
   |- HTC Temperature Hysteresis                           Threshold   [    2 C]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

Topology

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID CCD CCX ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0   0  0   0  0      32  8        32  8       512  8 i  131072 16w 
001:  0    2   0  0   1  0      32  8        32  8       512  8 i  131072 16w 
002:  0    4   0  0   2  0      32  8        32  8       512  8 i  131072 16w 
003:  0    8   0  1   4  0      32  8        32  8       512  8 i  131072 16w 
004:  0   10   0  1   5  0      32  8        32  8       512  8 i  131072 16w 
005:  0   12   0  1   6  0      32  8        32  8       512  8 i  131072 16w 
006:  0   16   2  2   8  0      32  8        32  8       512  8 i  131072 16w 
007:  0   18   2  2   9  0      32  8        32  8       512  8 i  131072 16w 
008:  0   20   2  2  10  0      32  8        32  8       512  8 i  131072 16w 
009:  0   24   2  3  12  0      32  8        32  8       512  8 i  131072 16w 
010:  0   26   2  3  13  0      32  8        32  8       512  8 i  131072 16w 
011:  0   28   2  3  14  0      32  8        32  8       512  8 i  131072 16w 
012:  0   32   4  4  16  0      32  8        32  8       512  8 i  131072 16w 
013:  0   34   4  4  17  0      32  8        32  8       512  8 i  131072 16w 
014:  0   36   4  4  18  0      32  8        32  8       512  8 i  131072 16w 
015:  0   40   4  5  20  0      32  8        32  8       512  8 i  131072 16w 
016:  0   42   4  5  21  0      32  8        32  8       512  8 i  131072 16w 
017:  0   44   4  5  22  0      32  8        32  8       512  8 i  131072 16w 
018:  0   48   6  6  24  0      32  8        32  8       512  8 i  131072 16w 
019:  0   50   6  6  25  0      32  8        32  8       512  8 i  131072 16w 
020:  0   52   6  6  26  0      32  8        32  8       512  8 i  131072 16w 
021:  0   56   6  7  28  0      32  8        32  8       512  8 i  131072 16w 
022:  0   58   6  7  29  0      32  8        32  8       512  8 i  131072 16w 
023:  0   60   6  7  30  0      32  8        32  8       512  8 i  131072 16w 
024:  0    1   0  0   0  1      32  8        32  8       512  8 i  131072 16w 
025:  0    3   0  0   1  1      32  8        32  8       512  8 i  131072 16w 
026:  0    5   0  0   2  1      32  8        32  8       512  8 i  131072 16w 
027:  0    9   0  1   4  1      32  8        32  8       512  8 i  131072 16w 
028:  0   11   0  1   5  1      32  8        32  8       512  8 i  131072 16w 
029:  0   13   0  1   6  1      32  8        32  8       512  8 i  131072 16w 
030:  0   17   2  2   8  1      32  8        32  8       512  8 i  131072 16w 
031:  0   19   2  2   9  1      32  8        32  8       512  8 i  131072 16w 
032:  0   21   2  2  10  1      32  8        32  8       512  8 i  131072 16w 
033:  0   25   2  3  12  1      32  8        32  8       512  8 i  131072 16w 
034:  0   27   2  3  13  1      32  8        32  8       512  8 i  131072 16w 
035:  0   29   2  3  14  1      32  8        32  8       512  8 i  131072 16w 
036:  0   33   4  4  16  1      32  8        32  8       512  8 i  131072 16w 
037:  0   35   4  4  17  1      32  8        32  8       512  8 i  131072 16w 
038:  0   37   4  4  18  1      32  8        32  8       512  8 i  131072 16w 
039:  0   41   4  5  20  1      32  8        32  8       512  8 i  131072 16w 
040:  0   43   4  5  21  1      32  8        32  8       512  8 i  131072 16w 
041:  0   45   4  5  22  1      32  8        32  8       512  8 i  131072 16w 
042:  0   49   6  6  24  1      32  8        32  8       512  8 i  131072 16w 
043:  0   51   6  6  25  1      32  8        32  8       512  8 i  131072 16w 
044:  0   53   6  6  26  1      32  8        32  8       512  8 i  131072 16w 
045:  0   57   6  7  28  1      32  8        32  8       512  8 i  131072 16w 
046:  0   59   6  7  29  1      32  8        32  8       512  8 i  131072 16w 
047:  0   61   6  7  30  1      32  8        32  8       512  8 i  131072 16w

Memory Controller

                              Zen UMC  [1490]                              
Controller #0                                                Quad Channel  
 Bus Rate  1800 MHz       Bus Speed 1799 MHz           DDR4 Speed 3599 MT/s
                                                                           
 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   18   22   22   22   42   82    6    9   38    5   14   26    5    5 
  #1   18   22   22   22   42   82    6    9   38    5   14   26    5    5 
  #2   18   22   22   22   42   82    6    9   38    5   14   26    5    5 
  #3   18   22   22   22   42   82    6    9   38    5   14   26    5    5 
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   18   14    7    3    1    7    6    1    5    4    0    0    0    0 
  #1   18   14    8    3    1    7    6    1    5    4    0    0    0    0 
  #2   18   14    7    3    1    7    6    1    5    4    0    0    0    0 
  #3   18   14    8    3    1    7    6    1    5    4    0    0    0    0 
      REFI RFC1 RFC2 RFC4 RCPB RPPB  BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0 14029  312  192  132   0    0   OFF  ON  R1W1   0    0   1T    ON   0 
  #1 14029  312  192  132   0    0   OFF  ON  R1W1   0    0   1T    ON   0 
  #2 14029  312  192  132   0    0   OFF  ON  R1W1   0    0   1T    ON   0 
  #3 14029  312  192  132   0    0   OFF  ON  R1W1   0    0   1T    ON   0 
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0    8  18    27  27    24  255 0:F:0   13   2   13   26 1008   11    4 
  #1    8  18    27  27    24  255 0:F:0   13   2   13   26 1008   11    4 
  #2    8  18    27  27    24  255 0:F:0   13   2   13   26 1008   11    4 
  #3    8  18    27  27    24  255 0:F:0   13   2   13   26 1008   11    4 
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    16    2    131072      1024          32768                    
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    16    2    131072      1024          32768                    
 DIMM Geometry for channel #2                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    16    2    131072      1024          32768                    
 DIMM Geometry for channel #3                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    16    2    131072      1024          32768

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment