cyring/gist:155706cc6226a4447f8fde89c7d8748d

Created November 13, 2021 13:54

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Intel(R) Xeon(R) E-2246G CPU @ 3.60GHz

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gistfile1.txt

CoreFreq version 1.88.4

Author

cyring commented Nov 13, 2021

Processor

System information

Processor                               [Intel(R) Xeon(R) E-2246G CPU @ 3.60GHz]
|- Architecture                                                  [Coffee Lake/S]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x00000096]
|- Signature                                                           [  06_9E]
|- Stepping                                                            [     10]
|- Online CPU                                                          [ 12/ 12]
|- Base Clock                                                          [ 99.999]
|- Frequency            (MHz)                      Ratio                        
                 Min    799.99                    <   8 >                       
                 Max   3599.96                    <  36 >                       
|- Factory                                                             [100.000]
                       3600                       [  36 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT   4799.95                    <  48 >                       
|- Turbo Boost                                                         [ UNLOCK]
                  1C   4799.95                    <  48 >                       
                  2C   4699.95                    <  47 >                       
                  3C   4599.95                    <  46 >                       
                  4C   4399.96                    <  44 >                       
                  5C   4399.96                    <  44 >                       
                  6C   4399.96                    <  44 >                       
|- Uncore                                                              [ UNLOCK]
                 Min    799.99                    <   8 >                       
                 Max   4299.96                    <  43 >                       
|- TDP                                                           Level [  0:3  ]
   |- Programmable                                                     [ UNLOCK]
   |- Configuration                                                    [   LOCK]
   |- Turbo Activation                                                 [ UNLOCK]
             Nominal   3599.96                    [  36 ]                       
               Turbo      AUTO                    <   0 >                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNMI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N]  BMI1/BMI2 [Y/Y]         CLWB [N] CLFLUSH/O [Y/Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [N]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]          SGX [N]       RDPID [N] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast-String Operation                                Fast-Strings   [Capable]
|- Fused Multiply Add                                     FMA | FMA4   [Capable]
|- Hardware Lock Elision                                         HLE   [Capable]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Capable]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Missing]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Capable]
|- Safer Mode Extensions                                         SMX   [Capable]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Capable]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Missing]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Extended xAPIC Support                                     x2APIC   [ x2APIC]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [Capable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [Missing]
|- Architectural - Buffer Overwriting                       MD-CLEAR   [Missing]
|- Architectural - Rogue Data Cache Load                     RDCL_NO   [Missing]
|- Architectural - Enhanced IBRS                            IBRS_ALL   [Missing]
|- Architectural - Return Stack Buffer Alternate                RSBA   [Missing]
|- Architectural - Speculative Store Bypass                   SSB_NO   [Missing]
|- Architectural - Microarchitectural Data Sampling           MDS_NO   [Missing]
|- Architectural - TSX Asynchronous Abort                     TAA_NO   [Missing]
|- Architectural - Page Size Change MCE               PSCHANGE_MC_NO   [Missing]
|- Architectural - STLB QoS                                     STLB   [Missing]
|- Architectural - Functional Safety Island                     FuSa   [Missing]
|- Architectural - RSM in CPL0 only                              RSM   [Missing]
|- Architectural - Split Locked Access Exception                SPLA   [Missing]
|- Architectural - Snoop Filter QoS Mask                SNOOP_FILTER   [Missing]
                                                                                
Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Line Prefetcher                                        L2 HW CL   < ON>
|- System Management Mode                                       SMM-Dual   [ ON]
|- Hyper-Threading                                                   HTT   [ ON]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost                                                     TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   < ON>
|- Race To Halt Optimization                                         R2H   < ON>
|- Watchdog Timer                                                    TCO   < ON>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [ ON]
   |- Version                                                     [         1.0]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  4]
|- Counters:          General                   Fixed                           
|                     4 x 48 bits             3 x 48 bits                       
|- Enhanced Halt State                                           C1E       < ON>
|- C1 Auto Demotion                                              C1A       < ON>
|- C3 Auto Demotion                                              C3A       < ON>
|- C1 UnDemotion                                                 C1U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware-Controlled Performance States                        HWP       <OFF>
   |- Capabilities      (MHz)                      Ratio                        
              Lowest      AUTO                    [   0 ]                       
           Efficient      AUTO                    [   0 ]                       
          Guaranteed      AUTO                    [   0 ]                       
             Highest      AUTO                    [   0 ]                       
|- Hardware Duty Cycling                                         HDC       <OFF>
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [   LOCK]
   |- Lowest C-State                                           LIMIT   <     C0>
   |- I/O MWAIT Redirection                                  IOMWAIT   < Enable>
   |- Max C-State Inclusion                                    RANGE   <     C8>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x1814]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     1     2     4     1     1     1              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]
                                                                                
Power, Current & Thermal                                                        
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   <      6>
   |- Energy Policy                                          HWP EPP   [      0]
|- Junction Temperature                                        TjMax   [ 0:100C]
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Capable]
|- Package Thermal Management                                    PTM   [Capable]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [   80 W]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit (28 sec)                                       PL1   <   80 W>
   |- Power Limit (1 sec)                                        PL2   <  112 W>
|- Thermal Design Power                                         Core   <Disable>
   |- Power Limit                                                PL1   [Missing]
|- Thermal Design Power                                       Uncore   <Disable>
   |- Power Limit                                                PL1   [Missing]
|- Thermal Design Power                                         DRAM   <Disable>
   |- Power Limit                                                PL1   [Missing]
   |- Power Limit (1 sec)                                        PL2   [   27 W]
|- Thermal Design Power                                     Platform   < Enable>
   |- Power Limit (28 sec)                                       PL1   <   80 W>
   |- Power Limit (1 sec)                                        PL2   <  100 W>
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000061035]
   |- Window                                            second   [  0.000976562]

Topology

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID    ID     ID  L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0     0      0    32768  8     32768  8    262144  4  12582912 16 i
001:  0    2     1      0    32768  8     32768  8    262144  4  12582912 16 i
002:  0    4     2      0    32768  8     32768  8    262144  4  12582912 16 i
003:  0    6     3      0    32768  8     32768  8    262144  4  12582912 16 i
004:  0    8     4      0    32768  8     32768  8    262144  4  12582912 16 i
005:  0   10     5      0    32768  8     32768  8    262144  4  12582912 16 i
006:  0    1     0      1    32768  8     32768  8    262144  4  12582912 16 i
007:  0    3     1      1    32768  8     32768  8    262144  4  12582912 16 i
008:  0    5     2      1    32768  8     32768  8    262144  4  12582912 16 i
009:  0    7     3      1    32768  8     32768  8    262144  4  12582912 16 i
010:  0    9     4      1    32768  8     32768  8    262144  4  12582912 16 i
011:  0   11     5      1    32768  8     32768  8    262144  4  12582912 16 i

Package C-States

Technologies

HWP OFF

HWP ON

Race To Halt Optimization=OFF and HWP Target ratio=47

Memory Controller

                            Cannon Point  [3EC6]                           
Controller #0                                                Dual Channel  
 Bus Rate  8000 MT/s      Bus Speed 7999 MT/s          DRAM Speed 2667 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS  RRD  RFC   WR RTPr WTPr  FAW  B2B  CWL CMD  REFI
  #0    19   19   19   43    7  467   21   10   42   28    0   17  2T 10400
  #1    19   19   19   43    7  467   21   10   42   28    0   17  2T 10400
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     7    4    7    7         9    9    9   11        33   29    8    6
  #1     7    4    6    7        10   10   10   11        33   29    8    6
      sgWW dgWW drWW ddWW                                         CKE   ECC
  #0     7    4    9    7                                           4    3 
  #1     7    4   10    7                                           4    3 
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    16    2     65536      1024          16384                    
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1    16    2     65536      1024          16384

Conic algorithm

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