cyring/gist:339c1fddb47397d9c98b86523e3c7c97

Created September 25, 2021 12:35

Star () You must be signed in to star a gist
Fork () You must be signed in to fork a gist

Learn more about clone URLs
Clone this repository at <script src="https://gist.github.com/cyring/339c1fddb47397d9c98b86523e3c7c97.js"></script>
Save cyring/339c1fddb47397d9c98b86523e3c7c97 to your computer and use it in GitHub Desktop.

Download ZIP

Intel i7 920

Raw

gistfile1.txt

CoreFreq version 1.87.3

Author

cyring commented Sep 25, 2021

Performance

Turbo Single Core

Turbo all Cores

Performance Target Frequency

C-States

IPC

Energy Policy

Clock Modulation

Uncore

Memory Controller

Uncore Counter

System

Tasks

Tracking

Kernel

System Information

Processor                               [Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz]
|- Architecture                                             [Nehalem/Bloomfield]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x0000001d]
|- Signature                                                           [  06_1A]
|- Stepping                                                            [      5]
|- Online CPU                                                          [  8/  8]
|- Base Clock                                                          [133.500]
|- Frequency            (MHz)                      Ratio                        
                 Min   1602.00                    <  12 >                       
                 Max   2670.01                    <  20 >                       
|- Factory                                                             [133.333]
                       2670                       [  20 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT   1602.00                    <  12 >                       
|- Turbo Boost                                                         [   LOCK]
                  1C   2937.01                    <  22 >                       
                  2C   2803.51                    <  21 >                       
                  3C   2803.51                    <  21 >                       
                  4C   2803.51                    <  21 >                       
|- Uncore                                                              [   LOCK]
                 Min   3204.01                    [  24 ]                       
                 Max   3204.01                    [  24 ]                       
|- TDP                                                           Level [  0:0  ]
   |- Programmable                                                     [   LOCK]
   |- Configuration                                                    [   LOCK]
   |- Turbo Activation                                                 [   LOCK]
               Turbo      AUTO                    [   0 ]                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [N]          AES [N]  AVX/AVX2 [N/N] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNMI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N]  BMI1/BMI2 [N/N]         CLWB [N] CLFLUSH/O [Y/N] 
|- CLAC-STAC    [N]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [N]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [N]   PCLMULQDQ [N] 
|- POPCNT       [Y]       RDRAND [N]       RDSEED [N]      RDTSCP [Y] 
|- SEP          [Y]          SHA [N]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]          SGX [N]       RDPID [N] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast-String Operation                                Fast-Strings   [Missing]
|- Fused Multiply Add                                     FMA | FMA4   [Missing]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Missing]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Process Context Identifiers                                  PCID   [Missing]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Missing]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Missing]
|- Supervisor-Mode Execution Prevention                         SMEP   [Missing]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Missing]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Extended xAPIC Support                                     x2APIC   [Missing]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Missing]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [Capable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [Missing]
|- Architectural - Buffer Overwriting                       MD-CLEAR   [Missing]
|- Architectural - Rogue Data Cache Load                     RDCL_NO   [Missing]
|- Architectural - Enhanced IBRS                            IBRS_ALL   [Missing]
|- Architectural - Return Stack Buffer Alternate                RSBA   [Missing]
|- Architectural - Speculative Store Bypass                   SSB_NO   [Missing]
|- Architectural - Microarchitectural Data Sampling           MDS_NO   [Missing]
|- Architectural - TSX Asynchronous Abort                     TAA_NO   [Missing]
|- Architectural - Page Size Change MCE               PSCHANGE_MC_NO   [Missing]
|- Architectural - STLB QoS                                     STLB   [Missing]
|- Architectural - Functional Safety Island                     FuSa   [Missing]
|- Architectural - RSM in CPL0 only                              RSM   [Missing]
|- Architectural - Split Locked Access Exception                SPLA   [Missing]
|- Architectural - Snoop Filter QoS Mask                SNOOP_FILTER   [Missing]
                                                                                
Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Line Prefetcher                                        L2 HW CL   < ON>
|- System Management Mode                                       SMM-Dual   [ ON]
|- Hyper-Threading                                                   HTT   [ ON]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost                                                     TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   <OFF>
|- Race To Halt Optimization                                         R2H   <OFF>
|- Watchdog Timer                                                    TCO   < ON>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  3]
|- Counters:          General                   Fixed                           
|                     4 x 48 bits             3 x 48 bits                       
|- Enhanced Halt State                                           C1E       <OFF>
|- C1 Auto Demotion                                              C1A       <OFF>
|- C3 Auto Demotion                                              C3A       <OFF>
|- C1 UnDemotion                                                 C1U       <OFF>
|- C3 UnDemotion                                                 C3U       <OFF>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware-Controlled Performance States                        HWP       [OFF]
|- Hardware Duty Cycling                                         HDC       [OFF]
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [ UNLOCK]
   |- Lowest C-State                                           LIMIT   <     C6>
   |- I/O MWAIT Redirection                                  IOMWAIT   < Enable>
   |- Max C-State Inclusion                                    RANGE   <     C7>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x814 ]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     1     1     0     0     0     0              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]
                                                                                
Power, Current & Thermal                                                        
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [ 12.50%]
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   [      0]
   |- Energy Policy                                          HWP EPP   [      0]
|- Junction Temperature                                        TjMax   [ 0:100C]
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit (1 sec)                                        PL1   [  130 W]
   |- Power Limit                                                PL2   [Missing]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [Missing]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [Missing]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [Missing]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [Missing]
   |- Power Limit                                                PL2   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [  110 A]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [      Missing]
   |- Window                                            second   [  0.000976562]

Sensors

make HWM_CHIPSET=W83627

Idle

Stressed [`Conic Compute > Hyperboloid of two sheets`]

System Registers

CPU FLAG TF  IF IOPL NT  RF  VM  AC  VIF VIP ID                     
#0        0   0   0   0   0   0   0   0   0   0                     
#1        0   0   0   0   0   0   0   0   0   0                     
#2        0   0   0   0   0   0   0   0   0   0                     
#3        0   0   0   0   0   0   0   0   0   0                     
#4        0   0   0   0   0   0   0   0   0   0                     
#5        0   0   0   0   0   0   0   0   0   0                     
#6        0   0   0   0   0   0   0   0   0   0                     
#7        0   0   0   0   0   0   0   0   0   0                     
CR0: PE  MP  EM  TS  ET  NE  WP  AM  NW  CD  PG         CR3: PWT PCD
#0    1   1   0   0   1   1   1   1   0   0   1               0   0 
#1    1   1   0   0   1   1   1   1   0   0   1               0   0 
#2    1   1   0   0   1   1   1   1   0   0   1               0   0 
#3    1   1   0   0   1   1   1   1   0   0   1               0   0 
#4    1   1   0   0   1   1   1   1   0   0   1               0   0 
#5    1   1   0   0   1   1   1   1   0   0   1               0   0 
#6    1   1   0   0   1   1   1   1   0   0   1               0   0 
#7    1   1   0   0   1   1   1   1   0   0   1               0   0 
CR4: VME PVI TSD DE  PSE PAE MCE PGE PCE FX XMM UMIP 5LP VMX SMX FS 
#0    0   0   0   0   1   1   1   1   1   1   1   0   0   0   0   0 
#1    0   0   0   0   0   1   1   1   1   1   1   0   0   0   0   0 
#2    0   0   0   0   0   1   1   1   1   1   1   0   0   0   0   0 
#3    0   0   0   0   0   1   1   1   1   1   1   0   0   0   0   0 
#4    0   0   0   0   0   1   1   1   1   1   1   0   0   0   0   0 
#5    0   0   0   0   0   1   1   1   1   1   1   0   0   0   0   0 
#6    0   0   0   0   0   1   1   1   1   1   1   0   0   0   0   0 
#7    0   0   0   0   0   1   1   1   1   1   1   0   0   0   0   0 
CR4:PCID SAV  KL SME SMA PKE CET PKS                        CR8: TPL
#0    0   0   0   0   0   0   0   0                               1 
#1    0   0   0   0   0   0   0   0                               1 
#2    0   0   0   0   0   0   0   0                               1 
#3    0   0   0   0   0   0   0   0                               1 
#4    0   0   0   0   0   0   0   0                               1 
#5    0   0   0   0   0   0   0   0                               1 
#6    0   0   0   0   0   0   0   0                               1 
#7    0   0   0   0   0   0   0   0                               1 
EFCR    LCK VMX^SGX [SENTER] [ SGX ] LMC                            
#0        1   0   1   0   0   0   0   0                             
#1        1   0   1   0   0   0   0   0                             
#2        1   0   1   0   0   0   0   0                             
#3        1   0   1   0   0   0   0   0                             
#4        1   0   1   0   0   0   0   0                             
#5        1   0   1   0   0   0   0   0                             
#6        1   0   1   0   0   0   0   0                             
#7        1   0   1   0   0   0   0   0                             
EFER     SCE LME LMA NXE SVM LMS FFX TCE MCM WBI                    
#0        1   1   1   1   0   0   0   0   0   0                     
#1        1   1   1   1   0   0   0   0   0   0                     
#2        1   1   1   1   0   0   0   0   0   0                     
#3        1   1   1   1   0   0   0   0   0   0                     
#4        1   1   1   1   0   0   0   0   0   0                     
#5        1   1   1   1   0   0   0   0   0   0                     
#6        1   1   1   1   0   0   0   0   0   0                     
#7        1   1   1   1   0   0   0   0   0   0

System Interrupts

Dashboard

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment