Created
November 15, 2021 22:21
-
-
Save cyring/b46b2fed48d1ba72784ab6e0d91c3f89 to your computer and use it in GitHub Desktop.
AMD EPYC 7281 16-Core Processor
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
CoreFreq version 1.88.4 |
Memory Controller
Commit 08bd8c7da03103d86231186e567785ec2545f9ca
Zen UMC [1460]
Controller #0 Dual Channel
Bus Rate 1333 MT/s Bus Speed 1330 MHz DRAM Speed 2661 MHz
Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW
#0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
#1 21 19 19 19 43 62 4 7 16 4 10 20 4 4
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
#1 18 10 10 2 1 6 6 1 4 4 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 0 0 0 0 0 0 ON OFF R0W0 0 0 1T OFF 0
#1 10400 312 192 132 0 0 ON OFF R1W1 0 7 1T OFF 1
MRD:PDA MOD:PDA STAG PDM RDDATA PHY [WRD WRL RDL] WRMPR
#0 0 0 0 0 0 0:F:0 0 0 0 0 0
#1 8 16 24 24 7 0:P:1 16 2 13 24 24
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 1 131072 1024 16384
Controller #1 Dual Channel
Bus Rate 1333 MT/s Bus Speed 1330 MHz DRAM Speed 2661 MHz
Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW
#0 21 19 19 19 43 62 4 7 16 4 10 20 4 4
#1 21 19 19 19 43 62 4 7 16 4 10 20 4 4
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 18 10 9 2 1 6 6 1 4 4 0 0 0 0
#1 18 10 10 2 1 6 6 1 4 4 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 10400 312 192 132 0 0 ON OFF R1W1 0 7 1T OFF 1
#1 10400 312 192 132 0 0 ON OFF R1W1 0 7 1T OFF 1
MRD:PDA MOD:PDA STAG PDM RDDATA PHY [WRD WRL RDL] WRMPR
#0 8 16 24 24 7 0:P:1 16 2 13 24 24
#1 8 16 24 24 7 0:P:1 16 2 13 24 24
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 1 131072 1024 16384
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 1 131072 1024 16384
Controller #2 Dual Channel
Bus Rate 1333 MT/s Bus Speed 1330 MHz DRAM Speed 2661 MHz
Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW
#0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
#1 21 19 19 19 43 62 4 7 16 4 10 20 4 4
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
#1 18 10 10 2 1 6 6 1 4 4 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 0 0 0 0 0 0 ON OFF R0W0 0 0 1T OFF 0
#1 10400 312 192 132 0 0 ON OFF R1W1 0 7 1T OFF 1
MRD:PDA MOD:PDA STAG PDM RDDATA PHY [WRD WRL RDL] WRMPR
#0 0 0 0 0 0 0:F:0 0 0 0 0 0
#1 8 16 24 24 7 0:P:1 16 2 13 24 24
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 1 131072 1024 16384
Controller #3 Dual Channel
Bus Rate 1333 MT/s Bus Speed 1330 MHz DRAM Speed 2661 MHz
Cha CL RCDR RCDW RP RAS RC RRDS RRDL FAW WTRS WTRL WR clRR clWW
#0 21 19 19 19 43 62 4 7 16 4 10 20 4 4
#1 21 19 19 19 43 62 4 7 16 4 10 20 4 4
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 18 10 9 2 1 6 6 1 4 4 0 0 0 0
#1 18 10 10 2 1 6 6 1 4 4 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 10400 312 192 132 0 0 ON OFF R1W1 0 7 1T OFF 1
#1 10400 312 192 132 0 0 ON OFF R1W1 0 7 1T OFF 1
MRD:PDA MOD:PDA STAG PDM RDDATA PHY [WRD WRL RDL] WRMPR
#0 8 16 24 24 7 0:P:1 16 2 13 24 24
#1 8 16 24 24 7 0:P:1 16 2 13 24 24
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 1 131072 1024 16384
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 1 131072 1024 16384
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Processor
Frequencies
Topology
Idle
Cycles
Sensors
Loaded
Single Core