cyring/gist:bf56d2db34247fd249036d519b32de28

Created October 11, 2022 09:53

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Ryzen 5 6600H

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gistfile1.txt

AMD Ryzen 5 6600H with Radeon Graphics

Author

cyring commented Oct 11, 2022 •

edited

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Processor                               [AMD Ryzen 5 6600H with Radeon Graphics]
|- Architecture                                                [Zen3+ Rembrandt]
|- Vendor ID                                                      [AuthenticAMD]
|- Microcode                                                        [0x0a404101]
|- Signature                                                           [  AF_44]
|- Stepping                                                            [      1]
|- Online CPU                                                          [ 12/ 12]
|- Base Clock                                                          [ 99.812]
|- Frequency            (MHz)                      Ratio                        
                 Min   1596.97                    <  16 >                       
                 Max   3293.76                    <  33 >                       
|- Factory                                                             [100.000]
                       3300                       [  33 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT   3293.76                    <  33 >                       
   |- CPPC                                                                      
                 Min      AUTO                    <   0 >                       
                 Max      AUTO                    <   0 >                       
                 TGT      AUTO                    <   0 >                       
|- Turbo Boost                                                         [   LOCK]
                 XFR   4491.49                    [  45 ]                       
                 CPB   4491.49                    [  45 ]                       
                  1C   1796.60                    <  18 >                       
                  2C   1596.97                    <  16 >                       
|- Uncore                                                              [   LOCK]
                 CLK   1596.97                    [  16 ]                       
                 MEM   9581.84                    [  96 ]                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNNI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N] AVX-VNNI-VEX [N]    AVX-FP128 [N]   AVX-FP256 [Y] 
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y] 
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Advanced Virtual Interrupt Controller                        AVIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Clear Zero Instruction                                     CLZERO   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Capable]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Missing]
|- Fast-String Operation                                        ERMS   [Missing]
|- Fused Multiply Add                                     FMA | FMA4   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Missing]
|- Memory Protection Extensions                                  MPX   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Missing]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Capable]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- AVIC controller for x2APIC                                 x2AVIC   [Missing]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
|- No Branch Type Confusion                                   BTC_NO   [ Unable]
|- BTC on Non-Branch instruction                            BTC-NOBR   [Capable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
Security Features                                                               
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Capable]
|- SEV - Encrypted State                                      SEV-ES   [Capable]
|- SEV - Secure Nested Paging                                SEV-SNP   [Missing]
|- Guest Mode Execute Trap                                      GMET   [Capable]
|- Supervisor Shadow Stack                                       SSS   [Capable]
|- VM Permission Levels                                         VMPL   [Missing]
|- VMPL Supervisor Shadow Stack                             VMPL-SSS   [Missing]
|- Secure Multi-Key Memory Encryption                         SME-MK   [Missing]
                                                                                
Technologies                                                                    
|- Instruction Cache Unit                                                       
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [OFF]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   < ON>
|- Virtualization                                                    SVM   [ ON]
   |- I/O MMU                                                      AMD-V   [ ON]
   |- Version                                                     [         0.1]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  1]
|- Counters:          General                   Fixed                           
|           {  6,  6,  4 } x 48 bits            3 x 64 bits                     
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       < ON>
|- Package C6 State                                              PC6       < ON>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x413 ]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     1     1     0     0     0     0     0     0              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Global Time Stamp Counter                                           [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
|- Continuous Performance Control                               _CPC       [OFF]
|- Collaborative Processor Performance Control                  CPPC       < ON>
   |- Capabilities     Lowest      Efficient     Guaranteed        Highest      
   |- CPU #0     299.43 (  3)   698.68 (  7)  2096.03 ( 21)  3193.95 ( 32)      
   |- CPU #1     299.44 (  3)   698.68 (  7)  2096.05 ( 21)  3193.97 ( 32)      
   |- CPU #2     299.44 (  3)   698.68 (  7)  2096.05 ( 21)  3293.80 ( 33)      
   |- CPU #3     299.44 (  3)   698.68 (  7)  2096.05 ( 21)  3293.80 ( 33)      
   |- CPU #4     299.44 (  3)   698.69 (  7)  2096.06 ( 21)  3293.81 ( 33)      
   |- CPU #5     299.44 (  3)   698.68 (  7)  2096.05 ( 21)  3293.80 ( 33)      
   |- CPU #6     299.44 (  3)   698.68 (  7)  2096.05 ( 21)  2894.55 ( 29)      
   |- CPU #7     299.44 (  3)   698.68 (  7)  2096.05 ( 21)  2894.55 ( 29)      
   |- CPU #8     299.43 (  3)   698.68 (  7)  2096.03 ( 21)  3094.14 ( 31)      
   |- CPU #9     299.44 (  3)   698.68 (  7)  2096.05 ( 21)  3094.16 ( 31)      
   |- CPU #10    299.44 (  3)   698.69 (  7)  2096.06 ( 21)  2994.37 ( 30)      
   |- CPU #11    299.43 (  3)   698.67 (  7)  2096.00 ( 21)  2994.28 ( 30)      
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax [ 49:  0 C]
|- CPPC Energy Preference                                       CPPC   <      0>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
|- Package Thermal Point                                                        
   |- Thermal Monitor Trip                                     Limit   [  125 C]
   |- HTC Temperature Limit                                    Limit   [  127 C]
   |- HTC Temperature Hysteresis                           Threshold   [    2 C]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID CCD CCX ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0   0  0   0  0      32  8        32  8       512  8 i   16384 16w 
001:  0    1   0  0   0  1      32  8        32  8       512  8 i   16384 16w 
002:  0    2   0  0   1  0      32  8        32  8       512  8 i   16384 16w 
003:  0    3   0  0   1  1      32  8        32  8       512  8 i   16384 16w 
004:  0    4   0  0   2  0      32  8        32  8       512  8 i   16384 16w 
005:  0    5   0  0   2  1      32  8        32  8       512  8 i   16384 16w 
006:  0    6   0  0   3  0      32  8        32  8       512  8 i   16384 16w 
007:  0    7   0  0   3  1      32  8        32  8       512  8 i   16384 16w 
008:  0    8   0  1   4  0      32  8        32  8       512  8 i   16384 16w 
009:  0    9   0  1   4  1      32  8        32  8       512  8 i   16384 16w 
010:  0   10   0  1   5  0      32  8        32  8       512  8 i   16384 16w 
011:  0   11   0  1   5  1      32  8        32  8       512  8 i   16384 16w

CPU     IPS            IPC            CPI
000     0.000571/s     0.048242/c    20.728883/i
001     0.000045/s     0.135748/c     7.366570/i
002     0.000036/s     0.125712/c     7.954708/i
003     0.000047/s     0.130918/c     7.638395/i
004     0.000474/s     0.226883/c     4.407564/i
005     0.000032/s     0.140153/c     7.135035/i
006     0.000296/s     0.232916/c     4.293399/i
007     0.000030/s     0.121000/c     8.264441/i
008     0.000054/s     0.140083/c     7.138640/i
009     0.000028/s     0.110798/c     9.025423/i
010     0.000039/s     0.114210/c     8.755781/i
011     0.000079/s     0.147684/c     6.771216/i

CPU Freq(MHz) Ratio  Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)  Min TMP:TS  Max
000   15.91 ( 0.16)   0.48   1.16   0.00  98.88   0.00   0.00  0  /  0:0  /  0
001    0.43 ( 0.00)   0.01   0.03   0.00  99.97   0.00   0.00  0  /  0:0  /  0
002    0.38 ( 0.00)   0.01   0.03   0.00  99.97   0.00   0.00  0  /  0:0  /  0
003    0.37 ( 0.00)   0.01   0.03   0.00  99.97   0.00   0.00  0  /  0:0  /  0
004    2.18 ( 0.02)   0.07   0.16   0.00  99.84   0.00   0.00  38 / 38:700/ 38
005    0.31 ( 0.00)   0.01   0.02   0.00  99.98   0.00   0.00  0  /  0:0  /  0
006    0.43 ( 0.00)   0.01   0.03   0.00  99.97   0.00   0.00  0  /  0:0  /  0
007    0.37 ( 0.00)   0.01   0.03   0.00  99.97   0.00   0.00  0  /  0:0  /  0
008    0.41 ( 0.00)   0.01   0.03   0.00  99.97   0.00   0.00  0  /  0:0  /  0
009    0.36 ( 0.00)   0.01   0.03   0.00  99.98   0.00   0.00  0  /  0:0  /  0
010    2.15 ( 0.02)   0.07   0.15   0.00  99.85   0.00   0.00  0  /  0:0  /  0
011    0.39 ( 0.00)   0.01   0.03   0.00  99.97   0.00   0.00  0  /  0:0  /  0

    Averages:        Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)    TjMax:    Pkg:
                      0.06   0.14   0.00  99.86   0.00   0.00       0 C    38 C

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000    1.93     0  0.0000    0  000000000000000109    0.001663208   0.001663208
001    0.45     0  0.0000    0  000000000000000000    0.000000000   0.000000000
002    1.11     0  0.0000    0  000000000000000091    0.001388550   0.001388550
003    1.13     0  0.0000    0  000000000000000000    0.000000000   0.000000000
004    0.79     0  0.0000    0  000000000000000001    0.000015259   0.000015259
005    0.42     0  0.0000    0  000000000000000000    0.000000000   0.000000000
006    1.44    86  0.5375   38  000000000000000016    0.000244141   0.000244141
007    0.79     0  0.0000    0  000000000000000000    0.000000000   0.000000000
008    1.15     0  0.0000    0  000000000000000082    0.001251221   0.001251221
009    0.84     0  0.0000    0  000000000000000000    0.000000000   0.000000000
010    3.64     0  0.0000    0  000000000000000233    0.003555298   0.003555298
011    0.93     0  0.0000    0  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J):   3.265731812   0.008117676   0.000000000   0.000000000   0.000000000
Power(W) :   3.265731812   0.008117676   0.000000000   0.000000000   0.000000000

[ 0] LENOVO                                                                     
[ 1] JUCN38WW                                                                   
[ 2] 06/10/2022                                                                 
[ 3] LENOVO                                                                     
[ 4] 82RD                                                                       
[ 5] Legion 5 15ARH7H                                                           
[ 6] P---Y---                                                                   
[ 7] LENOVO_MT_82RD_BU_idea_FM_Legion 5 15ARH7H                                 
[ 8] Legion 5 15ARH7H                                                           
[ 9] LENOVO                                                                     
[10] LNVNB161216                                                                
[11]  NO DPK                                                                    
[12] P---Y---                                                                   
[13] Number Of Devices:2\Maximum Capacity:67108864 bytes                        
[14] P0 CHANNEL A DIMM 0\P0 CHANNEL A                                           
[15]                                                                            
[16]                                                                            
[17]                                                                            
[18] Micron Technology                                                          
[19]                                                                            
[20]                                                                            
[21]                                                                            
[22] MTC4C10163S1SC48BA1                                                        
[23]                                                                            
[24]                                                                            
[25]

Linux:                                                                          
|- Release                                                     [5.19.13-arch1-1]
|- Version              [#1 SMP PREEMPT_DYNAMIC Tue, 04 Oct 2022 14:36:58 +0000]
|- Machine                                                              [x86_64]
Memory:                                                                         
|- Total RAM                                                         15544704 KB
|- Shared RAM                                                            1836 KB
|- Free RAM                                                          14624760 KB
|- Buffer RAM                                                           35500 KB
|- Total High                                                               0 KB
|- Free High                                                                0 KB
Clock Source                                                  <    corefreq_tsc>
CPU-Freq driver                                               [  corefreqk-perf]
Governor                                                      [ corefreq-policy]
CPU-Idle driver                                               [  corefreqk-idle]
|- Idle Limit                                                 <              C2>
   |- State        POLL      C1      C2      C3      C4      C5      C6         
   |-           CPUIDLE  I/O-C1  I/O-C2  I/O-C3  I/O-C4  I/O-C5  I/O-C6         
   |- Power          -1       0       0       0       0       0       0         
   |- Latency         0       1      20      40      60      80     100         
   |- Residency       0       2      40      80     120     160     200

Author

cyring commented Oct 17, 2022 •

edited

Loading

UMC

SoC

(Work in progress)

`MSR_AMD_F17H_PMGT_MISC`

static void Call_SVI_RMB(const unsigned int plane0, const unsigned int plane1,
                        const unsigned long long factor)
{
        AMD_RMB_SVI SVI = {.value = 0};
        ZEN_PMGT_MISC PM = {.value = 0};
        UNUSED(factor);

        Core_AMD_SMN_Read(      SVI,
                                SMU_AMD_RMB_SVI(plane0),
                                PRIVATE(OF(Zen)).Device.DF );

        PUBLIC(RO(Proc))->PowerThermal.VID.CPU = SVI.SVI1;
/*
        Core_AMD_SMN_Read(      SVI,
                                SMU_AMD_RMB_SVI(plane1),
                                PRIVATE(OF(Zen)).Device.DF );
*/
        RDMSR(PM, MSR_AMD_F17H_PMGT_MISC);
        PUBLIC(RO(Proc))->PowerThermal.VID.SOC = PM.CurDFVid;
}

CPU @ `0x006f010` , SoC @ `0x006f018`

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