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cyring/gist:dc681daba303d76b8dc2d3da38fa33b6

Created January 3, 2024 09:37
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Cortex Registers
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cyring commented Jan 3, 2024 •
edited 

typedef struct
{
	struct CACHE_INFO
	{
		union CCSIDR
		{
			unsigned long long	value;
			struct
			{
				unsigned long long
				LineSz		:  3-0,
				Assoc		: 13-3,
				Set		: 28-13,
				WrAlloc 	: 29-28,
				RdAlloc 	: 30-29,
				WrBack		: 31-30,
				WrThrough	: 32-31,
				RES0		: 64-32;
			};
		} ccsid;
		union CLIDR
		{
			unsigned long long	value;
			struct
			{
				unsigned long long
				Ctype1		:  3-0,
				Ctype2		:  6-3,
				Ctype3		:  9-6,
				RES0		: 21-9,
				LoUIS		: 24-21,
				LoC		: 27-24,
				LoUU		: 30-27,
				ICB		: 33-30,
				RES1		: 64-33;
			};
		} clidr;
		unsigned int	Size;
	} Cache[CACHE_MAX_LEVEL];
} CACHE_TOPOLOGY;

typedef union
{
	unsigned long long	value;
	struct
	{
		unsigned long long
		InD		:  1-0,
		Level		:  4-1,
		RES0		: 32-4,
		RES1		: 64-32;
	};
} CSSELR;
void Cache_Topology(CORE_RO *Core)
{
	CSSELR cssel[CACHE_MAX_LEVEL] = {
		{ .InD = 1, .Level = 0 },	/*	L1I	*/
		{ .InD = 0, .Level = 0 },	/*	L1D	*/
		{ .InD = 0, .Level = 1 },	/*	L2	*/
		{ .InD = 0, .Level = 2 }	/*	L3	*/
	};
	unsigned int loop;
    for (loop = 0; loop < CACHE_MAX_LEVEL; loop++) {
	__asm__ volatile
	(
		"msr	csselr_el1,	%[cssel]"	"\n\t"
		"mrs	%[ccsid],	ccsidr_el1"	"\n\t"
		"mrs	%[clidr],	clidr_el1"	"\n\t"
		"isb"
		: [ccsid]	"=r" (Core->T.Cache[loop].ccsid),
		  [clidr]	"=r" (Core->T.Cache[loop].clidr)
		: [cssel]	"r"  (cssel[loop])
		: "memory"
	);
	printk("CPU[%u]\tCSSELR[%d:%d]=%llx\tCLIDR=%llx\n", Core->Bind,
		cssel[loop].Level, cssel[loop].InD,
		Core->T.Cache[loop].ccsid.value,
		Core->T.Cache[loop].clidr.value);
    }
}
CPU[0]  CSSELR[0:1]=200fe01a    CLIDR=c3000123
CPU[0]  CSSELR[0:0]=700fe01a    CLIDR=c3000123
CPU[0]  CSSELR[1:0]=703fe01a    CLIDR=c3000123
CPU[0]  CSSELR[2:0]=71ffe07a    CLIDR=c3000123
CPU[1]  CSSELR[0:1]=200fe01a    CLIDR=c3000123
CPU[1]  CSSELR[0:0]=700fe01a    CLIDR=c3000123
CPU[1]  CSSELR[1:0]=703fe01a    CLIDR=c3000123
CPU[1]  CSSELR[2:0]=71ffe07a    CLIDR=c3000123
CPU[2]  CSSELR[0:1]=200fe01a    CLIDR=c3000123
CPU[2]  CSSELR[0:0]=700fe01a    CLIDR=c3000123
CPU[2]  CSSELR[1:0]=703fe01a    CLIDR=c3000123
CPU[2]  CSSELR[2:0]=71ffe07a    CLIDR=c3000123
CPU[3]  CSSELR[0:1]=200fe01a    CLIDR=c3000123
CPU[3]  CSSELR[0:0]=700fe01a    CLIDR=c3000123
CPU[3]  CSSELR[1:0]=703fe01a    CLIDR=c3000123
CPU[3]  CSSELR[2:0]=71ffe07a    CLIDR=c3000123
CPU[4]  CSSELR[0:1]=201fe01a    CLIDR=c3000123
CPU[4]  CSSELR[0:0]=701fe01a    CLIDR=c3000123
CPU[4]  CSSELR[1:0]=707fe03a    CLIDR=c3000123
CPU[4]  CSSELR[2:0]=71ffe07a    CLIDR=c3000123
CPU[5]  CSSELR[0:1]=201fe01a    CLIDR=c3000123
CPU[5]  CSSELR[0:0]=701fe01a    CLIDR=c3000123
CPU[5]  CSSELR[1:0]=707fe03a    CLIDR=c3000123
CPU[5]  CSSELR[2:0]=71ffe07a    CLIDR=c3000123
CPU[6]  CSSELR[0:1]=201fe01a    CLIDR=c3000123
CPU[6]  CSSELR[0:0]=701fe01a    CLIDR=c3000123
CPU[6]  CSSELR[1:0]=707fe03a    CLIDR=c3000123
CPU[6]  CSSELR[2:0]=71ffe07a    CLIDR=c3000123
CPU[7]  CSSELR[0:1]=201fe01a    CLIDR=c3000123
CPU[7]  CSSELR[0:0]=701fe01a    CLIDR=c3000123
CPU[7]  CSSELR[1:0]=707fe03a    CLIDR=c3000123
CPU[7]  CSSELR[2:0]=71ffe07a    CLIDR=c3000123

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