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@cyyself
Created Apr 12, 2022
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module axi_perf(
input clock,
input reset,
input mem_axi4_0_awready,
output mem_axi4_0_awvalid,
output [3:0] mem_axi4_0_awid,
output [30:0] mem_axi4_0_awaddr,
output [7:0] mem_axi4_0_awlen,
output [2:0] mem_axi4_0_awsize,
output [1:0] mem_axi4_0_awburst,
input mem_axi4_0_wready,
output mem_axi4_0_wvalid,
output [63:0] mem_axi4_0_wdata,
output [7:0] mem_axi4_0_wstrb,
output mem_axi4_0_wlast,
output mem_axi4_0_bready,
input mem_axi4_0_bvalid,
input [3:0] mem_axi4_0_bid,
input [1:0] mem_axi4_0_bresp,
input mem_axi4_0_arready,
output mem_axi4_0_arvalid,
output [3:0] mem_axi4_0_arid,
output [30:0] mem_axi4_0_araddr,
output [7:0] mem_axi4_0_arlen,
output [2:0] mem_axi4_0_arsize,
output [1:0] mem_axi4_0_arburst,
output mem_axi4_0_rready,
input mem_axi4_0_rvalid,
input [3:0] mem_axi4_0_rid,
input [63:0] mem_axi4_0_rdata,
input [1:0] mem_axi4_0_rresp,
input mem_axi4_0_rlast,
output [31:0] last_read,
output [31:0] last_write
);
reg [31:0] last_read_ticks = 0;
reg [31:0] last_write_ticks = 0;
assign last_read = last_read_ticks;
assign last_write = last_write_ticks;
reg read;
reg [30:0] addr;
reg awvalid;
reg arvalid;
reg [3:0] current_burst;
assign mem_axi4_0_awvalid = awvalid;
assign mem_axi4_0_awid = 0;
assign mem_axi4_0_awaddr = addr;
assign mem_axi4_0_awlen = 8'd7; // 7 + 1 = 8
assign mem_axi4_0_awsize = 3'd3; // 2**3 = 8
assign mem_axi4_0_awburst = 2'd2; // WRAP
assign mem_axi4_0_wvalid = 1'b1;
assign mem_axi4_0_wdata = 64'hdead_beef_0f00_ba60;
assign mem_axi4_0_wstrb = 8'hff;
assign mem_axi4_0_wlast = (!read && current_burst == 4'd8);
assign mem_axi4_0_bready = 1'b1;
assign mem_axi4_0_arvalid = arvalid;
assign mem_axi4_0_arid = 0;
assign mem_axi4_0_araddr = addr;
assign mem_axi4_0_arlen = 8'd7; // 7 + 1 = 8
assign mem_axi4_0_arsize = 3'd3; // 2**3 = 8
assign mem_axi4_0_arburst = 2'd2;
assign mem_axi4_0_rready = 1'b1;
reg [31:0] read_ticks;
reg [31:0] write_ticks;
always @(posedge clock) begin
if (reset) begin
read <= 0;
read_ticks <= 0;
write_ticks <= 0;
current_burst <= 0;
addr <= 0;
awvalid <= 0;
arvalid <= 0;
end
else if (!read) begin
write_ticks <= write_ticks + 1;
if (current_burst == 0) begin
awvalid <= 1'b1;
if (awvalid && mem_axi4_0_awready) begin
current_burst <= mem_axi4_0_wready ? 4'd2 : 4'd1;
awvalid <= 1'b0;
end
end
else begin
if (mem_axi4_0_wready) begin
current_burst <= current_burst + 1;
if (current_burst == 4'd8) begin
last_write_ticks <= write_ticks;
read_ticks <= 0;
read <= 1'b1;
current_burst <= 0;
end
end
end
end
else begin
read_ticks <= read_ticks + 1;
if (current_burst == 0) begin
arvalid <= 1'b1;
if (arvalid && mem_axi4_0_arready) begin
current_burst <= mem_axi4_0_rvalid ? 4'd2 : 4'd1;
arvalid <= 0;
end
end
else begin
if (mem_axi4_0_rvalid) begin
current_burst <= current_burst + 1;
if (current_burst == 4'd8) begin
last_read_ticks <= read_ticks;
write_ticks <= 0;
read <= 1'b0;
current_burst <= 0;
end
end
end
end
end
endmodule
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