Skip to content

Instantly share code, notes, and snippets.

@dadeba
dadeba / main_grav2.c
Last active Jun 27, 2019
g5: bare metal C code
View main_grav2.c
extern float base0;
float sqrtf(float);
void grav_kernel(float *x, float *y, float *z, float *m,
float *ax, float *ay, float *az, float *pt, float *res,
int n);
int main(int argc, char * argv[])
{
@dadeba
dadeba / FPMUL.v
Last active Dec 8, 2018
pipelined FPMUL
View FPMUL.v
module FPMUL( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [31:0] io_x, // @[:@6.4]
input [31:0] io_y, // @[:@6.4]
output [31:0] io_z // @[:@6.4]
);
wire [7:0] _T_12; // @[FPBASE.scala 16:27:@9.4]
wire _T_14; // @[FPBASE.scala 27:17:@10.4]
wire [31:0] _T_18; // @[FPBASE.scala 13:33:@15.6]
@dadeba
dadeba / yuv2png.py
Last active Nov 14, 2018
YUYV422 to PNG using OpenCV
View yuv2png.py
#!/usr/bin/python3
from __future__ import print_function
import cv2
import numpy as np
import sys
import os.path
def c255(x):
return min(max(int(x),0),255)
View gist:2f8b4b49a72c1a2762f975811cbba449
+ def config_sync(self, size, direc):
+ with open(self.class_path + '/sync_size', mode='w') as f:
+ f.write(str(size))
+ with open(self.class_path + '/sync_direction', mode='w') as f:
+ f.write(str(direc))
+
+ def sync_for_cpu(self):
+ with open(self.class_path + '/sync_for_cpu', mode='w') as f:
+ f.write(str(1))
+
@dadeba
dadeba / lfc-pynq.dts
Created Aug 28, 2018
FPGA Overlay DTS file for the PYNQ-BNN MNIST example
View lfc-pynq.dts
/dts-v1/;
/ {
fragment@0 {
target-path = "/amba/fpga-region0";
#address-cells = <0x1>;
#size-cells = <0x1>;
__overlay__ {
#address-cells = <0x1>;
#size-cells = <0x1>;
@dadeba
dadeba / bnn_pynq.py
Created Aug 28, 2018
A python implementation for the PYNQ-BNN MNIST example
View bnn_pynq.py
import numpy as np
from udmabuf import Udmabuf
from uio import Uio
import os
import struct
import math
# set path to the BNN-PYQN repo.
BNN_PYNQ_ROOT = '.'
PARAM = 'bnn/params/mnist'
View pipeline_top.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pipeline_top is
port (
xi : in std_logic_vector(31 downto 0);
yi : in std_logic_vector(31 downto 0);
@dadeba
dadeba / g5.q
Last active Mar 22, 2018
pipeline description
View g5.q
/VARI xi, yi, zi, e2;
/VARJ xj, yj, zj, mj;
/VARF ax, ay, az, ap;
dx = xj - xi;
dy = yj - yi;
dz = zj - zi;
r2 = dx*dx + dy*dy + dz*dz + e2;
r1i = powm12(r2);
r2i = r1i*r1i;
r1im = mj*r1i;
View sph1.q
/VARI xi, yi, zi, vxi, vyi, vzi, hi;
/VARJ xj, yj, zj, vxj, vyj, vzj, hj, mj;
/VARF rho, rox, roy, roz, dd;
dx = xi - xj;
dy = yi - yj;
dz = zi - zj;
r2 = dx*dx + dy*dy + dz*dz;
r1 = sqrt(r2);
View test.py
import math as math
import numpy as np
from chainer import Function, FunctionSet, gradient_check, Variable, optimizers
import chainer.functions as F
model = FunctionSet(
l1 = F.Linear(1, 10),
l3 = F.Linear(10, 1),
)