dual.log

USB


[NOTE ]  coreboot-4.19-549-gdc654a071e-dirty Tue Feb 21 18:08:01 UTC 2023 x86_32 bootblock starting (log level: 7)...
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0xe50000.
[DEBUG]  FMAP: base = 0xff000000 size = 0x1000000 #areas = 5
[DEBUG]  FMAP: area COREBOOT found @ e50200 (1768960 bytes)
[INFO ]  CBFS: mcache @0xfeff0e00 built for 12 files, used 0x2ac of 0x4000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x180f8 in mcache @0xfeff0e2c
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 45 ms


[NOTE ]  coreboot-4.19-549-gdc654a071e-dirty Tue Feb 21 18:08:01 UTC 2023 x86_32 romstage starting (log level: 7)...
[INFO ]  full_reset() called!SB


[NOTE ]  coreboot-4.19-549-gdc654a071e-dirty Tue Feb 21 18:08:01 UTC 2023 x86_32 bootblock starting (log level: 7)...
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0xe50000.
[DEBUG]  FMAP: base = 0xff000000 size = 0x1000000 #areas = 5
[DEBUG]  FMAP: area COREBOOT found @ e50200 (1768960 bytes)
[INFO ]  CBFS: mcache @0xfeff0e00 built for 12 files, used 0x2ac of 0x4000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x180f8 in mcache @0xfeff0e2c
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 45 ms


[NOTE ]  coreboot-4.19-549-gdc654a071e-dirty Tue Feb 21 18:08:01 UTC 2023 x86_32 romstage starting (log level: 7)...
[DEBUG]  SMBus controller enabled
[DEBUG]  Setting up static northbridge registers... done
[DEBUG]  Initializing Graphics...
[DEBUG]  Back from systemagent_early_init()
[INFO ]  Intel ME early init
[INFO ]  Intel ME firmware is ready
[DEBUG]  ME: Requested 0MB UMA
[DEBUG]  Starting native Platform init
[DEBUG]  DMI: Running at X4 @ 5000MT/s
[DEBUG]  FMAP: area RW_MRC_CACHE found @ e00000 (65536 bytes)
[DEBUG]  Trying stored timings.
[DEBUG]  Starting Ivy Bridge RAM training (fast boot).
[DEBUG]  100MHz reference clock support: yes
[DEBUG]  PLL_REF100_CFG value: 0x2
[DEBUG]  Trying CAS 11, tCK 320.
[DEBUG]  Found compatible clock, CAS pair.
[DEBUG]  Selected DRAM frequency: 800 MHz
[DEBUG]  Selected CAS latency   : 11T
[DEBUG]  MPLL busy... done in 10 us
[DEBUG]  MPLL frequency is set at : 800 MHz
[DEBUG]  XOVER CLK [c14] = 0
[DEBUG]  XOVER CMD [320c] = 4000
[DEBUG]  XOVER CLK [d14] = 3000000
[DEBUG]  XOVER CMD [330c] = 24000
[DEBUG]  DBP [4000] = 1cbbbb
[DEBUG]  RAP [4004] = cc187476
[DEBUG]  OTHP [400c] = 68b4
[DEBUG]  OTHP [400c] = 68b4
[DEBUG]  REFI [4298] = 6cf01860
[DEBUG]  SRFTP [42a4] = 41f88200
[DEBUG]  DBP [4400] = 1cbbbb
[DEBUG]  RAP [4404] = cc187476
[DEBUG]  OTHP [440c] = 68b4
[DEBUG]  OTHP [440c] = 68b4
[DEBUG]  REFI [4698] = 6cf01860
[DEBUG]  SRFTP [46a4] = 41f88200
[DEBUG]  Done dimm mapping
[DEBUG]  Update PCI-E configuration space:
[DEBUG]  PCI(0, 0, 0)[a0] = 0
[DEBUG]  PCI(0, 0, 0)[a4] = 2
[DEBUG]  PCI(0, 0, 0)[bc] = 82a00000
[DEBUG]  PCI(0, 0, 0)[a8] = 7d600000
[DEBUG]  PCI(0, 0, 0)[ac] = 2
[DEBUG]  PCI(0, 0, 0)[b8] = 80000000
[DEBUG]  PCI(0, 0, 0)[b0] = 80a00000
[DEBUG]  PCI(0, 0, 0)[b4] = 80800000
[DEBUG]  Done memory map
[DEBUG]  RCOMP...done
[DEBUG]  COMP2 done
[DEBUG]  COMP1 done
[DEBUG]  FORCE RCOMP and wait 20us...done
[DEBUG]  Done io registers
[DEBUG]  CPE
[DEBUG]  CP5b
[DEBUG]  CP5c
[DEBUG]  OTHP [440c] = 68b4
[DEBUG]  t123: 1767, 6000, 7620
[NOTE ]  ME: Wrong mode : 2
[NOTE ]  ME: FWS2: 0x1b0a0140
[NOTE ]  ME:  Bist in progress: 0x0
[NOTE ]  ME:  ICC Status      : 0x0
[NOTE ]  ME:  Invoke MEBx     : 0x0
[NOTE ]  ME:  CPU replaced    : 0x0
[NOTE ]  ME:  MBP ready       : 0x0
[NOTE ]  ME:  MFS failure     : 0x1
[NOTE ]  ME:  Warm reset req  : 0x0
[NOTE ]  ME:  CPU repl valid  : 0x1
[NOTE ]  ME:  (Reserved)      : 0x0
[NOTE ]  ME:  FW update req   : 0x0
[NOTE ]  ME:  (Reserved)      : 0x0
[NOTE ]  ME:  Current state   : 0xa
[NOTE ]  ME:  Current PM event: 0xb
[NOTE ]  ME:  Progress code   : 0x1
[NOTE ]  PASSED! Tell ME that DRAM is ready
[NOTE ]  ME: ME is reporting as disabled, so not waiting for a response.
[NOTE ]  ME: FWS2: 0x1b0a0140
[NOTE ]  ME:  Bist in progress: 0x0
[NOTE ]  ME:  ICC Status      : 0x0
[NOTE ]  ME:  Invoke MEBx     : 0x0
[NOTE ]  ME:  CPU replaced    : 0x0
[NOTE ]  ME:  MBP ready       : 0x0
[NOTE ]  ME:  MFS failure     : 0x1
[NOTE ]  ME:  Warm reset req  : 0x0
[NOTE ]  ME:  CPU repl valid  : 0x1
[NOTE ]  ME:  (Reserved)      : 0x0
[NOTE ]  ME:  FW update req   : 0x0
[NOTE ]  ME:  (Reserved)      : 0x0
[NOTE ]  ME:  Current state   : 0xa
[NOTE ]  ME:  Current PM event: 0xb
[NOTE ]  ME:  Progress code   : 0x1
[NOTE ]  ME: Requested BIOS Action: No DID Ack received
[DEBUG]  ME: FW Partition Table      : OK
[DEBUG]  ME: Bringup Loader Failure  : NO
[DEBUG]  ME: Firmware Init Complete  : NO
[DEBUG]  ME: Manufacturing Mode      : YES
[DEBUG]  ME: Boot Options Present    : NO
[DEBUG]  ME: Update In Progress      : NO
[DEBUG]  ME: Current Working State   : Initializing
[DEBUG]  ME: Current Operation State : Bring up
[DEBUG]  ME: Current Operation Mode  : Debug or Disabled by AltDisableBit
[DEBUG]  ME: Error Code              : No Error
[DEBUG]  ME: Progress Phase          : BUP Phase
[DEBUG]  ME: Power Management Event  : Power cycle reset through Moff
[DEBUG]  ME: Progress Phase State    : Check to see if straps say ME DISABLED
[DEBUG]  memcfg DDR3 ref clock 133 MHz
[DEBUG]  memcfg DDR3 clock 1596 MHz
[DEBUG]  memcfg channel assignment: A: 1, B  0, C  2
[DEBUG]  memcfg channel[0] config (00000000):
[DEBUG]     ECC inactive
[DEBUG]     enhanced interleave mode off
[DEBUG]     rank interleave off
[DEBUG]     DIMMA 0 MB width x8 single rank, selected
[DEBUG]     DIMMB 0 MB width x8 single rank
[DEBUG]  memcfg channel[1] config (00620020):
[DEBUG]     ECC inactive
[DEBUG]     enhanced interleave mode on
[DEBUG]     rank interleave on
[DEBUG]     DIMMA 8192 MB width x8 dual rank, selected
[DEBUG]     DIMMB 0 MB width x8 single rank
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0x7ffff000 254 entries.
[DEBUG]  IMD: root @ 0x7fffec00 62 entries.
[DEBUG]  FMAP: area COREBOOT found @ e50200 (1768960 bytes)
[DEBUG]  External stage cache:
[DEBUG]  IMD: root @ 0x803ff000 254 entries.
[DEBUG]  IMD: root @ 0x803fec00 62 entries.
[DEBUG]  CBMEM entry for DIMM info: 0x7ffdc000
[DEBUG]  SMM Memory Map
[DEBUG]  SMRAM       : 0x80000000 0x800000
[DEBUG]   Subregion 0: 0x80000000 0x300000
[DEBUG]   Subregion 1: 0x80300000 0x100000
[DEBUG]   Subregion 2: 0x80400000 0x400000
[DEBUG]  Normal boot
[INFO ]  CBFS: Found 'fallback/postcar' @0x3e840 size 0x5ed0 in mcache @0xfeff0fd4
[DEBUG]  Loading module at 0x7ffd0000 with entry 0x7ffd0031. filesize: 0x5ae0 memsize: 0xbe78
[DEBUG]  Processing 236 relocs. Offset value of 0x7dfd0000
[DEBUG]  BS: romstage times (exec / console): total (unknown) / 568 ms
[DEBUG]  usbdebug: postcar starting...
[DEBUG]  Normal boot
[DEBUG]  FMAP: area COREBOOT found @ e50200 (1768960 bytes)
[INFO ]  CBFS: Found 'fallback/ramstage' @0x1ea40 size 0x1c7fc in mcache @0x7fffe9bc
[DEBUG]  Loading module at 0x7ff83000 with entry 0x7ff83000. filesize: 0x39538 memsize: 0x4b6b0
[DEBUG]  Processing 3844 relocs. Offset value of 0x7bf83000
[DEBUG]  BS: postcar times (exec / console): total (unknown) / 47 ms
[DEBUG]  usbdebug: ramstage starting...
[DEBUG]  Normal boot
[INFO ]  Enumerating buses...
[DEBUG]  Root Device scanning...
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  DOMAIN: 0000 enabled
[DEBUG]  DOMAIN: 0000 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 00
[DEBUG]  PCI: 00:00.0 [8086/0150] enabled
[DEBUG]  PCI: 00:01.0 [8086/0151] disabled
[DEBUG]  PCI: 00:02.0 [8086/0152] enabled
[DEBUG]  PCI: 00:14.0 [8086/1e31] enabled
[DEBUG]  PCI: 00:16.0: Disabling device
[DEBUG]  PCI: 00:16.0 [8086/1e3a] disabled
[DEBUG]  PCI: 00:16.1: Disabling device
[DEBUG]  PCI: 00:16.2: Disabling device
[DEBUG]  PCI: 00:16.3: Disabling device
[DEBUG]  PCI: 00:19.0: Disabling device
[DEBUG]  PCI: 00:1a.0 [8086/1e2d] enabled
[DEBUG]  PCI: 00:1b.0 [8086/1e20] enabled
[INFO ]  PCH: PCIe Root Port coalescing is enabled
[DEBUG]  PCI: 00:1c.0 [8086/1e10] enabled
[DEBUG]  PCI: 00:1c.1 [8086/1e12] enabled
[DEBUG]  PCI: 00:1c.2: Disabling device
[DEBUG]  PCI: 00:1c.2 [8086/1e14] disabled
[DEBUG]  PCI: 00:1c.3: Disabling device
[DEBUG]  PCI: 00:1c.3 [8086/1e16] disabled
[DEBUG]  PCI: 00:1c.4: Disabling device
[DEBUG]  PCI: 00:1c.4: check set enabled
[DEBUG]  PCI: 00:1c.5: Disabling device
[DEBUG]  PCI: 00:1c.6: Disabling device
[DEBUG]  PCI: 00:1c.7: Disabling device
[DEBUG]  PCI: 00:1d.0 [8086/1e26] enabled
[DEBUG]  PCI: 00:1e.0 [8086/244e] enabled
[DEBUG]  PCI: 00:1f.0 [8086/1e49] enabled
[DEBUG]  PCI: 00:1f.2 [8086/1e00] enabled
[DEBUG]  PCI: 00:1f.3 [8086/1e22] enabled
[DEBUG]  PCI: 00:1f.5: Disabling device
[DEBUG]  PCI: 00:1f.5 [8086/1e08] disabled No operations
[DEBUG]  PCI: 00:1f.6: Disabling device
[DEBUG]  PCI: 00:1f.6 [8086/1e24] disabled No operations
[WARN ]  PCI: Leftover static devices:
[WARN ]  PCI: 00:01.1
[WARN ]  PCI: 00:01.2
[WARN ]  PCI: 00:04.0
[WARN ]  PCI: 00:06.0
[WARN ]  PCI: 00:16.1
[WARN ]  PCI: 00:16.2
[WARN ]  PCI: 00:16.3
[WARN ]  PCI: 00:19.0
[WARN ]  PCI: 00:1c.4
[WARN ]  PCI: 00:1c.5
[WARN ]  PCI: 00:1c.6
[WARN ]  PCI: 00:1c.7
[WARN ]  PCI: Check your devicetree.cb.
[DEBUG]  PCI: 00:1c.0 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 01
[DEBUG]  scan_bus: bus PCI: 00:1c.0 finished in 4 msecs
[DEBUG]  PCI: 00:1c.1 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 02
[DEBUG]  PCI: 02:00.0 [10ec/8168] enabled
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled L1
[INFO ]  PCIe: Max_Payload_Size adjusted to 128
[DEBUG]  PCI: 02:00.0: No LTR support
[DEBUG]  scan_bus: bus PCI: 00:1c.1 finished in 25 msecs
[DEBUG]  PCI: 00:1e.0 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 03
[DEBUG]  scan_bus: bus PCI: 00:1e.0 finished in 4 msecs
[DEBUG]  PCI: 00:1f.0 scanning...
[DEBUG]  scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
[DEBUG]  PCI: 00:1f.3 scanning...
[DEBUG]  scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
[DEBUG]  scan_bus: bus DOMAIN: 0000 finished in 273 msecs
[DEBUG]  scan_bus: bus Root Device finished in 290 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 305 ms
[DEBUG]  found VGA at PCI: 00:02.0
[DEBUG]  Setting up VGA for PCI: 00:02.0
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[DEBUG]  Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
[DEBUG]  TOUUD 0x27d600000 TOLUD 0x82a00000 TOM 0x200000000
[DEBUG]  MEBASE 0x7ffff00000
[DEBUG]  IGD decoded, subtracting 32M UMA and 2M GTT
[DEBUG]  TSEG base 0x80000000 size 8M
[INFO ]  Available memory below 4GB: 2048M
[INFO ]  Available memory above 4GB: 6102M
[DEBUG]  PCI: 00:1a.0 EHCI BAR hook registered
[DEBUG]  More than one caller of pci_ehci_read_resources from PCI: 00:1d.0
[INFO ]  Done reading resources.
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
[DEBUG]   PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]    PCI: 02:00.0 10 *  [0x0 - 0xff] io
[DEBUG]   PCI: 00:1c.1 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]   PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]    PCI: 02:00.0 20 *  [0x0 - 0x3fff] prefmem
[DEBUG]    PCI: 02:00.0 18 *  [0x4000 - 0x4fff] prefmem
[DEBUG]   PCI: 00:1c.1 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG]   update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 1000, Size: f000, Tag: 100
[DEBUG]    PCI: 00:1c.1 1c *  [0x1000 - 0x1fff] limit: 1fff io
[DEBUG]    PCI: 00:02.0 20 *  [0x2000 - 0x203f] limit: 203f io
[DEBUG]    PCI: 00:1f.2 20 *  [0x2040 - 0x205f] limit: 205f io
[DEBUG]    PCI: 00:1f.2 10 *  [0x2060 - 0x2067] limit: 2067 io
[DEBUG]    PCI: 00:1f.2 18 *  [0x2068 - 0x206f] limit: 206f io
[DEBUG]    PCI: 00:1f.2 14 *  [0x2070 - 0x2073] limit: 2073 io
[DEBUG]    PCI: 00:1f.2 1c *  [0x2074 - 0x2077] limit: 2077 io
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG]  DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
[DEBUG]   update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 04 base 00100000 limit 7fffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 05 base 100000000 limit 27d5fffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 06 base 80000000 limit 829fffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 82a00000, Size: 6d600000, Tag: 200
[INFO ]   * Base: f4000000, Size: ac00000, Tag: 200
[INFO ]   * Base: fec01000, Size: 3ff000, Tag: 200
[INFO ]   * Base: 27d600000, Size: d82a00000, Tag: 100200
[DEBUG]    PCI: 00:02.0 18 *  [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
[DEBUG]    PCI: 00:02.0 10 *  [0x82c00000 - 0x82ffffff] limit: 82ffffff mem
[DEBUG]    PCI: 00:1c.1 24 *  [0x82a00000 - 0x82afffff] limit: 82afffff prefmem
[DEBUG]    PCI: 00:14.0 10 *  [0x82b00000 - 0x82b0ffff] limit: 82b0ffff mem
[DEBUG]    PCI: 00:1b.0 10 *  [0x82b10000 - 0x82b13fff] limit: 82b13fff mem
[DEBUG]    PCI: 00:1f.2 24 *  [0x82b14000 - 0x82b147ff] limit: 82b147ff mem
[DEBUG]    PCI: 00:1a.0 10 *  [0x82b15000 - 0x82b153ff] limit: 82b153ff mem
[DEBUG]    PCI: 00:1d.0 10 *  [0x82b16000 - 0x82b163ff] limit: 82b163ff mem
[DEBUG]    PCI: 00:1f.3 10 *  [0x82b17000 - 0x82b170ff] limit: 82b170ff mem
[DEBUG]  DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
[DEBUG]  PCI: 00:1c.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff
[INFO ]   PCI: 00:1c.1: Resource ranges:
[INFO ]   * Base: 1000, Size: 1000, Tag: 100
[DEBUG]    PCI: 02:00.0 10 *  [0x1000 - 0x10ff] limit: 10ff io
[DEBUG]  PCI: 00:1c.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done
[DEBUG]  PCI: 00:1c.1 prefmem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff
[INFO ]   PCI: 00:1c.1: Resource ranges:
[INFO ]   * Base: 82a00000, Size: 100000, Tag: 1200
[DEBUG]    PCI: 02:00.0 20 *  [0x82a00000 - 0x82a03fff] limit: 82a03fff prefmem
[DEBUG]    PCI: 02:00.0 18 *  [0x82a04000 - 0x82a04fff] limit: 82a04fff prefmem
[DEBUG]  PCI: 00:1c.1 prefmem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff done
[INFO ]  === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
[DEBUG]  PCI: 00:02.0 10 <- [0x0000000082c00000 - 0x0000000082ffffff] size 0x00400000 gran 0x16 mem64
[DEBUG]  PCI: 00:02.0 18 <- [0x0000000090000000 - 0x000000009fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG]  PCI: 00:02.0 20 <- [0x0000000000002000 - 0x000000000000203f] size 0x00000040 gran 0x06 io
[DEBUG]  PCI: 00:14.0 10 <- [0x0000000082b00000 - 0x0000000082b0ffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:1a.0 EHCI Debug Port hook triggered
[DEBUG]  PCI: 00:1a.0 10 <- [0x0000000082b15000 - 0x0000000082b153ff] size 0x00000400 gran 0x0a mem
[DEBUG]  PCI: 00:1a.0 EHCI Debug Port relocated
[DEBUG]  PCI: 00:1b.0 10 <- [0x0000000082b10000 - 0x0000000082b13fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io
[DEBUG]  PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
[DEBUG]  PCI: 00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 01 mem
[DEBUG]  PCI: 00:1c.1 1c <- [0x0000000000001000 - 0x0000000000001fff] size 0x00001000 gran 0x0c bus 02 io
[DEBUG]  PCI: 00:1c.1 24 <- [0x0000000082a00000 - 0x0000000082afffff] size 0x00100000 gran 0x14 bus 02 prefmem
[DEBUG]  PCI: 00:1c.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 02 mem
[DEBUG]  PCI: 02:00.0 10 <- [0x0000000000001000 - 0x00000000000010ff] size 0x00000100 gran 0x08 io
[DEBUG]  PCI: 02:00.0 18 <- [0x0000000082a04000 - 0x0000000082a04fff] size 0x00001000 gran 0x0c prefmem64
[DEBUG]  PCI: 02:00.0 20 <- [0x0000000082a00000 - 0x0000000082a03fff] size 0x00004000 gran 0x0e prefmem64
[DEBUG]  PCI: 00:1d.0 10 <- [0x0000000082b16000 - 0x0000000082b163ff] size 0x00000400 gran 0x0a mem
[DEBUG]  PCI: 00:1e.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 03 io
[DEBUG]  PCI: 00:1e.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
[DEBUG]  PCI: 00:1e.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 03 mem
[DEBUG]  PCI: 00:1f.2 10 <- [0x0000000000002060 - 0x0000000000002067] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:1f.2 14 <- [0x0000000000002070 - 0x0000000000002073] size 0x00000004 gran 0x02 io
[DEBUG]  PCI: 00:1f.2 18 <- [0x0000000000002068 - 0x000000000000206f] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:1f.2 1c <- [0x0000000000002074 - 0x0000000000002077] size 0x00000004 gran 0x02 io
[DEBUG]  PCI: 00:1f.2 20 <- [0x0000000000002040 - 0x000000000000205f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 00:1f.2 24 <- [0x0000000082b14000 - 0x0000000082b147ff] size 0x00000800 gran 0x0b mem
[DEBUG]  PCI: 00:1f.3 10 <- [0x0000000082b17000 - 0x0000000082b170ff] size 0x00000100 gran 0x08 mem64
[INFO ]  Done setting resources.
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 1 / 782 ms
[INFO ]  Enabling resources...
[DEBUG]  PCI: 00:00.0 subsystem <- 1462/7758
[DEBUG]  PCI: 00:00.0 cmd <- 06
[DEBUG]  PCI: 00:02.0 subsystem <- 1462/2111
[DEBUG]  PCI: 00:02.0 cmd <- 03
[DEBUG]  PCI: 00:14.0 subsystem <- 1462/7758
[DEBUG]  PCI: 00:14.0 cmd <- 102
[DEBUG]  PCI: 00:1a.0 subsystem <- 1462/7758
[DEBUG]  PCI: 00:1a.0 cmd <- 106
[DEBUG]  PCI: 00:1b.0 subsystem <- 1462/d758
[DEBUG]  PCI: 00:1b.0 cmd <- 102
[DEBUG]  PCI: 00:1c.0 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.0 subsystem <- 1462/7758
[DEBUG]  PCI: 00:1c.0 cmd <- 100
[DEBUG]  PCI: 00:1c.1 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.1 subsystem <- 1462/7758
[DEBUG]  PCI: 00:1c.1 cmd <- 107
[DEBUG]  PCI: 00:1d.0 subsystem <- 1462/7758
[DEBUG]  PCI: 00:1d.0 cmd <- 102
[DEBUG]  PCI: 00:1e.0 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1e.0 subsystem <- 1462/7758
[DEBUG]  PCI: 00:1e.0 cmd <- 100
[DEBUG]  PCI: 00:1f.0 subsystem <- 1462/7758
[DEBUG]  PCI: 00:1f.0 cmd <- 107
[DEBUG]  PCI: 00:1f.2 subsystem <- 1462/7758
[DEBUG]  PCI: 00:1f.2 cmd <- 03
[DEBUG]  PCI: 00:1f.3 subsystem <- 1462/7758
[DEBUG]  PCI: 00:1f.3 cmd <- 103
[DEBUG]  PCI: 02:00.0 cmd <- 03
[INFO ]  done.
[DEBUG]  BS: BS_DEV_ENABLE run times (exec / console): 0 / 122 ms
[INFO ]  Initializing devices...
[DEBUG]  CPU_CLUSTER: 0 init
[DEBUG]  MTRR: Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
[DEBUG]  0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0
[DEBUG]  0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1
[DEBUG]  0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0
[DEBUG]  0x0000000100000000 - 0x000000027d5fffff size 0x17d600000 type 6
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  apic_id 0x0 setup mtrr for CPU physical address size: 36 bits
[DEBUG]  MTRR: default type WB/UC MTRR counts: 4/4.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
[DEBUG]  MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1
[DEBUG]  MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6
[DEBUG]  MTRR: 3 base 0x0000000200000000 mask 0x0000000f80000000 type 6

[DEBUG]  MTRR check
[DEBUG]  Fixed MTRRs   : Enabled
[DEBUG]  Variable MTRRs: Enabled

[DEBUG]  CPU has 2 cores, 4 threads enabled.
[DEBUG]  Setting up SMI for CPU
[INFO ]  Will perform SMM setup.
[DEBUG]  FMAP: area COREBOOT found @ e50200 (1768960 bytes)
[INFO ]  CBFS: Found 'cpu_microcode_blob.bin' @0x18200 size 0x6800 in mcache @0x7fffe98c
[DEBUG]  microcode: sig=0x306a9 pf=0x2 revision=0x21
[INFO ]  CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  CPU: APIC: 00 enabled
[DEBUG]  CPU: APIC: 01 enabled
[DEBUG]  CPU: APIC: 02 enabled
[DEBUG]  CPU: APIC: 03 enabled
[DEBUG]  Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG]  Processing 16 relocs. Offset value of 0x00030000
[DEBUG]  Attempting to start 3 APs
[DEBUG]  Waiting for 10ms after sending INIT.
[DEBUG]  Waiting for SIPI to complete...
[INFO ]  LAPIC 0x1 in XAPIC mode.
[DEBUG]  done.
[INFO ]  AP: slot 1 apic_id 1, MCU rev: 0x00000021
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[INFO ]  LAPIC 0x2 in XAPIC mode.
[INFO ]  LAPIC 0x3 in XAPIC mode.
[INFO ]  AP: slot 3 apic_id 2, MCU rev: 0x00000021
[INFO ]  AP: slot 2 apic_id 3, MCU rev: 0x00000021
[DEBUG]  Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8
[DEBUG]  Processing 11 relocs. Offset value of 0x00038000
[DEBUG]  smm_module_setup_stub: stack_top = 0x80001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG]  smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG]  SMM Module: stub loaded at 38000. Will call 0x7ffa0148
[DEBUG]  Installing permanent SMM handler to 0x80000000
[DEBUG]  FX_SAVE      [0x802ff800-0x80300000]
[DEBUG]  HANDLER      [0x802fb000-0x802ff268]

[DEBUG]  CPU 0
[DEBUG]    ss0        [0x802fac00-0x802fb000]
[DEBUG]    stub0      [0x802f3000-0x802f31e8]

[DEBUG]  CPU 1
[DEBUG]    ss1        [0x802fa800-0x802fac00]
[DEBUG]    stub1      [0x802f2c00-0x802f2de8]

[DEBUG]  CPU 2
[DEBUG]    ss2        [0x802fa400-0x802fa800]
[DEBUG]    stub2      [0x802f2800-0x802f29e8]

[DEBUG]  CPU 3
[DEBUG]    ss3        [0x802fa000-0x802fa400]
[DEBUG]    stub3      [0x802f2400-0x802f25e8]

[DEBUG]  stacks       [0x80000000-0x80001000]
[DEBUG]  Loading module at 0x802fb000 with entry 0x802fbb88. filesize: 0x4150 memsize: 0x4268
[DEBUG]  Processing 256 relocs. Offset value of 0x802fb000
[DEBUG]  Loading module at 0x802f3000 with entry 0x802f3000. filesize: 0x1e8 memsize: 0x1e8
[DEBUG]  Processing 11 relocs. Offset value of 0x802f3000
[DEBUG]  smm_module_setup_stub: stack_top = 0x80001000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG]  smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x300000
[DEBUG]  SMM Module: placing smm entry code at 802f2c00,  cpu # 0x1
[DEBUG]  SMM Module: placing smm entry code at 802f2800,  cpu # 0x2
[DEBUG]  SMM Module: placing smm entry code at 802f2400,  cpu # 0x3
[DEBUG]  SMM Module: stub loaded at 802f3000. Will call 0x802fbb88
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb000, cpu = 0
[DEBUG]  In relocation handler: cpu 0
[DEBUG]  New SMBASE=0x802eb000 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eac00, cpu = 1
[DEBUG]  In relocation handler: cpu 1
[DEBUG]  New SMBASE=0x802eac00 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ea800, cpu = 2
[DEBUG]  In relocation handler: cpu 2
[DEBUG]  New SMBASE=0x802ea800 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ea400, cpu = 3
[DEBUG]  In relocation handler: cpu 3
[DEBUG]  New SMBASE=0x802ea400 IEDBASE=0x80400000
[DEBUG]  Writing SMRR. base = 0x80000006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  Initializing CPU #0
[DEBUG]  CPU: vendor Intel device 306a9
[DEBUG]  CPU: family 06, model 3a, stepping 09
[INFO ]  CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
[INFO ]  CPU: platform id 1
[INFO ]  CPU: cpuid(1) 0x306a9
[INFO ]  CPU: AES NOT supported
[INFO ]  CPU: TXT NOT supported
[INFO ]  CPU: VT supported
[DEBUG]  VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  model_x06ax: frequency set to 3300
[INFO ]  Turbo is unavailable
[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #1
[INFO ]  Initializing CPU #2
[INFO ]  Initializing CPU #3
[DEBUG]  CPU: vendor Intel device 306a9
[DEBUG]  CPU: family 06, model 3a, stepping 09
[DEBUG]  CPU: vendor Intel device 306a9
[DEBUG]  CPU: family 06, model 3a, stepping 09
[INFO ]  CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
[INFO ]  CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
[INFO ]  CPU: platform id 1
[INFO ]  CPU: platform id 1
[INFO ]  CPU: cpuid(1) 0x306a9
[INFO ]  CPU: cpuid(1) 0x306a9
[INFO ]  CPU: AES NOT supported
[INFO ]  CPU: TXT NOT supported
[INFO ]  CPU: VT supported
[INFO ]  CPU: AES NOT supported
[INFO ]  CPU: TXT NOT supported
[INFO ]  CPU: VT supported
[DEBUG]  VMX status: enabled
[DEBUG]  VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  model_x06ax: frequency set to 3300
[DEBUG]  model_x06ax: frequency set to 3300
[INFO ]  CPU #3 initialized
[INFO ]  CPU #2 initialized
[DEBUG]  CPU: vendor Intel device 306a9
[DEBUG]  CPU: family 06, model 3a, stepping 09
[INFO ]  CPU: Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz.
[INFO ]  CPU: platform id 1
[INFO ]  CPU: cpuid(1) 0x306a9
[INFO ]  CPU: AES NOT supported
[INFO ]  CPU: TXT NOT supported
[INFO ]  CPU: VT supported
[DEBUG]  VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  model_x06ax: frequency set to 3300
[INFO ]  CPU #1 initialized
[INFO ]  bsp_do_flight_plan done after 558 msecs.
[DEBUG]  SMI_STS: 
[DEBUG]  GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO1 GPIO0 
[DEBUG]  ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 
[DEBUG]  TCO_STS: 
[DEBUG]  Locking SMM.
[DEBUG]  CPU_CLUSTER: 0 init finished in 873 msecs
[DEBUG]  PCI: 00:00.0 init
[DEBUG]  Disabling PEG12.
[DEBUG]  Disabling PEG11.
[DEBUG]  Disabling PEG10.
[DEBUG]  Disabling Device 4.
[DEBUG]  Disabling PEG60.
[DEBUG]  Disabling Device 7.
[DEBUG]  Disabling PEG IO clock.
[DEBUG]  Set BIOS_RESET_CPL
[DEBUG]  CPU TDP: 55 Watts
[DEBUG]  PCI: 00:00.0 init finished in 29 msecs
[DEBUG]  PCI: 00:02.0 init
[WARN ]  CBFS: 'vbt.bin' not found.
[WARN ]  CBFS: 'pci8086,0152.rom' not found.
[WARN ]  CBFS: 'pci8086,0106.rom' not found.
[DEBUG]  PCI Option ROM loading disabled for PCI: 00:02.0
[DEBUG]  GMA: locate_vbt_vbios: d017 90f0 9e fd 8
[ERROR]  GMA: VBT couldn't be found
[DEBUG]  GT Power Management Init
[DEBUG]  IVB GT1 Power Meter Weights
[DEBUG]  GT Power Management Init (post VBIOS)
[INFO ]  framebuffer_info: bytes_per_line: 5504, bits_per_pixel: 32
[INFO ]                     x_res x y_res: 1366 x 768, size: 4227072 at 0x90000000
[DEBUG]  PCI: 00:02.0 init finished in 65 msecs
[DEBUG]  PCI: 00:14.0 init
[DEBUG]  XHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:14.0 init finished in 4 msecs
[DEBUG]  PCI: 00:1a.0 init
[DEBUG]  EHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:1a.0 init finished in 4 msecs
[DEBUG]  PCI: 00:1b.0 init
[DEBUG]  Azalia: base = 0x82b10000
[DEBUG]  Azalia: codec_mask = 09
[DEBUG]  azalia_audio: Initializing codec #3
[DEBUG]  azalia_audio: codec viddid: 80862806
[DEBUG]  azalia_audio: verb_size: 16
[DEBUG]  azalia_audio: verb loaded.
[DEBUG]  azalia_audio: Initializing codec #0
[DEBUG]  azalia_audio: codec viddid: 10ec0887
[DEBUG]  azalia_audio: verb_size: 60
[DEBUG]  azalia_audio: verb loaded.
[DEBUG]  PCI: 00:1b.0 init finished in 46 msecs
[DEBUG]  PCI: 00:1c.0 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:1c.0 init finished in 4 msecs
[DEBUG]  PCI: 00:1c.1 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:1c.1 init finished in 4 msecs
[DEBUG]  PCI: 00:1d.0 init
[DEBUG]  EHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:1d.0 init finished in 4 msecs
[DEBUG]  PCI: 00:1e.0 init
[DEBUG]  PCI init.
[DEBUG]  PCI: 00:1e.0 init finished in 2 msecs
[DEBUG]  PCI: 00:1f.0 init
[DEBUG]  pch: lpc_init
[INFO ]  PCH: detected B75, device id: 0x1e49, rev id 0x4
[DEBUG]  IOAPIC: Initializing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: 24 interrupts
[DEBUG]  IOAPIC: Clearing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: Bootstrap Processor Local APIC = 0x00
[INFO ]  Set power off after power failure.
[INFO ]  NMI sources disabled.
[DEBUG]  PantherPoint PM init
[DEBUG]  RTC: failed = 0x0
[DEBUG]  RTC Init
[DEBUG]  apm_control: Disabling ACPI.
[DEBUG]  APMC done.
[DEBUG]  pch_spi_init
[DEBUG]  PCI: 00:1f.0 init finished in 53 msecs
[DEBUG]  PCI: 00:1f.2 init
[DEBUG]  SATA: Initializing...
[DEBUG]  SATA: Controller in AHCI mode.
[DEBUG]  ABAR: 0x82b14000
[DEBUG]  PCI: 00:1f.2 init finished in 10 msecs
[DEBUG]  PCI: 00:1f.3 init
[DEBUG]  PCI: 00:1f.3 init finished in 0 msecs
[DEBUG]  PCI: 02:00.0 init
[DEBUG]  PCI: 02:00.0 init finished in 0 msecs
[INFO ]  Devices initialized
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 315 / 908 ms
[DEBUG]  FMAP: area SMMSTORE found @ e10000 (262144 bytes)
[INFO ]  Manufacturer: c2
[INFO ]  SF: Detected c2 2018 with sector size 0x1000, total 0x1000000
[DEBUG]  smm store: 4 # blocks with size 0x10000
[INFO ]  SMMSTORE: Setting up SMI handler
[DEBUG]  BS: BS_DEV_INIT exit times (exec / console): 0 / 25 ms
[INFO ]  Finalize devices...
[DEBUG]  PCI: 00:1f.0 final
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[INFO ]  Devices finalized
[DEBUG]  BS: BS_POST_DEVICE run times (exec / console): 0 / 16 ms
[INFO ]  CBFS: Found 'fallback/dsdt.aml' @0x3c300 size 0x24e7 in mcache @0x7fffea88
[WARN ]  CBFS: 'fallback/slic' not found.
[INFO ]  ACPI: Writing ACPI tables at 7ff36000.
[DEBUG]  ACPI:    * FACS
[DEBUG]  ACPI:    * DSDT
[DEBUG]  ACPI:    * FADT
[DEBUG]  ACPI: added table 1/32, length now 40
[DEBUG]  ACPI:     * SSDT
[DEBUG]  Found 1 CPU(s) with 4 core(s) each.
[DEBUG]  PSS: 3300MHz power 55000 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 43981 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2400MHz power 35986 control 0x1800 status 0x1800
[DEBUG]  PSS: 2000MHz power 28563 control 0x1400 status 0x1400
[DEBUG]  PSS: 1600MHz power 21721 control 0x1000 status 0x1000
[DEBUG]  PSS: 3300MHz power 55000 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 43981 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2400MHz power 35986 control 0x1800 status 0x1800
[DEBUG]  PSS: 2000MHz power 28563 control 0x1400 status 0x1400
[DEBUG]  PSS: 1600MHz power 21721 control 0x1000 status 0x1000
[DEBUG]  PSS: 3300MHz power 55000 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 43981 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2400MHz power 35986 control 0x1800 status 0x1800
[DEBUG]  PSS: 2000MHz power 28563 control 0x1400 status 0x1400
[DEBUG]  PSS: 1600MHz power 21721 control 0x1000 status 0x1000
[DEBUG]  PSS: 3300MHz power 55000 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 43981 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2400MHz power 35986 control 0x1800 status 0x1800
[DEBUG]  PSS: 2000MHz power 28563 control 0x1400 status 0x1400
[DEBUG]  PSS: 1600MHz power 21721 control 0x1000 status 0x1000
[DEBUG]  PCI space above 4GB MMIO is at 0x27d600000, len = 0xd82a00000
[DEBUG]  Generating ACPI PIRQ entries
[DEBUG]  ACPI: added table 2/32, length now 44
[DEBUG]  ACPI:    * MCFG
[DEBUG]  ACPI: added table 3/32, length now 48
[DEBUG]  ACPI:    * MADT
[DEBUG]  IOAPIC: 24 interrupts
[DEBUG]  ACPI: added table 4/32, length now 52
[DEBUG]  current = 7ff39d40
[DEBUG]  ACPI:    * HPET
[DEBUG]  ACPI: added table 5/32, length now 56
[INFO ]  ACPI: done.
[DEBUG]  ACPI tables: 15744 bytes.
[DEBUG]  smbios_write_tables: 7ff2e000
[DEBUG]  SMBIOS firmware version is set to coreboot_version: '4.19-549-gdc654a071e-dirty'
[INFO ]  Create SMBIOS type 16
[INFO ]  Create SMBIOS type 17
[INFO ]  Create SMBIOS type 20
[DEBUG]  SMBIOS tables: 803 bytes.
[DEBUG]  Writing table forward entry at 0x00000500
[DEBUG]  Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum dfe8
[DEBUG]  Writing coreboot table at 0x7ff5a000
[DEBUG]   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG]   1. 0000000000001000-000000000009ffff: RAM
[DEBUG]   2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG]   3. 0000000000100000-000000007ff2dfff: RAM
[DEBUG]   4. 000000007ff2e000-000000007ff82fff: CONFIGURATION TABLES
[DEBUG]   5. 000000007ff83000-000000007ffcefff: RAMSTAGE
[DEBUG]   6. 000000007ffcf000-000000007fffffff: CONFIGURATION TABLES
[DEBUG]   7. 0000000080000000-00000000829fffff: RESERVED
[DEBUG]   8. 00000000f0000000-00000000f3ffffff: RESERVED
[DEBUG]   9. 0000000100000000-000000027d5fffff: RAM
[DEBUG]  Wrote coreboot table at: 0x7ff5a000, 0x3fc bytes, checksum 6854
[DEBUG]  coreboot table: 1044 bytes.
[DEBUG]  IMD ROOT    0. 0x7ffff000 0x00001000
[DEBUG]  IMD SMALL   1. 0x7fffe000 0x00001000
[DEBUG]  CONSOLE     2. 0x7ffde000 0x00020000
[DEBUG]  TIME STAMP  3. 0x7ffdd000 0x00000910
[DEBUG]  MEM INFO    4. 0x7ffdc000 0x000007a8
[DEBUG]  AFTER CAR   5. 0x7ffcf000 0x0000d000
[DEBUG]  RAMSTAGE    6. 0x7ff82000 0x0004d000
[DEBUG]  SMM BACKUP  7. 0x7ff72000 0x00010000
[DEBUG]  SMM COMBUFFER 8. 0x7ff62000 0x00010000
[DEBUG]  COREBOOT    9. 0x7ff5a000 0x00008000
[DEBUG]  ACPI       10. 0x7ff36000 0x00024000
[DEBUG]  SMBIOS     11. 0x7ff2e000 0x00008000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0x7fffec00 0x00000400
[DEBUG]    USBDEBUG    1. 0x7fffeba0 0x00000050
[DEBUG]    RO MCACHE   2. 0x7fffe8e0 0x000002ac
[DEBUG]    FMAP        3. 0x7fffe7c0 0x0000010a
[DEBUG]    ROMSTAGE    4. 0x7fffe7a0 0x00000004
[DEBUG]    ROMSTG STCK 5. 0x7fffe6e0 0x000000a8
[DEBUG]    ACPI GNVS   6. 0x7fffe5e0 0x00000100
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 2 / 424 ms
[INFO ]  CBFS: Found 'fallback/payload' @0x44780 size 0xbed49 in mcache @0x7fffeaf8
[DEBUG]  Checking segment from ROM address 0xffe949ac
[DEBUG]  Checking segment from ROM address 0xffe949c8
[DEBUG]  Loading segment from ROM address 0xffe949ac
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x00800000 memsize 0x590000 srcaddr 0xffe949e4 filesize 0xbed11
[DEBUG]  Loading Segment: addr: 0x00800000 memsz: 0x0000000000590000 filesz: 0x00000000000bed11
[DEBUG]  using LZMA
[DEBUG]  Loading segment from ROM address 0xffe949c8
[DEBUG]    Entry Point 0x00801626
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 210 / 57 ms
[DEBUG]  ICH-NM10-PCH: watchdog disabled
[DEBUG]  Jumping to boot code at 0x00801626(0x7ff5a000)[