X550 ixgbe_t

gistfile1.txt

{
    instance = 0
    mac_hdl = 0xffffff1157164138
    dip = 0xffffff114608e010
    hw = {
        hw_addr = 0xffffff10f31a2000
        back = 0xffffff1158472788
        mac = {
            ops = {
                init_hw = ixgbe_init_hw_generic
                reset_hw = ixgbe_reset_hw_X550em
                start_hw = ixgbe_start_hw_X540
                clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic
                enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2
                get_media_type = ixgbe_get_media_type_X550em
                get_supported_physical_layer = ixgbe_get_supported_physical_layer_X550em
                get_mac_addr = ixgbe_get_mac_addr_generic
                get_san_mac_addr = 0
                set_san_mac_addr = 0
                get_device_caps = ixgbe_get_device_caps_generic
                get_wwn_prefix = 0
                get_fcoe_boot_status = 0
                stop_adapter = ixgbe_stop_adapter_generic
                get_bus_info = ixgbe_get_bus_info_X550em
                set_lan_id = ixgbe_set_lan_id_multi_port_pcie
                read_analog_reg8 = 0
                write_analog_reg8 = 0
                setup_sfp = ixgbe_setup_sfp_modules_X550em
                enable_rx_dma = ixgbe_enable_rx_dma_generic
                disable_sec_rx_path = 0
                enable_sec_rx_path = 0
                acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em
                release_swfw_sync = ixgbe_release_swfw_sync_X550em
                prot_autoc_read = 0
                prot_autoc_write = 0
                disable_tx_laser = 0
                enable_tx_laser = 0
                flap_tx_laser = 0
                setup_link = ixgbe_setup_mac_link_t_X550em
                setup_mac_link = 0
                check_link = ixgbe_check_link_t_X550em
                get_link_capabilities = ixgbe_get_link_capabilities_X550em
                set_rate_select_speed = 0
                setup_rxpba = ixgbe_set_rxpba_generic
                led_on = ixgbe_led_on_t_X550em
                led_off = ixgbe_led_off_t_X550em
                blink_led_start = ixgbe_blink_led_start_X540
                blink_led_stop = ixgbe_blink_led_stop_X540
                set_rar = ixgbe_set_rar_generic
                set_uc_addr = 0
                clear_rar = ixgbe_clear_rar_generic
                insert_mac_addr = ixgbe_insert_mac_addr_generic
                set_vmdq = ixgbe_set_vmdq_generic
                set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic
                clear_vmdq = ixgbe_clear_vmdq_generic
                init_rx_addrs = ixgbe_init_rx_addrs_generic
                update_uc_addr_list = ixgbe_update_uc_addr_list_generic
                update_mc_addr_list = ixgbe_update_mc_addr_list_generic
                enable_mc = ixgbe_enable_mc_generic
                disable_mc = ixgbe_disable_mc_generic
                clear_vfta = ixgbe_clear_vfta_generic
                set_vfta = ixgbe_set_vfta_generic
                set_vlvf = ixgbe_set_vlvf_generic
                init_uta_tables = ixgbe_init_uta_tables_generic
                set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing
                set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing
                fc_enable = ixgbe_fc_enable_generic
                setup_fc = ixgbe_setup_fc_generic
                set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic
                get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic
                disable_rx = ixgbe_disable_rx_x550
                enable_rx = ixgbe_enable_rx_generic
                set_source_address_pruning = ixgbe_set_source_address_pruning_X550
                set_ethertype_anti_spoofing = ixgbe_set_ethertype_anti_spoofing_X550
                dmac_update_tcs = ixgbe_dmac_update_tcs_X550
                dmac_config_tcs = ixgbe_dmac_config_tcs_X550
                dmac_config = ixgbe_dmac_config_X550
                setup_eee = 0
                read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550
                write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550
                disable_mdd = ixgbe_disable_mdd_X550
                enable_mdd = ixgbe_enable_mdd_X550
                mdd_event = ixgbe_mdd_event_X550
                restore_mdd_vf = ixgbe_restore_mdd_vf_X550
            }
            type = 7 (ixgbe_mac_X550EM_x)
            addr = [ 0xc, 0xc4, 0x7a, 0x7b, 0x5c, 0xbe ]
            perm_addr = [ 0xc, 0xc4, 0x7a, 0x7b, 0x5c, 0xbe ]
            san_addr = [ 0, 0, 0, 0, 0, 0 ]
            wwnn_prefix = 0
            wwpn_prefix = 0
            mta_shadow = [ 0x10000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ... ]
            mc_filter_type = 0        
            mcft_size = 0x80
            vft_size = 0x80
            num_rar_entries = 0x80
            rar_highwater = 0x1
            rx_pb_size = 0x180
            max_tx_queues = 0x80
            max_rx_queues = 0x80
            orig_autoc = 0
            san_mac_rar_index = 0
            get_link_status = 0 (0)
            orig_autoc2 = 0
            max_msix_vectors = 0x40
            arc_subsystem_valid = 0x1 (B_TRUE)
            orig_link_settings_stored = 0 (0)
            autotry_restart = 0 (0)
            flags = 0
            dmac_config = {
                watchdog_timer = 0
                fcoe_en = 0 (0)
                link_speed = 0
                fcoe_tc = 0
                num_tcs = 0
            }
            set_lben = 0 (0)
            max_link_up_time = 0x5a
        }
        addr_ctrl = {
            num_mc_addrs = 0x1
            rar_used_count = 0x1
            mta_in_use = 0x1
            overflow_promisc = 0
            user_set_promisc = 0 (0)
        }
        fc = {
            high_water = [ 0x20000, 0, 0, 0, 0, 0, 0, 0 ]
            low_water = [ 0x10000, 0, 0, 0, 0, 0, 0, 0 ]
            pause_time = 0xffff
            send_xon = 0x1 (B_TRUE)
            strict_ieee = 0 (0)
            disable_fc_autoneg = 0 (0)
            fc_was_autonegged = 0 (0)
            current_mode = 0 (ixgbe_fc_none)
            requested_mode = 0 (ixgbe_fc_none)
        }
        phy = {
            ops = {
                identify = ixgbe_identify_phy_x550em
                identify_sfp = ixgbe_identify_module_generic
                init = ixgbe_init_phy_ops_X550em
                reset = ixgbe_reset_phy_t_X550em
                read_reg = ixgbe_read_phy_reg_generic
                write_reg = ixgbe_write_phy_reg_generic
                read_reg_mdi = ixgbe_read_phy_reg_mdi
                write_reg_mdi = ixgbe_write_phy_reg_mdi
                setup_link = ixgbe_setup_phy_link_generic
                setup_internal_link = ixgbe_setup_internal_phy_t_x550em
                setup_link_speed = ixgbe_setup_phy_link_speed_generic
                check_link = 0
                get_firmware_version = ixgbe_get_phy_firmware_version_generic
                read_i2c_byte = ixgbe_read_i2c_byte_generic
                write_i2c_byte = ixgbe_write_i2c_byte_generic
                read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic
                read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic
                write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic
                i2c_bus_clear = ixgbe_i2c_bus_clear
                read_i2c_combined = ixgbe_read_i2c_combined_generic
                write_i2c_combined = ixgbe_write_i2c_combined_generic
                check_overtemp = ixgbe_tn_check_overtemp
                set_phy_power = ixgbe_set_copper_phy_power
                enter_lplu = ixgbe_enter_lplu_t_x550em
                handle_lasi = ixgbe_handle_lasi_ext_t_x550em
                read_i2c_combined_unlocked = ixgbe_read_i2c_combined_generic_unlocked
                write_i2c_combined_unlocked = ixgbe_write_i2c_combined_generic_unlocked
                read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked
                write_i2c_byte_unlocked = ixgbe_write_i2c_byte_generic_unlocked
            }
            type = 6 (ixgbe_phy_x550em_ext_t)
            addr = 0
            id = 0x1540240
            sfp_type = 0t65535 (ixgbe_sfp_type_unknown)
            sfp_setup_needed = 0 (0)
            revision = 0x2
            media_type = 4 (ixgbe_media_type_copper)
            phy_semaphore_mask = 0x2
            reset_disable = 0 (0)
            autoneg_advertised = 0xa0
            speeds_supported = 0xa0
            smart_speed = 0 (0)
            smart_speed_active = 0 (0)
            multispeed_fiber = 0 (0)
            reset_if_overtemp = 0 (0)
            qsfp_shared_i2c_bus = 0 (0)
            nw_mng_if_sel = 0x40000002
        }
        eeprom = {
            ops = {
                init_params = ixgbe_init_eeprom_params_X540
                read = ixgbe_read_ee_hostif_X550
                read_buffer = ixgbe_read_ee_hostif_buffer_X550
                write = ixgbe_write_ee_hostif_X550
                write_buffer = ixgbe_write_ee_hostif_buffer_X550
                validate_checksum = ixgbe_validate_eeprom_checksum_X550
                update_checksum = ixgbe_update_eeprom_checksum_X550
                calc_checksum = ixgbe_calc_eeprom_checksum_X550
            }
            type = 2 (ixgbe_flash)
            semaphore_delay = 0xa
            word_size = 0x2000
            address_bits = 0
            word_page_size = 0
            ctrl_word_3 = 0
        }
        bus = {
            speed = 0 (ixgbe_bus_speed_unknown)
            width = 0 (ixgbe_bus_width_unknown)
            type = 4 (ixgbe_bus_type_internal)
            func = 0
            lan_id = 0
        }
        mbx = {
            ops = {
                init_params = ixgbe_init_mbx_params_pf
                read = 0
                write = 0
                read_posted = 0
                write_posted = 0
                check_for_msg = 0
                check_for_ack = 0
                check_for_rst = 0
            }
            stats = {
                msgs_tx = 0
                msgs_rx = 0
                acks = 0
                reqs = 0
                rsts = 0
            }
            timeout = 0
            usec_delay = 0
            v2p_mailbox = 0           
            size = 0
        }
        mvals = ixgbe_mvals_X550EM_x
        device_id = 0x15ad
        vendor_id = 0x8086
        subsystem_device_id = 0x15ad
        subsystem_vendor_id = 0x15d9
        revision_id = 0
        adapter_stopped = 0 (0)
        api_version = 0
        force_full_reset = 0 (0)
        allow_unsupported_sfp = 0 (0)
        wol_enabled = 0 (0)
    }
    osdep = {
        reg_handle = 0xffffff11581ab800
        cfg_handle = 0xffffff11581ab940
        ixgbe = 0xffffff1158472000
    }
    capab = ixgbe_X550_cap
    sfp_taskq = 0xffffff1156e244b0
    overtemp_taskq = 0xffffff1156e24398
    eims = 0x8e10ffff
    eimc = 0
    eicr = 0
    ixgbe_state = 0x3
    link_state = 0 (LINK_STATE_DOWN)
    link_speed = 0
    link_duplex = 0
    reset_count = 0
    attach_progress = 0x1faff
    loopback_mode = 0
    default_mtu = 0x2328
    max_frame_size = 0x233e
    rcb_pending = 0
    vect_map = [
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0x1, 0 ]
            rxr_cnt = 0x1
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0x1 ]
            other_cnt = 0x1
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0x2, 0 ]
            rxr_cnt = 0x1
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0x4, 0 ]
            rxr_cnt = 0x1
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0x8, 0 ]
            rxr_cnt = 0x1
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0x10, 0 ]
            rxr_cnt = 0x1
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0x20, 0 ]
            rxr_cnt = 0x1
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0x40, 0 ]
            rxr_cnt = 0x1             
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0x80, 0 ]
            rxr_cnt = 0x1
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0x1, 0 ]
            txr_cnt = 0x1
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0x2, 0 ]
            txr_cnt = 0x1
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0x4, 0 ]
            txr_cnt = 0x1
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0x8, 0 ]
            txr_cnt = 0x1             
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0x10, 0 ]
            txr_cnt = 0x1
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0x20, 0 ]
            txr_cnt = 0x1
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0x40, 0 ]
            txr_cnt = 0x1
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0xffffff1158472000
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0x80, 0 ]
            txr_cnt = 0x1
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0             
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {                             
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]         
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
        {
            ixgbe = 0
            rx_map = [ 0, 0 ]
            rxr_cnt = 0
            tx_map = [ 0, 0 ]
            txr_cnt = 0
            other_map = [ 0 ]
            other_cnt = 0
        },
    ... ]
    rx_rings = 0xffffff1158300c80
    num_rx_rings = 0x8
    rx_ring_size = 0x400
    rx_buf_size = 0x2400              
    lro_enable = 0 (0)
    lro_pkt_count = 0
    rx_groups = 0xffffff11581b79e0
    num_rx_groups = 0x1
    tx_rings = 0xffffff1156fa2000
    num_tx_rings = 0x8
    tx_ring_size = 0x400
    tx_buf_size = 0x2400
    tx_ring_init = 0x1 (B_TRUE)
    tx_head_wb_enable = 0 (0)
    tx_hcksum_enable = 0x1 (B_TRUE)
    lso_enable = 0x1 (B_TRUE)
    mr_enable = 0x1 (B_TRUE)
    relax_order_enable = 0x1 (B_TRUE)
    classify_mode = 0x1
    tx_copy_thresh = 0x200
    tx_recycle_thresh = 0x13
    tx_overload_thresh = 0x2
    tx_resched_thresh = 0x80
    rx_hcksum_enable = 0x1 (B_TRUE)
    rx_copy_thresh = 0x80
    rx_limit_per_intr = 0x100
    intr_throttling = [ 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, ... ]
    intr_force = 0
    fm_capabilities = 0xf
    intr_type = 0x4
    intr_cnt = 0x10
    intr_cnt_max = 0x10
    intr_cnt_min = 0x1
    intr_cap = 0x32
    intr_size = 0x80
    intr_pri = 0x6
    htable = 0xffffff1156f3a480
    eims_mask = 0
    cb_hdl = 0xffffff114608e280
    gen_lock = {
        _opaque = [ 0 ]
    }
    watchdog_lock = {
        _opaque = [ 0 ]
    }
    rx_pending_lock = {
        _opaque = [ 0 ]
    }
    watchdog_enable = 0x1 (B_TRUE)    
    watchdog_start = 0x1 (B_TRUE)
    watchdog_tid = 0x17ffc9a1b
    unicst_init = 0x1 (B_TRUE)
    unicst_avail = 0x7f
    unicst_total = 0x80
    unicst_addr = [
        {
            reg = {
                high = 0xc40c0001
                low = 0xbe5c7b7a
            }
            mac = {
                set = 0x1
                group_index = 0
                addr = [ 0xc, 0xc4, 0x7a, 0x7b, 0x5c, 0xbe ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0       
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },                            
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0              
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {                   
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {                             
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0               
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
        {
            reg = {
                high = 0
                low = 0
            }
            mac = {
                set = 0
                group_index = 0
                addr = [ 0, 0, 0, 0, 0, 0 ]
            }
        },
    ... ]
    mcast_count = 0x1
    mcast_table = [
        {
            ether_addr_octet = [ 0x1, 0, 0x5e, 0, 0, 0x1 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },                            
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
        {
            ether_addr_octet = [ 0, 0, 0, 0, 0, 0 ]
        },
    ... ]
    sys_page_size = 0x1000
    link_check_complete = 0x1 (B_TRUE)
    link_check_hrtime = 0x936f03f62b01
    periodic_id = 1
    ixgbe_ks = 0xffffff115847d000
    param_en_10000fdx_cap = 0x1
    param_en_1000fdx_cap = 0x1
    param_en_100fdx_cap = 0x1
    param_adv_10000fdx_cap = 0x1
    param_adv_1000fdx_cap = 0x1
    param_adv_100fdx_cap = 0
    param_pause_cap = 0x1             
    param_asym_pause_cap = 0x1
    param_rem_fault = 0
    param_adv_autoneg_cap = 0x1
    param_adv_pause_cap = 0x1
    param_adv_asym_pause_cap = 0x1
    param_adv_rem_fault = 0
    param_lp_10000fdx_cap = 0
    param_lp_1000fdx_cap = 0
    param_lp_100fdx_cap = 0
    param_lp_autoneg_cap = 0
    param_lp_pause_cap = 0
    param_lp_asym_pause_cap = 0
    param_lp_rem_fault = 0
    param_pad_to_32 = 0
}