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****** START compiling Program:POPCNTAndBMI2Unrolled(int):int (MethodHash=8edbbc1e)
Generating code for Unix x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 7e 03 00 00 04 ldsfld 0x4000003
IL_0005 20 00 04 00 00 ldc.i4 0x400
IL_000a 02 ldarg.0
IL_000b 28 14 00 00 0a call 0xA000014
IL_0010 2a ret
Arg #0 passed in register(s) rdi
lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for Program:POPCNTAndBMI2Unrolled(int):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 011h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:POPCNTAndBMI2Unrolled(int):int
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [000..011)
CLFLG_MINOPT set for method Program:POPCNTAndBMI2Unrolled(int):int
IL Code Size,Instr 17, 5, Basic Block count 1, Local Variable Num,Ref count 2, 1 for method Program:POPCNTAndBMI2Unrolled(int):int
IL Code Size,Instr 17, 5, Basic Block count 1, Local Variable Num,Ref count 2, 1 for method Program:POPCNTAndBMI2Unrolled(int):int
OPTIONS: opts.MinOpts() == true
Basic block list for 'Program:POPCNTAndBMI2Unrolled(int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Program:POPCNTAndBMI2Unrolled(int):int
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:POPCNTAndBMI2Unrolled(int):int'
[ 0] 0 (0x000) ldsfld 04000003
[ 1] 5 (0x005) ldc.i4 1024
[ 2] 10 (0x00a) ldarg.0
[ 3] 11 (0x00b) call 0A000014
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[ 1] 16 (0x010) ret
[000009] ------------ * STMT void (IL 0x000... ???)
[000008] --C-G------- \--* RETURN int
[000004] --C-G------- \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
promotion opt flag not enabled
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'Program:POPCNTAndBMI2Unrolled(int):int'
fgMorphTree BB01, stmt 1 (before)
[000008] --C-G------- * RETURN int
[000004] --C-G------- \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
Morphing args for 4.CALL:
argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
Sorting the arguments:
Deferred argument ('rdi'):
[000001] x---G+------ * IND long
[000010] -----+------ \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
Replaced with placeholder node:
[000011] ----------L- * ARGPLACE long
Deferred argument ('rdx'):
[000003] -----+------ * LCL_VAR int V00 arg0
Replaced with placeholder node:
[000013] ----------L- * ARGPLACE int
Deferred argument ('rsi'):
[000002] -----+------ * CNS_INT int 0x400
Replaced with placeholder node:
[000015] ----------L- * ARGPLACE int
Shuffled argument table: rdi rdx rsi
fgArgTabEntry[arg 0 1.IND, 1 reg: rdi, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 2 3.LCL_VAR, 1 reg: rdx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 1 2.CNS_INT, 1 reg: rsi, align=1, lateArgInx=2, processed]
fgMorphTree BB01, stmt 1 (after)
[000008] --CXG+------ * RETURN int
[000004] --CXG+------ \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] x---G+------ arg0 in rdi +--* IND long
[000010] -----+------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
[000003] -----+------ arg2 in rdx +--* LCL_VAR int V00 arg0
[000002] -----+------ arg1 in rsi \--* CNS_INT int 0x400
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeBlockAndEdgeWeights()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing, so not computing edge weights
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
***** BB01, stmt 1
[000009] ------------ * STMT void (IL 0x000...0x010)
[000008] --CXG+------ \--* RETURN int
[000004] --CXG+------ \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] x---G+------ arg0 in rdi +--* IND long
[000010] -----+------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
[000003] -----+------ arg2 in rdx +--* LCL_VAR int V00 arg0
[000002] -----+------ arg1 in rsi \--* CNS_INT int 0x400
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
***** BB01, stmt 1
[000009] ------------ * STMT void (IL 0x000...0x010)
[000008] --CXG+------ \--* RETURN int
[000004] --CXG+------ \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] x---G+------ arg0 in rdi +--* IND long
[000010] -----+------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
[000003] -----+------ arg2 in rdx +--* LCL_VAR int V00 arg0
[000002] -----+------ arg1 in rsi \--* CNS_INT int 0x400
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 15 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
***** BB01, stmt 1
( 24, 27) [000009] ------------ * STMT void (IL 0x000...0x010)
N015 ( 24, 27) [000008] --CXG------- \--* RETURN int
N014 ( 23, 26) [000004] --CXG------- \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
N008 ( 5, 12) [000001] x---G------- arg0 in rdi +--* IND long
N007 ( 3, 10) [000010] ------------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
N009 ( 3, 2) [000003] ------------ arg2 in rdx +--* LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ arg1 in rsi \--* CNS_INT int 0x400
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
***** BB01, stmt 1
( 24, 27) [000009] ------------ * STMT void (IL 0x000...0x010)
N015 ( 24, 27) [000008] --CXG------- \--* RETURN int
N014 ( 23, 26) [000004] --CXG------- \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
N008 ( 5, 12) [000001] x---G------- arg0 in rdi +--* IND long
N007 ( 3, 10) [000010] ------------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
N009 ( 3, 2) [000003] ------------ arg2 in rdx +--* LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ arg1 in rsi \--* CNS_INT int 0x400
-------------------------------------------------------------------------------------------------------------------
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t1 long arg0 in rdi
+--* t3 int arg2 in rdx
+--* t2 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
outgoingArgSpaceSize 0 sufficient for call [000004], which needs 0
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t1 long arg0 in rdi
+--* t3 int arg2 in rdx
+--* t2 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
No addressing mode:
N007 ( 3, 10) [000010] ------------ * CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
lowering call (before):
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t1 long arg0 in rdi
+--* t3 int arg2 in rdx
+--* t2 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000011] ----------L- * ARGPLACE long
lowering arg : N002 ( 0, 0) [000015] ----------L- * ARGPLACE int
lowering arg : N003 ( 0, 0) [000013] ----------L- * ARGPLACE int
late:
======
lowering arg : N008 ( 5, 12) [000001] x---G------- * IND long
new node is : [000017] ----G------- * PUTARG_REG long REG rdi
lowering arg : N009 ( 3, 2) [000003] ------------ * LCL_VAR int V00 arg0
new node is : [000018] ------------ * PUTARG_REG int REG rdx
lowering arg : N010 ( 1, 4) [000002] ------------ * CNS_INT int 0x400
new node is : [000019] ------------ * PUTARG_REG int REG rsi
lowering call (after):
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
lowering GT_RETURN
N015 ( 24, 27) [000008] ---XG------- * RETURN int
============Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk ( 0)
In fgLocalVarLivenessInit
*************** In fgPerBlockLocalVarLiveness()
*************** In fgInterBlockLocalVarLiveness()
*** lvaComputeRefCounts ***
Liveness pass finished after lowering, IR:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{}
{}
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
; Decided to create an EBP based frame for ETW stackwalking (Debug Code)
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 )
BB01 [000..011) (return), preds={} succs={}
=====
N000. IL_OFFSET IL offset: 0x0
N007. t10* = CNS_INT(h) 0x7fec25be4cb8 static Fseq[_bits]
N008. t1 = IND ; t10*
N000. t17 = PUTARG_REG; t1
N009. t3 = V00 MEM
N000. t18 = PUTARG_REG; t3
N010. t2 = CNS_INT 0x400
N000. t19 = PUTARG_REG; t2
N014. t4 = CALL ; t17,t18,t19
N015. RETURN ; t4
buildIntervals second part ========
Int arg V00 in reg rdi
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N002 ( 24, 27) [000009] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N004 ( 3, 10) [000010] ------------ * CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits] REG NA
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N004.t10. CNS_INT }
N006 ( 5, 12) [000001] x---G------- * IND long REG NA
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #3 @7 RefTypeDef <Ivl:1> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N006.t1. IND }
N008 (???,???) [000017] ----G------- * PUTARG_REG long REG rdi
<RefPosition #4 @8 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #5 @8 RefTypeUse <Ivl:1> BB01 regmask=[rdi] minReg=1 last fixed>
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #6 @9 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #7 @9 RefTypeDef <Ivl:2> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N008.t17. PUTARG_REG }
N010 ( 3, 2) [000003] ------------ * LCL_VAR int V00 arg0 NA REG NA
Interval 3: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #8 @11 RefTypeDef <Ivl:3> LCL_VAR BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N008.t17. PUTARG_REG; N010.t3. LCL_VAR }
N012 (???,???) [000018] ------------ * PUTARG_REG int REG rdx
<RefPosition #9 @12 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #10 @12 RefTypeUse <Ivl:3> BB01 regmask=[rdx] minReg=1 last fixed>
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #11 @13 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #12 @13 RefTypeDef <Ivl:4> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N008.t17. PUTARG_REG; N012.t18. PUTARG_REG }
N014 ( 1, 4) [000002] ------------ * CNS_INT int 0x400 REG NA
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #13 @15 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N008.t17. PUTARG_REG; N012.t18. PUTARG_REG; N014.t2. CNS_INT }
N016 (???,???) [000019] ------------ * PUTARG_REG int REG rsi
<RefPosition #14 @16 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #15 @16 RefTypeUse <Ivl:5> BB01 regmask=[rsi] minReg=1 last fixed>
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #16 @17 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #17 @17 RefTypeDef <Ivl:6> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N008.t17. PUTARG_REG; N012.t18. PUTARG_REG; N016.t19. PUTARG_REG }
N018 ( 23, 26) [000004] --CXG------- * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
<RefPosition #18 @18 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #19 @18 RefTypeUse <Ivl:2> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #20 @18 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #21 @18 RefTypeUse <Ivl:4> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #22 @18 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #23 @18 RefTypeUse <Ivl:6> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #24 @19 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #25 @19 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #26 @19 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #27 @19 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #28 @19 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #29 @19 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #30 @19 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #31 @19 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #32 @19 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
Interval 7: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #33 @19 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @19 RefTypeDef <Ivl:7> CALL BB01 regmask=[rax] minReg=1 fixed>
+<TreeNodeInfo 1=3 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 3 produce=1
DefList: { N018.t4. CALL }
N020 ( 24, 27) [000008] ---XG------- * RETURN int REG NA
<RefPosition #35 @20 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #36 @20 RefTypeUse <Ivl:7> BB01 regmask=[rax] minReg=1 last fixed>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (constant) RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#3@7 #5@8} physReg:NA Preferences=[rdi]
Interval 2: RefPositions {#7@9 #19@18} physReg:NA Preferences=[rdi]
Interval 3: RefPositions {#8@11 #10@12} physReg:NA Preferences=[rdx]
Interval 4: RefPositions {#12@13 #21@18} physReg:NA Preferences=[rdx]
Interval 5: (constant) RefPositions {#13@15 #15@16} physReg:NA Preferences=[rsi]
Interval 6: RefPositions {#17@17 #23@18} physReg:NA Preferences=[rsi]
Interval 7: RefPositions {#34@19 #36@20} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @7 RefTypeDef <Ivl:1> IND BB01 regmask=[rdi] minReg=1>
<RefPosition #4 @8 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #5 @8 RefTypeUse <Ivl:1> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #6 @9 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #7 @9 RefTypeDef <Ivl:2> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
<RefPosition #8 @11 RefTypeDef <Ivl:3> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #9 @12 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #10 @12 RefTypeUse <Ivl:3> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #11 @13 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #12 @13 RefTypeDef <Ivl:4> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #13 @15 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[rsi] minReg=1>
<RefPosition #14 @16 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #15 @16 RefTypeUse <Ivl:5> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #16 @17 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #17 @17 RefTypeDef <Ivl:6> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed>
<RefPosition #18 @18 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #19 @18 RefTypeUse <Ivl:2> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #20 @18 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #21 @18 RefTypeUse <Ivl:4> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #22 @18 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #23 @18 RefTypeUse <Ivl:6> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #24 @19 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #25 @19 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #26 @19 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #27 @19 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #28 @19 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #29 @19 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #30 @19 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #31 @19 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #32 @19 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #33 @19 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @19 RefTypeDef <Ivl:7> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #35 @20 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #36 @20 RefTypeUse <Ivl:7> BB01 regmask=[rax] minReg=1 last fixed>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [000..011) (return), preds={} succs={}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. CNS_INT(h) 0x7fec25be4cb8 static Fseq[_bits] REG NA
Def:<I0>(#1)
N006. IND
Use:<I0>(#2) *
Def:<I1>(#3)
N008. PUTARG_REG
Use:<I1>(#5) Fixed:rdi(#4) *
Def:<I2>(#7) rdi
N010. V00 MEM
Def:<I3>(#8)
N012. PUTARG_REG
Use:<I3>(#10) Fixed:rdx(#9) *
Def:<I4>(#12) rdx
N014. CNS_INT 0x400 REG NA
Def:<I5>(#13)
N016. PUTARG_REG
Use:<I5>(#15) Fixed:rsi(#14) *
Def:<I6>(#17) rsi
N018. CALL
Use:<I2>(#19) Fixed:rdi(#18) *
Use:<I4>(#21) Fixed:rdx(#20) *
Use:<I6>(#23) Fixed:rsi(#22) *
Kill: rax rcx rdx rsi rdi r8 r9 r10 r11
Def:<I7>(#34) rax
N020. RETURN
Use:<I7>(#36) Fixed:rax(#35) *
Linear scan intervals after buildIntervals:
Interval 0: (constant) RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#3@7 #5@8} physReg:NA Preferences=[rdi]
Interval 2: RefPositions {#7@9 #19@18} physReg:NA Preferences=[rdi]
Interval 3: RefPositions {#8@11 #10@12} physReg:NA Preferences=[rdx]
Interval 4: RefPositions {#12@13 #21@18} physReg:NA Preferences=[rdx]
Interval 5: (constant) RefPositions {#13@15 #15@16} physReg:NA Preferences=[rsi]
Interval 6: RefPositions {#17@17 #23@18} physReg:NA Preferences=[rsi]
Interval 7: RefPositions {#34@19 #36@20} physReg:NA Preferences=[rax]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (constant) RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#3@7 #5@8} physReg:NA Preferences=[rdi]
Interval 2: RefPositions {#7@9 #19@18} physReg:NA Preferences=[rdi]
Interval 3: RefPositions {#8@11 #10@12} physReg:NA Preferences=[rdx]
Interval 4: RefPositions {#12@13 #21@18} physReg:NA Preferences=[rdx]
Interval 5: (constant) RefPositions {#13@15 #15@16} physReg:NA Preferences=[rsi]
Interval 6: RefPositions {#17@17 #23@18} physReg:NA Preferences=[rsi]
Interval 7: RefPositions {#34@19 #36@20} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @7 RefTypeDef <Ivl:1> IND BB01 regmask=[rdi] minReg=1>
<RefPosition #4 @8 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #5 @8 RefTypeUse <Ivl:1> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #6 @9 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #7 @9 RefTypeDef <Ivl:2> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
<RefPosition #8 @11 RefTypeDef <Ivl:3> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #9 @12 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #10 @12 RefTypeUse <Ivl:3> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #11 @13 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #12 @13 RefTypeDef <Ivl:4> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #13 @15 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[rsi] minReg=1>
<RefPosition #14 @16 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #15 @16 RefTypeUse <Ivl:5> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #16 @17 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #17 @17 RefTypeDef <Ivl:6> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed>
<RefPosition #18 @18 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #19 @18 RefTypeUse <Ivl:2> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #20 @18 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #21 @18 RefTypeUse <Ivl:4> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #22 @18 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #23 @18 RefTypeUse <Ivl:6> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #24 @19 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #25 @19 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #26 @19 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #27 @19 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #28 @19 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #29 @19 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #30 @19 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #31 @19 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #32 @19 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #33 @19 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @19 RefTypeDef <Ivl:7> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #35 @20 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #36 @20 RefTypeUse <Ivl:7> BB01 regmask=[rax] minReg=1 last fixed>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
------------------------------+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rbx |r12 |r13 |
------------------------------+----+----+----+----+----+
| | | | | |
0.#0 BB1 PredBB0 | | | | | |
------------------------------+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rbx |rdi |r12 |r13 |
------------------------------+----+----+----+----+----+----+
5.#1 C0 Def Alloc rdi | | | |C0 a| | |
6.#2 C0 Use * Keep rdi | | | |C0 a| | |
7.#3 I1 Def Alloc rdi | | | |I1 a| | |
8.#4 rdi Fixd Keep rdi | | | |I1 a| | |
8.#5 I1 Use * Keep rdi | | | |I1 a| | |
9.#6 rdi Fixd Keep rdi | | | | | | |
9.#7 I2 Def Alloc rdi | | | |I2 a| | |
------------------------------+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
------------------------------+----+----+----+----+----+----+----+
11.#8 I3 Def Alloc rdx | | |I3 a| |I2 a| | |
12.#9 rdx Fixd Keep rdx | | |I3 a| |I2 a| | |
12.#10 I3 Use * Keep rdx | | |I3 a| |I2 a| | |
13.#11 rdx Fixd Keep rdx | | | | |I2 a| | |
13.#12 I4 Def Alloc rdx | | |I4 a| |I2 a| | |
------------------------------+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
------------------------------+----+----+----+----+----+----+----+----+
15.#13 C5 Def Alloc rsi | | |I4 a| |C5 a|I2 a| | |
16.#14 rsi Fixd Keep rsi | | |I4 a| |C5 a|I2 a| | |
16.#15 C5 Use * Keep rsi | | |I4 a| |C5 a|I2 a| | |
17.#16 rsi Fixd Keep rsi | | |I4 a| | |I2 a| | |
17.#17 I6 Def Alloc rsi | | |I4 a| |I6 a|I2 a| | |
18.#18 rdi Fixd Keep rdi | | |I4 a| |I6 a|I2 a| | |
18.#19 I2 Use * Keep rdi | | |I4 a| |I6 a|I2 a| | |
18.#20 rdx Fixd Keep rdx | | |I4 a| |I6 a|I2 a| | |
18.#21 I4 Use * Keep rdx | | |I4 a| |I6 a|I2 a| | |
18.#22 rsi Fixd Keep rsi | | |I4 a| |I6 a|I2 a| | |
18.#23 I6 Use * Keep rsi | | |I4 a| |I6 a|I2 a| | |
19.#24 rax Kill Keep rax | | | | | | | | |
19.#25 rcx Kill Keep rcx | | | | | | | | |
19.#26 rdx Kill Keep rdx | | | | | | | | |
19.#27 rsi Kill Keep rsi | | | | | | | | |
19.#28 rdi Kill Keep rdi | | | | | | | | |
19.#29 r8 Kill Keep r8 | | | | | | | | |
19.#30 r9 Kill Keep r9 | | | | | | | | |
19.#31 r10 Kill Keep r10 | | | | | | | | |
19.#32 r11 Kill Keep r11 | | | | | | | | |
19.#33 rax Fixd Keep rax | | | | | | | | |
19.#34 I7 Def Alloc rax |I7 a| | | | | | | |
20.#35 rax Fixd Keep rax |I7 a| | | | | | | |
20.#36 I7 Use * Keep rax | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[rdi] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #3 @7 RefTypeDef <Ivl:1> IND BB01 regmask=[rdi] minReg=1>
<RefPosition #4 @8 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #5 @8 RefTypeUse <Ivl:1> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #6 @9 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #7 @9 RefTypeDef <Ivl:2> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
<RefPosition #8 @11 RefTypeDef <Ivl:3> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #9 @12 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #10 @12 RefTypeUse <Ivl:3> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #11 @13 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #12 @13 RefTypeDef <Ivl:4> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #13 @15 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[rsi] minReg=1>
<RefPosition #14 @16 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #15 @16 RefTypeUse <Ivl:5> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #16 @17 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #17 @17 RefTypeDef <Ivl:6> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed>
<RefPosition #18 @18 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #19 @18 RefTypeUse <Ivl:2> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #20 @18 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #21 @18 RefTypeUse <Ivl:4> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #22 @18 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #23 @18 RefTypeUse <Ivl:6> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #24 @19 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #25 @19 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #26 @19 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #27 @19 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #28 @19 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #29 @19 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #30 @19 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #31 @19 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #32 @19 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #33 @19 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @19 RefTypeDef <Ivl:7> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #35 @20 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #36 @20 RefTypeUse <Ivl:7> BB01 regmask=[rax] minReg=1 last fixed>
Active intervals at end of allocation:
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
N002 ( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N004 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits] REG rdi
/--* t10 long
N006 ( 5, 12) [000001] x---G------- t1 = * IND long REG rdi
/--* t1 long
N008 (???,???) [000017] ----G------- t17 = * PUTARG_REG long REG rdi
N010 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0 rdx REG rdx
/--* t3 int
N012 (???,???) [000018] ------------ t18 = * PUTARG_REG int REG rdx
N014 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400 REG rsi
/--* t2 int
N016 (???,???) [000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N018 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N020 ( 24, 27) [000008] ---XG------- * RETURN int REG NA
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
------------------------------+----+----+----+----+----+----+----+----+
0.#0 BB1 PredBB0 | | | | | | | | |
5.#1 C0 Def Alloc rdi | | | | | |C0 a| | |
6.#2 C0 Use * Keep rdi | | | | | |C0 i| | |
7.#3 I1 Def Alloc rdi | | | | | |I1 a| | |
8.#4 rdi Fixd Keep rdi | | | | | |I1 a| | |
8.#5 I1 Use * Keep rdi | | | | | |I1 i| | |
9.#6 rdi Fixd Keep rdi | | | | | | | | |
9.#7 I2 Def Alloc rdi | | | | | |I2 a| | |
11.#8 I3 Def Alloc rdx | | |I3 a| | |I2 a| | |
12.#9 rdx Fixd Keep rdx | | |I3 a| | |I2 a| | |
12.#10 I3 Use * Keep rdx | | |I3 i| | |I2 a| | |
13.#11 rdx Fixd Keep rdx | | | | | |I2 a| | |
13.#12 I4 Def Alloc rdx | | |I4 a| | |I2 a| | |
15.#13 C5 Def Alloc rsi | | |I4 a| |C5 a|I2 a| | |
16.#14 rsi Fixd Keep rsi | | |I4 a| |C5 a|I2 a| | |
16.#15 C5 Use * Keep rsi | | |I4 a| |C5 i|I2 a| | |
17.#16 rsi Fixd Keep rsi | | |I4 a| | |I2 a| | |
17.#17 I6 Def Alloc rsi | | |I4 a| |I6 a|I2 a| | |
18.#18 rdi Fixd Keep rdi | | |I4 a| |I6 a|I2 a| | |
18.#19 I2 Use * Keep rdi | | |I4 a| |I6 a|I2 i| | |
18.#20 rdx Fixd Keep rdx | | |I4 a| |I6 a| | | |
18.#21 I4 Use * Keep rdx | | |I4 i| |I6 a| | | |
18.#22 rsi Fixd Keep rsi | | | | |I6 a| | | |
18.#23 I6 Use * Keep rsi | | | | |I6 i| | | |
19.#24 rax Kill Keep rax | | | | | | | | |
19.#25 rcx Kill Keep rcx | | | | | | | | |
19.#26 rdx Kill Keep rdx | | | | | | | | |
19.#27 rsi Kill Keep rsi | | | | | | | | |
19.#28 rdi Kill Keep rdi | | | | | | | | |
19.#29 r8 Kill Keep r8 | | | | | | | | |
19.#30 r9 Kill Keep r9 | | | | | | | | |
19.#31 r10 Kill Keep r10 | | | | | | | | |
19.#32 r11 Kill Keep r11 | | | | | | | | |
19.#33 rax Fixd Keep rax | | | | | | | | |
19.#34 I7 Def Alloc rax |I7 a| | | | | | | |
20.#35 rax Fixd Keep rax |I7 a| | | | | | | |
20.#36 I7 Use * Keep rax |I7 i| | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 0
Total Reg Cand Vars: 0
Total number of Intervals: 7
Total number of RefPositions: 36
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [000..011) (return), preds={} succs={}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. rdi* = CNS_INT(h) 0x7fec25be4cb8 static Fseq[_bits] REG rdi
N006. rdi = IND ; rdi*
N008. rdi = PUTARG_REG; rdi
N010. rdx = V00 MEM
N012. rdx = PUTARG_REG; rdx
N014. rsi = CNS_INT 0x400 REG rsi
N016. rsi = PUTARG_REG; rsi
N018. rax = CALL ; rdi,rdx,rsi
N020. RETURN ; rax
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [rax rcx rdx rsi rdi r8-r11]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V00 arg0, size=4, stkOffs=-0x14
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) int -> [rbp-0x04]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
;
; Lcl frame size = 16
=============== Generating BB01 [000..011) (return), preds={} succs={} flags=0x00000000.400b0020: i label target gcsafe LIR
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M17377_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Setting stack level from -572662307 to 0
Scope info: begin block BB01, IL range [000..011)
Scope info: open scopes =
<none>
Added IP mapping: 0x0000 STACK_EMPTY (G_M17377_IG02,ins#0,ofs#0) label
Generating: N002 ( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N004 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits] REG rdi
IN0001: mov rdi, 0x7FEC25BE4CB8
/--* t10 long
Generating: N006 ( 5, 12) [000001] x---G------- t1 = * IND long REG rdi
IN0002: mov rdi, qword ptr [rdi]
/--* t1 long
Generating: N008 (???,???) [000017] ----G------- t17 = * PUTARG_REG long REG rdi
Generating: N010 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0 rdx REG rdx
IN0003: mov edx, dword ptr [V00 rbp-04H]
/--* t3 int
Generating: N012 (???,???) [000018] ------------ t18 = * PUTARG_REG int REG rdx
Generating: N014 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400 REG rsi
IN0004: mov esi, 0x400
/--* t2 int
Generating: N016 (???,???) [000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
Generating: N018 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0005: call GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
/--* t4 int
Generating: N020 ( 24, 27) [000008] ---XG------- * RETURN int REG NA
Scope info: end block BB01, IL range [000..011)
Scope info: ending scope, LVnum=0 [000..011)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M17377_IG02,ins#5,ofs#26) label
Reserving epilog IG for block BB01
IN0006: nop
G_M17377_IG02: ; offs=000000H, funclet=00
*************** After placeholder IG creation
G_M17377_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M17377_IG02: ; offs=000000H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M17377_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 24, compSizeEstimate = 27 Program:POPCNTAndBMI2Unrolled(int):int
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) int -> [rbp-0x04]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
;
; Lcl frame size = 16
*************** Before prolog / epilog generation
G_M17377_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M17377_IG02: ; offs=000000H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M17377_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M17377_IG01,ins#0,ofs#0) label
__prolog:
IN0007: push rbp
IN0008: sub rsp, 16
IN0009: lea rbp, [rsp+10H]
*************** In genClearStackVec3ArgUpperBits()
*************** In genFnPrologCalleeRegArgs() for int regs
IN000a: mov dword ptr [V00 rbp-04H], edi
*************** In genEnregisterIncomingStackArgs()
G_M17377_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN000b: lea rsp, [rbp]
IN000c: pop rbp
IN000d: ret
G_M17377_IG03: ; offs=00001BH, funclet=00
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M17377_IG01: ; func=00, offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M17377_IG02: ; offs=00000DH, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M17377_IG03: ; offs=000028H, size=0006H, epilog, nogc, emitadd
*************** In emitJumpDistBind()
Hot code size = 0x2E bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M17377_IG01: ; func=00, offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0007: 000000 55 push rbp
IN0008: 000001 4883EC10 sub rsp, 16
IN0009: 000005 488D6C2410 lea rbp, [rsp+10H]
IN000a: 00000A 897DFC mov dword ptr [rbp-04H], edi
G_M17377_IG02: ; func=00, offs=00000DH, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 00000D 48BFB84CBE25EC7F0000 mov rdi, 0x7FEC25BE4CB8
IN0002: 000017 488B3F mov rdi, qword ptr [rdi]
IN0003: 00001A 8B55FC mov edx, dword ptr [rbp-04H]
IN0004: 00001D BE00040000 mov esi, 0x400
; Call at 0022 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0005: 000022 E821D9FFFF call GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
IN0006: 000027 90 nop
G_M17377_IG03: ; func=00, offs=000028H, size=0006H, epilog, nogc, emitadd
IN000b: 000028 488D6500 lea rsp, [rbp]
IN000c: 00002C 5D pop rbp
IN000d: 00002D C3 ret
Allocated method code size = 46 , actual size = 46
*************** After end code gen, before unwindEmit()
G_M17377_IG01: ; func=00, offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0007: 000000 push rbp
IN0008: 000001 sub rsp, 16
IN0009: 000005 lea rbp, [rsp+10H]
IN000a: 00000A mov dword ptr [V00 rbp-04H], edi
G_M17377_IG02: ; offs=00000DH, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 00000D mov rdi, 0x7FEC25BE4CB8
IN0002: 000017 mov rdi, qword ptr [rdi]
IN0003: 00001A mov edx, dword ptr [V00 rbp-04H]
IN0004: 00001D mov esi, 0x400
IN0005: 000022 call GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
IN0006: 000027 nop
G_M17377_IG03: ; offs=000028H, size=0006H, epilog, nogc, emitadd
IN000b: 000028 lea rsp, [rbp]
IN000c: 00002C pop rbp
IN000d: 00002D ret
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x00002e (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x05
CountOfUnwindCodes: 2
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 1 * 8 + 8 = 16 = 0x10
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x00007FEC268639A0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x2e, unwindSize=0x8, pUnwindBlock=0x0000000001401128, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 3
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000000D ( STACK_EMPTY )
IL offs EPILOG : 0x00000027 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 1
*************** Variable debug info
1 vars
0( UNKNOWN) : From 00000000h to 0000000Dh, in rdi
*************** In gcInfoBlockHdrSave()
Set code length to 46.
Set ReturnKind to Scalar.
Set stack base register to rbp.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:
Method code size: 46
Allocations for Program:POPCNTAndBMI2Unrolled(int):int (MethodHash=8edbbc1e)
count: 184, size: 20915, max = 2600
allocateMemory: 65536, nraUsed: 23288
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 0 | 0.00%
ASTNode | 2560 | 12.24%
InstDesc | 2568 | 12.28%
ImpStack | 384 | 1.84%
BasicBlock | 864 | 4.13%
fgArgInfo | 192 | 0.92%
fgArgInfoPtrArr | 24 | 0.11%
FlowList | 0 | 0.00%
TreeStatementList | 0 | 0.00%
SiScope | 72 | 0.34%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 0 | 0.00%
LSRA | 2960 | 14.15%
LSRA_Interval | 640 | 3.06%
LSRA_RefPosition | 2368 | 11.32%
Reachability | 0 | 0.00%
SSA | 0 | 0.00%
ValueNumber | 0 | 0.00%
LvaTable | 1792 | 8.57%
UnwindInfo | 0 | 0.00%
hashBv | 40 | 0.19%
bitset | 56 | 0.27%
FixedBitVect | 8 | 0.04%
Generic | 638 | 3.05%
IndirAssignMap | 0 | 0.00%
FieldSeqStore | 176 | 0.84%
ZeroOffsetFieldMap | 0 | 0.00%
ArrayInfoMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 0 | 0.00%
GC | 1288 | 6.16%
CorSig | 104 | 0.50%
Inlining | 128 | 0.61%
ArrayStack | 0 | 0.00%
DebugInfo | 168 | 0.80%
DebugOnly | 2644 | 12.64%
Codegen | 1144 | 5.47%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 97 | 0.46%
RangeCheck | 0 | 0.00%
CopyProp | 0 | 0.00%
SideEffects | 0 | 0.00%
****** DONE compiling Program:POPCNTAndBMI2Unrolled(int):int
****** START compiling GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int (MethodHash=cbde5985)
Generating code for Unix x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 02 ldarg.0
IL_0001 0a stloc.0
IL_0002 2b 37 br.s 55 (IL_003b)
IL_0004 04 ldarg.2
IL_0005 06 ldloc.0
IL_0006 4c ldind.i8
IL_0007 28 0d 00 00 0a call 0xA00000D
IL_000c 06 ldloc.0
IL_000d 1e ldc.i4.8
IL_000e 58 add
IL_000f 4c ldind.i8
IL_0010 28 0d 00 00 0a call 0xA00000D
IL_0015 58 add
IL_0016 06 ldloc.0
IL_0017 18 ldc.i4.2
IL_0018 d3 conv.i
IL_0019 1e ldc.i4.8
IL_001a 5a mul
IL_001b 58 add
IL_001c 4c ldind.i8
IL_001d 28 0d 00 00 0a call 0xA00000D
IL_0022 58 add
IL_0023 06 ldloc.0
IL_0024 19 ldc.i4.3
IL_0025 d3 conv.i
IL_0026 1e ldc.i4.8
IL_0027 5a mul
IL_0028 58 add
IL_0029 4c ldind.i8
IL_002a 28 0d 00 00 0a call 0xA00000D
IL_002f 58 add
IL_0030 69 conv.i4
IL_0031 59 sub
IL_0032 10 02 starg.s 0x2
IL_0034 06 ldloc.0
IL_0035 1a ldc.i4.4
IL_0036 d3 conv.i
IL_0037 1e ldc.i4.8
IL_0038 5a mul
IL_0039 58 add
IL_003a 0a stloc.0
IL_003b 04 ldarg.2
IL_003c 20 00 01 00 00 ldc.i4 0x100
IL_0041 2f c1 bge.s -63 (IL_0004)
IL_0043 04 ldarg.2
IL_0044 0b stloc.1
IL_0045 2b 12 br.s 18 (IL_0059)
IL_0047 04 ldarg.2
IL_0048 0b stloc.1
IL_0049 04 ldarg.2
IL_004a 06 ldloc.0
IL_004b 4c ldind.i8
IL_004c 28 0d 00 00 0a call 0xA00000D
IL_0051 69 conv.i4
IL_0052 59 sub
IL_0053 10 02 starg.s 0x2
IL_0055 06 ldloc.0
IL_0056 1e ldc.i4.8
IL_0057 58 add
IL_0058 0a stloc.0
IL_0059 04 ldarg.2
IL_005a 16 ldc.i4.0
IL_005b 30 ea bgt.s -22 (IL_0047)
IL_005d 06 ldloc.0
IL_005e 1e ldc.i4.8
IL_005f 59 sub
IL_0060 0a stloc.0
IL_0061 17 ldc.i4.1
IL_0062 6a conv.i8
IL_0063 07 ldloc.1
IL_0064 17 ldc.i4.1
IL_0065 59 sub
IL_0066 1f 3f ldc.i4.s 0x3F
IL_0068 5f and
IL_0069 62 shl
IL_006a 06 ldloc.0
IL_006b 4c ldind.i8
IL_006c 28 11 00 00 0a call 0xA000011
IL_0071 28 12 00 00 0a call 0xA000012
IL_0076 69 conv.i4
IL_0077 0c stloc.2
IL_0078 06 ldloc.0
IL_0079 02 ldarg.0
IL_007a 59 sub
IL_007b 1e ldc.i4.8
IL_007c 5b div
IL_007d 6a conv.i8
IL_007e 1f 40 ldc.i4.s 0x40
IL_0080 6a conv.i8
IL_0081 5a mul
IL_0082 69 conv.i4
IL_0083 08 ldloc.2
IL_0084 58 add
IL_0085 2a ret
Arg #0 passed in register(s) rdi
Arg #1 passed in register(s) rsi
Arg #2 passed in register(s) rdx
lvaGrabTemp returning 6 (V06 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 long
; V01 arg1 int
; V02 arg2 int
; V03 loc0 long
; V04 loc1 int
; V05 loc2 int
; V06 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 6
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 086h
1: 01h 01h V01 arg1 000h 086h
2: 02h 02h V02 arg2 000h 086h
3: 03h 03h V03 loc0 000h 086h
4: 04h 04h V04 loc1 000h 086h
5: 05h 05h V05 loc2 000h 086h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
Jump targets:
IL_0004
IL_003b
IL_0047
IL_0059
New Basic Block BB01 [0000] created.
BB01 [000..004)
New Basic Block BB02 [0001] created.
BB02 [004..03B)
New Basic Block BB03 [0002] created.
BB03 [03B..043)
New Basic Block BB04 [0003] created.
BB04 [043..047)
New Basic Block BB05 [0004] created.
BB05 [047..059)
New Basic Block BB06 [0005] created.
BB06 [059..05D)
New Basic Block BB07 [0006] created.
BB07 [05D..086)
CLFLG_MINOPT set for method GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
IL Code Size,Instr 134, 94, Basic Block count 7, Local Variable Num,Ref count 7, 29 for method GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
IL Code Size,Instr 134, 94, Basic Block count 7, Local Variable Num,Ref count 7, 29 for method GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
OPTIONS: opts.MinOpts() == true
Basic block list for 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always)
BB02 [0001] 1 1 [004..03B) bwd
BB03 [0002] 2 1 [03B..043)-> BB02 ( cond ) bwd
BB04 [0003] 1 1 [043..047)-> BB06 (always)
BB05 [0004] 1 1 [047..059) bwd
BB06 [0005] 2 1 [059..05D)-> BB05 ( cond ) bwd
BB07 [0006] 1 1 [05D..086) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) stloc.0
[000004] ------------ * STMT void (IL 0x000... ???)
[000001] ------------ | /--* LCL_VAR long V00 arg0
[000003] -A---------- \--* ASG long
[000002] D------N---- \--* LCL_VAR long V03 loc0
[ 0] 2 (0x002) br.s
impImportBlockPending for BB03
Importing BB03 (PC=059) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 59 (0x03b) ldarg.2
[ 1] 60 (0x03c) ldc.i4 256
[ 2] 65 (0x041) bge.s
[000010] ------------ * STMT void (IL 0x03B... ???)
[000009] ------------ \--* JTRUE void
[000007] ------------ | /--* CNS_INT int 256
[000008] ------------ \--* GE int
[000006] ------------ \--* LCL_VAR int V02 arg2
impImportBlockPending for BB04
impImportBlockPending for BB02
Importing BB02 (PC=004) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 4 (0x004) ldarg.2
[ 1] 5 (0x005) ldloc.0
[ 2] 6 (0x006) ldind.i8
[ 2] 7 (0x007) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 2] 12 (0x00c) ldloc.0
[ 3] 13 (0x00d) ldc.i4.8 8
[ 4] 14 (0x00e) add
[ 3] 15 (0x00f) ldind.i8
[ 3] 16 (0x010) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 3] 21 (0x015) add
[ 2] 22 (0x016) ldloc.0
[ 3] 23 (0x017) ldc.i4.2 2
[ 4] 24 (0x018) conv.i
[ 4] 25 (0x019) ldc.i4.8 8
[ 5] 26 (0x01a) mul
[ 4] 27 (0x01b) add
[ 3] 28 (0x01c) ldind.i8
[ 3] 29 (0x01d) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 3] 34 (0x022) add
[ 2] 35 (0x023) ldloc.0
[ 3] 36 (0x024) ldc.i4.3 3
[ 4] 37 (0x025) conv.i
[ 4] 38 (0x026) ldc.i4.8 8
[ 5] 39 (0x027) mul
[ 4] 40 (0x028) add
[ 3] 41 (0x029) ldind.i8
[ 3] 42 (0x02a) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 3] 47 (0x02f) add
[ 2] 48 (0x030) conv.i4
[ 2] 49 (0x031) sub
[ 1] 50 (0x032) starg.s 2
[000047] ------------ * STMT void (IL 0x004... ???)
[000043] ---XG------- | /--* CAST int <- long
[000041] ---XG------- | | | /--* HWIntrinsic long PopCount
[000040] *--XG------- | | | | \--* IND long
[000037] ------------ | | | | | /--* CAST long <- int
[000036] ------------ | | | | | | \--* CNS_INT int 8
[000038] ------------ | | | | | /--* MUL long
[000035] ------------ | | | | | | \--* CAST long <- int
[000034] ------------ | | | | | | \--* CNS_INT int 3
[000039] ------------ | | | | \--* ADD long
[000033] ------------ | | | | \--* LCL_VAR long V03 loc0
[000042] ---XG------- | | \--* ADD long
[000031] ---XG------- | | | /--* HWIntrinsic long PopCount
[000030] *--XG------- | | | | \--* IND long
[000027] ------------ | | | | | /--* CAST long <- int
[000026] ------------ | | | | | | \--* CNS_INT int 8
[000028] ------------ | | | | | /--* MUL long
[000025] ------------ | | | | | | \--* CAST long <- int
[000024] ------------ | | | | | | \--* CNS_INT int 2
[000029] ------------ | | | | \--* ADD long
[000023] ------------ | | | | \--* LCL_VAR long V03 loc0
[000032] ---XG------- | | \--* ADD long
[000021] ---XG------- | | | /--* HWIntrinsic long PopCount
[000020] *--XG------- | | | | \--* IND long
[000018] ------------ | | | | | /--* CAST long <- int
[000017] ------------ | | | | | | \--* CNS_INT int 8
[000019] ------------ | | | | \--* ADD long
[000016] ------------ | | | | \--* LCL_VAR long V03 loc0
[000022] ---XG------- | | \--* ADD long
[000015] ---XG------- | | \--* HWIntrinsic long PopCount
[000014] *--XG------- | | \--* IND long
[000013] ------------ | | \--* LCL_VAR long V03 loc0
[000044] ---XG------- | /--* SUB int
[000012] ------------ | | \--* LCL_VAR int V02 arg2
[000046] -A-XG------- \--* ASG int
[000045] D------N---- \--* LCL_VAR int V02 arg2
[ 0] 52 (0x034) ldloc.0
[ 1] 53 (0x035) ldc.i4.4 4
[ 2] 54 (0x036) conv.i
[ 2] 55 (0x037) ldc.i4.8 8
[ 3] 56 (0x038) mul
[ 2] 57 (0x039) add
[ 1] 58 (0x03a) stloc.0
[000057] ------------ * STMT void (IL 0x034... ???)
[000052] ------------ | /--* CAST long <- int
[000051] ------------ | | \--* CNS_INT int 8
[000053] ------------ | /--* MUL long
[000050] ------------ | | \--* CAST long <- int
[000049] ------------ | | \--* CNS_INT int 4
[000054] ------------ | /--* ADD long
[000048] ------------ | | \--* LCL_VAR long V03 loc0
[000056] -A---------- \--* ASG long
[000055] D------N---- \--* LCL_VAR long V03 loc0
impImportBlockPending for BB03
Importing BB04 (PC=067) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 67 (0x043) ldarg.2
[ 1] 68 (0x044) stloc.1
[000062] ------------ * STMT void (IL 0x043... ???)
[000059] ------------ | /--* LCL_VAR int V02 arg2
[000061] -A---------- \--* ASG int
[000060] D------N---- \--* LCL_VAR int V04 loc1
[ 0] 69 (0x045) br.s
impImportBlockPending for BB06
Importing BB06 (PC=089) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 89 (0x059) ldarg.2
[ 1] 90 (0x05a) ldc.i4.0 0
[ 2] 91 (0x05b) bgt.s
[000068] ------------ * STMT void (IL 0x059... ???)
[000067] ------------ \--* JTRUE void
[000065] ------------ | /--* CNS_INT int 0
[000066] ------------ \--* GT int
[000064] ------------ \--* LCL_VAR int V02 arg2
impImportBlockPending for BB07
impImportBlockPending for BB05
Importing BB05 (PC=071) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 71 (0x047) ldarg.2
[ 1] 72 (0x048) stloc.1
[000073] ------------ * STMT void (IL 0x047... ???)
[000070] ------------ | /--* LCL_VAR int V02 arg2
[000072] -A---------- \--* ASG int
[000071] D------N---- \--* LCL_VAR int V04 loc1
[ 0] 73 (0x049) ldarg.2
[ 1] 74 (0x04a) ldloc.0
[ 2] 75 (0x04b) ldind.i8
[ 2] 76 (0x04c) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 2] 81 (0x051) conv.i4
[ 2] 82 (0x052) sub
[ 1] 83 (0x053) starg.s 2
[000082] ------------ * STMT void (IL 0x049... ???)
[000078] ---XG------- | /--* CAST int <- long
[000077] ---XG------- | | \--* HWIntrinsic long PopCount
[000076] *--XG------- | | \--* IND long
[000075] ------------ | | \--* LCL_VAR long V03 loc0
[000079] ---XG------- | /--* SUB int
[000074] ------------ | | \--* LCL_VAR int V02 arg2
[000081] -A-XG------- \--* ASG int
[000080] D------N---- \--* LCL_VAR int V02 arg2
[ 0] 85 (0x055) ldloc.0
[ 1] 86 (0x056) ldc.i4.8 8
[ 2] 87 (0x057) add
[ 1] 88 (0x058) stloc.0
[000089] ------------ * STMT void (IL 0x055... ???)
[000085] ------------ | /--* CAST long <- int
[000084] ------------ | | \--* CNS_INT int 8
[000086] ------------ | /--* ADD long
[000083] ------------ | | \--* LCL_VAR long V03 loc0
[000088] -A---------- \--* ASG long
[000087] D------N---- \--* LCL_VAR long V03 loc0
impImportBlockPending for BB06
Importing BB07 (PC=093) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 93 (0x05d) ldloc.0
[ 1] 94 (0x05e) ldc.i4.8 8
[ 2] 95 (0x05f) sub
[ 1] 96 (0x060) stloc.0
[000097] ------------ * STMT void (IL 0x05D... ???)
[000093] ------------ | /--* CAST long <- int
[000092] ------------ | | \--* CNS_INT int 8
[000094] ------------ | /--* SUB long
[000091] ------------ | | \--* LCL_VAR long V03 loc0
[000096] -A---------- \--* ASG long
[000095] D------N---- \--* LCL_VAR long V03 loc0
[ 0] 97 (0x061) ldc.i4.1 1
[ 1] 98 (0x062) conv.i8
[ 1] 99 (0x063) ldloc.1
[ 2] 100 (0x064) ldc.i4.1 1
[ 3] 101 (0x065) sub
[ 2] 102 (0x066) ldc.i4.s 63
[ 3] 104 (0x068) and
[ 2] 105 (0x069) shl
[ 1] 106 (0x06a) ldloc.0
[ 2] 107 (0x06b) ldind.i8
[ 2] 108 (0x06c) call 0A000011
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 1] 113 (0x071) call 0A000012
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 1] 118 (0x076) conv.i4
[ 1] 119 (0x077) stloc.2
[000113] ------------ * STMT void (IL 0x061... ???)
[000110] ---XG------- | /--* CAST int <- long
[000109] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG------- | | | /--* IND long
[000106] ------------ | | | | \--* LCL_VAR long V03 loc0
[000108] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
[000103] ------------ | | | /--* CNS_INT int 63
[000104] ------------ | | | /--* AND int
[000101] ------------ | | | | | /--* CNS_INT int 1
[000102] ------------ | | | | \--* SUB int
[000100] ------------ | | | | \--* LCL_VAR int V04 loc1
[000105] ------------ | | \--* LSH long
[000099] ------------ | | \--* CAST long <- int
[000098] ------------ | | \--* CNS_INT int 1
[000112] -A-XG------- \--* ASG int
[000111] D------N---- \--* LCL_VAR int V05 loc2
[ 0] 120 (0x078) ldloc.0
[ 1] 121 (0x079) ldarg.0
[ 2] 122 (0x07a) sub
[ 1] 123 (0x07b) ldc.i4.8 8
[ 2] 124 (0x07c) div
[ 1] 125 (0x07d) conv.i8
[ 1] 126 (0x07e) ldc.i4.s 64
[ 2] 128 (0x080) conv.i8
[ 2] 129 (0x081) mul
[ 1] 130 (0x082) conv.i4
[ 1] 131 (0x083) ldloc.2
[ 2] 132 (0x084) add
[ 1] 133 (0x085) ret
[000127] ------------ * STMT void (IL 0x078... ???)
[000126] ---X-------- \--* RETURN int
[000124] ------------ | /--* LCL_VAR int V05 loc2
[000125] ---X-------- \--* ADD int
[000123] ---X-------- \--* CAST int <- long
[000121] ------------ | /--* CAST long <- int
[000120] ------------ | | \--* CNS_INT int 64
[000122] ---X-------- \--* MUL long
[000118] ------------ | /--* CAST long <- int
[000117] ------------ | | \--* CNS_INT int 8
[000119] ---X-------- \--* DIV long
[000115] ------------ | /--* LCL_VAR long V00 arg0
[000116] ------------ \--* SUB long
[000114] ------------ \--* LCL_VAR long V03 loc0
New BlockSet epoch 1, # of blocks (including unused BB00): 8, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i
BB02 [0001] 1 1 [004..03B) i bwd
BB03 [0002] 2 1 [03B..043)-> BB02 ( cond ) i bwd
BB04 [0003] 1 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 1 [047..059) i bwd
BB06 [0005] 2 1 [059..05D)-> BB05 ( cond ) i bwd
BB07 [0006] 1 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
promotion opt flag not enabled
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB01, stmt 1 (before)
[000001] ------------ /--* LCL_VAR long V00 arg0
[000003] -A---------- * ASG long
[000002] D------N---- \--* LCL_VAR long V03 loc0
Morphing BB02 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB02, stmt 2 (before)
[000043] ---XG------- /--* CAST int <- long
[000041] ---XG------- | | /--* HWIntrinsic long PopCount
[000040] *--XG------- | | | \--* IND long
[000037] ------------ | | | | /--* CAST long <- int
[000036] ------------ | | | | | \--* CNS_INT int 8
[000038] ------------ | | | | /--* MUL long
[000035] ------------ | | | | | \--* CAST long <- int
[000034] ------------ | | | | | \--* CNS_INT int 3
[000039] ------------ | | | \--* ADD long
[000033] ------------ | | | \--* LCL_VAR long V03 loc0
[000042] ---XG------- | \--* ADD long
[000031] ---XG------- | | /--* HWIntrinsic long PopCount
[000030] *--XG------- | | | \--* IND long
[000027] ------------ | | | | /--* CAST long <- int
[000026] ------------ | | | | | \--* CNS_INT int 8
[000028] ------------ | | | | /--* MUL long
[000025] ------------ | | | | | \--* CAST long <- int
[000024] ------------ | | | | | \--* CNS_INT int 2
[000029] ------------ | | | \--* ADD long
[000023] ------------ | | | \--* LCL_VAR long V03 loc0
[000032] ---XG------- | \--* ADD long
[000021] ---XG------- | | /--* HWIntrinsic long PopCount
[000020] *--XG------- | | | \--* IND long
[000018] ------------ | | | | /--* CAST long <- int
[000017] ------------ | | | | | \--* CNS_INT int 8
[000019] ------------ | | | \--* ADD long
[000016] ------------ | | | \--* LCL_VAR long V03 loc0
[000022] ---XG------- | \--* ADD long
[000015] ---XG------- | \--* HWIntrinsic long PopCount
[000014] *--XG------- | \--* IND long
[000013] ------------ | \--* LCL_VAR long V03 loc0
[000044] ---XG------- /--* SUB int
[000012] ------------ | \--* LCL_VAR int V02 arg2
[000046] -A-XG------- * ASG int
[000045] D------N---- \--* LCL_VAR int V02 arg2
fgMorphTree BB02, stmt 2 (after)
[000129] ---XG+------ /--* CAST int <- long
[000041] ---XG+------ | \--* HWIntrinsic long PopCount
[000040] *--XG+------ | \--* IND long
[000037] -----+------ | | /--* CAST long <- int
[000036] -----+------ | | | \--* CNS_INT int 8
[000038] -----+------ | | /--* MUL long
[000035] -----+------ | | | \--* CAST long <- int
[000034] -----+------ | | | \--* CNS_INT int 3
[000039] -----+------ | \--* ADD long
[000033] -----+------ | \--* LCL_VAR long V03 loc0
[000042] ---XG+------ /--* ADD int
[000131] ---XG+------ | | /--* CAST int <- long
[000031] ---XG+------ | | | \--* HWIntrinsic long PopCount
[000030] *--XG+------ | | | \--* IND long
[000027] -----+------ | | | | /--* CAST long <- int
[000026] -----+------ | | | | | \--* CNS_INT int 8
[000028] -----+------ | | | | /--* MUL long
[000025] -----+------ | | | | | \--* CAST long <- int
[000024] -----+------ | | | | | \--* CNS_INT int 2
[000029] -----+------ | | | \--* ADD long
[000023] -----+------ | | | \--* LCL_VAR long V03 loc0
[000032] ---XG+------ | \--* ADD int
[000133] ---XG+------ | | /--* CAST int <- long
[000021] ---XG+------ | | | \--* HWIntrinsic long PopCount
[000020] *--XG+------ | | | \--* IND long
[000018] -----+------ | | | | /--* CAST long <- int
[000017] -----+------ | | | | | \--* CNS_INT int 8
[000019] -----+------ | | | \--* ADD long
[000016] -----+------ | | | \--* LCL_VAR long V03 loc0
[000022] ---XG+------ | \--* ADD int
[000132] ---XG+------ | \--* CAST int <- long
[000015] ---XG+------ | \--* HWIntrinsic long PopCount
[000014] *--XG+------ | \--* IND long
[000013] -----+------ | \--* LCL_VAR long V03 loc0
[000044] ---XG+------ /--* SUB int
[000012] -----+------ | \--* LCL_VAR int V02 arg2
[000046] -A-XG+------ * ASG int
[000045] D----+-N---- \--* LCL_VAR int V02 arg2
fgMorphTree BB02, stmt 3 (before)
[000052] ------------ /--* CAST long <- int
[000051] ------------ | \--* CNS_INT int 8
[000053] ------------ /--* MUL long
[000050] ------------ | \--* CAST long <- int
[000049] ------------ | \--* CNS_INT int 4
[000054] ------------ /--* ADD long
[000048] ------------ | \--* LCL_VAR long V03 loc0
[000056] -A---------- * ASG long
[000055] D------N---- \--* LCL_VAR long V03 loc0
Morphing BB03 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB03, stmt 4 (before)
[000009] ------------ * JTRUE void
[000007] ------------ | /--* CNS_INT int 256
[000008] ------------ \--* GE int
[000006] ------------ \--* LCL_VAR int V02 arg2
Morphing BB04 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB04, stmt 5 (before)
[000059] ------------ /--* LCL_VAR int V02 arg2
[000061] -A---------- * ASG int
[000060] D------N---- \--* LCL_VAR int V04 loc1
Morphing BB05 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB05, stmt 6 (before)
[000070] ------------ /--* LCL_VAR int V02 arg2
[000072] -A---------- * ASG int
[000071] D------N---- \--* LCL_VAR int V04 loc1
fgMorphTree BB05, stmt 7 (before)
[000078] ---XG------- /--* CAST int <- long
[000077] ---XG------- | \--* HWIntrinsic long PopCount
[000076] *--XG------- | \--* IND long
[000075] ------------ | \--* LCL_VAR long V03 loc0
[000079] ---XG------- /--* SUB int
[000074] ------------ | \--* LCL_VAR int V02 arg2
[000081] -A-XG------- * ASG int
[000080] D------N---- \--* LCL_VAR int V02 arg2
fgMorphTree BB05, stmt 8 (before)
[000085] ------------ /--* CAST long <- int
[000084] ------------ | \--* CNS_INT int 8
[000086] ------------ /--* ADD long
[000083] ------------ | \--* LCL_VAR long V03 loc0
[000088] -A---------- * ASG long
[000087] D------N---- \--* LCL_VAR long V03 loc0
Morphing BB06 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB06, stmt 9 (before)
[000067] ------------ * JTRUE void
[000065] ------------ | /--* CNS_INT int 0
[000066] ------------ \--* GT int
[000064] ------------ \--* LCL_VAR int V02 arg2
Morphing BB07 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB07, stmt 10 (before)
[000093] ------------ /--* CAST long <- int
[000092] ------------ | \--* CNS_INT int 8
[000094] ------------ /--* SUB long
[000091] ------------ | \--* LCL_VAR long V03 loc0
[000096] -A---------- * ASG long
[000095] D------N---- \--* LCL_VAR long V03 loc0
fgMorphTree BB07, stmt 11 (before)
[000110] ---XG------- /--* CAST int <- long
[000109] ---XG------- | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG------- | | /--* IND long
[000106] ------------ | | | \--* LCL_VAR long V03 loc0
[000108] ---XG------- | \--* HWIntrinsic long ParallelBitDeposit
[000103] ------------ | | /--* CNS_INT int 63
[000104] ------------ | | /--* AND int
[000101] ------------ | | | | /--* CNS_INT int 1
[000102] ------------ | | | \--* SUB int
[000100] ------------ | | | \--* LCL_VAR int V04 loc1
[000105] ------------ | \--* LSH long
[000099] ------------ | \--* CAST long <- int
[000098] ------------ | \--* CNS_INT int 1
[000112] -A-XG------- * ASG int
[000111] D------N---- \--* LCL_VAR int V05 loc2
fgMorphTree BB07, stmt 11 (after)
[000110] ---XG+------ /--* CAST int <- long
[000109] ---XG+------ | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG+------ | | /--* IND long
[000106] -----+------ | | | \--* LCL_VAR long V03 loc0
[000108] ---XG+------ | \--* HWIntrinsic long ParallelBitDeposit
[000103] -----+------ | | /--* CNS_INT int 63
[000104] -----+------ | | /--* AND int
[000101] -----+------ | | | | /--* CNS_INT int -1
[000102] -----+------ | | | \--* ADD int
[000100] -----+------ | | | \--* LCL_VAR int V04 loc1
[000105] -----+------ | \--* LSH long
[000099] -----+------ | \--* CAST long <- int
[000098] -----+------ | \--* CNS_INT int 1
[000112] -A-XG+------ * ASG int
[000111] D----+-N---- \--* LCL_VAR int V05 loc2
fgMorphTree BB07, stmt 12 (before)
[000126] ---X-------- * RETURN int
[000124] ------------ | /--* LCL_VAR int V05 loc2
[000125] ---X-------- \--* ADD int
[000123] ---X-------- \--* CAST int <- long
[000121] ------------ | /--* CAST long <- int
[000120] ------------ | | \--* CNS_INT int 64
[000122] ---X-------- \--* MUL long
[000118] ------------ | /--* CAST long <- int
[000117] ------------ | | \--* CNS_INT int 8
[000119] ---X-------- \--* DIV long
[000115] ------------ | /--* LCL_VAR long V00 arg0
[000116] ------------ \--* SUB long
[000114] ------------ \--* LCL_VAR long V03 loc0
fgMorphTree BB07, stmt 12 (after)
[000126] ---X-+------ * RETURN int
[000124] -----+------ | /--* LCL_VAR int V05 loc2
[000125] ---X-+------ \--* ADD int
[000121] -----+------ | /--* NOP int
[000120] -----+------ | | \--* CNS_INT int 64
[000122] ---X-+------ \--* MUL int
[000134] ---X-+------ \--* CAST int <- long
[000118] -----+------ | /--* CAST long <- int
[000117] -----+------ | | \--* CNS_INT int 8
[000119] ---X-+------ \--* DIV long
[000115] -----+------ | /--* LCL_VAR long V00 arg0
[000116] -----+------ \--* SUB long
[000114] -----+------ \--* LCL_VAR long V03 loc0
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i
BB02 [0001] 1 1 [004..03B) i bwd
BB03 [0002] 2 1 [03B..043)-> BB02 ( cond ) i bwd
BB04 [0003] 1 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 1 [047..059) i bwd
BB06 [0005] 2 1 [059..05D)-> BB05 ( cond ) i bwd
BB07 [0006] 1 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i
BB02 [0001] 1 1 [004..03B) i bwd
BB03 [0002] 2 1 [03B..043)-> BB02 ( cond ) i bwd
BB04 [0003] 1 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 1 [047..059) i bwd
BB06 [0005] 2 1 [059..05D)-> BB05 ( cond ) i bwd
BB07 [0006] 1 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeBlockAndEdgeWeights()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing, so not computing edge weights
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
***** BB01, stmt 1
[000004] ------------ * STMT void (IL 0x000...0x001)
[000001] -----+------ | /--* LCL_VAR long V00 arg0
[000003] -A---+------ \--* ASG long
[000002] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
***** BB02, stmt 2
[000047] ------------ * STMT void (IL 0x004...0x032)
[000129] ---XG+------ | /--* CAST int <- long
[000041] ---XG+------ | | \--* HWIntrinsic long PopCount
[000040] *--XG+------ | | \--* IND long
[000037] -----+------ | | | /--* CAST long <- int
[000036] -----+------ | | | | \--* CNS_INT int 8
[000038] -----+------ | | | /--* MUL long
[000035] -----+------ | | | | \--* CAST long <- int
[000034] -----+------ | | | | \--* CNS_INT int 3
[000039] -----+------ | | \--* ADD long
[000033] -----+------ | | \--* LCL_VAR long V03 loc0
[000042] ---XG+------ | /--* ADD int
[000131] ---XG+------ | | | /--* CAST int <- long
[000031] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000030] *--XG+------ | | | | \--* IND long
[000027] -----+------ | | | | | /--* CAST long <- int
[000026] -----+------ | | | | | | \--* CNS_INT int 8
[000028] -----+------ | | | | | /--* MUL long
[000025] -----+------ | | | | | | \--* CAST long <- int
[000024] -----+------ | | | | | | \--* CNS_INT int 2
[000029] -----+------ | | | | \--* ADD long
[000023] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000032] ---XG+------ | | \--* ADD int
[000133] ---XG+------ | | | /--* CAST int <- long
[000021] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000020] *--XG+------ | | | | \--* IND long
[000018] -----+------ | | | | | /--* CAST long <- int
[000017] -----+------ | | | | | | \--* CNS_INT int 8
[000019] -----+------ | | | | \--* ADD long
[000016] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000022] ---XG+------ | | \--* ADD int
[000132] ---XG+------ | | \--* CAST int <- long
[000015] ---XG+------ | | \--* HWIntrinsic long PopCount
[000014] *--XG+------ | | \--* IND long
[000013] -----+------ | | \--* LCL_VAR long V03 loc0
[000044] ---XG+------ | /--* SUB int
[000012] -----+------ | | \--* LCL_VAR int V02 arg2
[000046] -A-XG+------ \--* ASG int
[000045] D----+-N---- \--* LCL_VAR int V02 arg2
***** BB02, stmt 3
[000057] ------------ * STMT void (IL 0x034...0x03A)
[000052] -----+------ | /--* CAST long <- int
[000051] -----+------ | | \--* CNS_INT int 8
[000053] -----+------ | /--* MUL long
[000050] -----+------ | | \--* CAST long <- int
[000049] -----+------ | | \--* CNS_INT int 4
[000054] -----+------ | /--* ADD long
[000048] -----+------ | | \--* LCL_VAR long V03 loc0
[000056] -A---+------ \--* ASG long
[000055] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
***** BB03, stmt 4
[000010] ------------ * STMT void (IL 0x03B...0x041)
[000009] -----+------ \--* JTRUE void
[000007] -----+------ | /--* CNS_INT int 256
[000008] J----+-N---- \--* GE int
[000006] -----+------ \--* LCL_VAR int V02 arg2
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
***** BB04, stmt 5
[000062] ------------ * STMT void (IL 0x043...0x044)
[000059] -----+------ | /--* LCL_VAR int V02 arg2
[000061] -A---+------ \--* ASG int
[000060] D----+-N---- \--* LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
***** BB05, stmt 6
[000073] ------------ * STMT void (IL 0x047...0x048)
[000070] -----+------ | /--* LCL_VAR int V02 arg2
[000072] -A---+------ \--* ASG int
[000071] D----+-N---- \--* LCL_VAR int V04 loc1
***** BB05, stmt 7
[000082] ------------ * STMT void (IL 0x049...0x053)
[000078] ---XG+------ | /--* CAST int <- long
[000077] ---XG+------ | | \--* HWIntrinsic long PopCount
[000076] *--XG+------ | | \--* IND long
[000075] -----+------ | | \--* LCL_VAR long V03 loc0
[000079] ---XG+------ | /--* SUB int
[000074] -----+------ | | \--* LCL_VAR int V02 arg2
[000081] -A-XG+------ \--* ASG int
[000080] D----+-N---- \--* LCL_VAR int V02 arg2
***** BB05, stmt 8
[000089] ------------ * STMT void (IL 0x055...0x058)
[000085] -----+------ | /--* CAST long <- int
[000084] -----+------ | | \--* CNS_INT int 8
[000086] -----+------ | /--* ADD long
[000083] -----+------ | | \--* LCL_VAR long V03 loc0
[000088] -A---+------ \--* ASG long
[000087] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
***** BB06, stmt 9
[000068] ------------ * STMT void (IL 0x059...0x05B)
[000067] -----+------ \--* JTRUE void
[000065] -----+------ | /--* CNS_INT int 0
[000066] J----+-N---- \--* GT int
[000064] -----+------ \--* LCL_VAR int V02 arg2
------------ BB07 [05D..086) (return), preds={BB06} succs={}
***** BB07, stmt 10
[000097] ------------ * STMT void (IL 0x05D...0x060)
[000093] -----+------ | /--* CAST long <- int
[000092] -----+------ | | \--* CNS_INT int 8
[000094] -----+------ | /--* SUB long
[000091] -----+------ | | \--* LCL_VAR long V03 loc0
[000096] -A---+------ \--* ASG long
[000095] D----+-N---- \--* LCL_VAR long V03 loc0
***** BB07, stmt 11
[000113] ------------ * STMT void (IL 0x061...0x077)
[000110] ---XG+------ | /--* CAST int <- long
[000109] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG+------ | | | /--* IND long
[000106] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000108] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000103] -----+------ | | | /--* CNS_INT int 63
[000104] -----+------ | | | /--* AND int
[000101] -----+------ | | | | | /--* CNS_INT int -1
[000102] -----+------ | | | | \--* ADD int
[000100] -----+------ | | | | \--* LCL_VAR int V04 loc1
[000105] -----+------ | | \--* LSH long
[000099] -----+------ | | \--* CAST long <- int
[000098] -----+------ | | \--* CNS_INT int 1
[000112] -A-XG+------ \--* ASG int
[000111] D----+-N---- \--* LCL_VAR int V05 loc2
***** BB07, stmt 12
[000127] ------------ * STMT void (IL 0x078...0x085)
[000126] ---X-+------ \--* RETURN int
[000124] -----+------ | /--* LCL_VAR int V05 loc2
[000125] ---X-+------ \--* ADD int
[000121] -----+------ | /--* NOP int
[000120] -----+------ | | \--* CNS_INT int 64
[000122] ---X-+------ \--* MUL int
[000134] ---X-+------ \--* CAST int <- long
[000118] -----+------ | /--* CAST long <- int
[000117] -----+------ | | \--* CNS_INT int 8
[000119] ---X-+------ \--* DIV long
[000115] -----+------ | /--* LCL_VAR long V00 arg0
[000116] -----+------ \--* SUB long
[000114] -----+------ \--* LCL_VAR long V03 loc0
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
***** BB01, stmt 1
[000004] ------------ * STMT void (IL 0x000...0x001)
[000001] -----+------ | /--* LCL_VAR long V00 arg0
[000003] -A---+------ \--* ASG long
[000002] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
***** BB02, stmt 2
[000047] ------------ * STMT void (IL 0x004...0x032)
[000129] ---XG+------ | /--* CAST int <- long
[000041] ---XG+------ | | \--* HWIntrinsic long PopCount
[000040] *--XG+------ | | \--* IND long
[000037] -----+------ | | | /--* CAST long <- int
[000036] -----+------ | | | | \--* CNS_INT int 8
[000038] -----+------ | | | /--* MUL long
[000035] -----+------ | | | | \--* CAST long <- int
[000034] -----+------ | | | | \--* CNS_INT int 3
[000039] -----+------ | | \--* ADD long
[000033] -----+------ | | \--* LCL_VAR long V03 loc0
[000042] ---XG+------ | /--* ADD int
[000131] ---XG+------ | | | /--* CAST int <- long
[000031] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000030] *--XG+------ | | | | \--* IND long
[000027] -----+------ | | | | | /--* CAST long <- int
[000026] -----+------ | | | | | | \--* CNS_INT int 8
[000028] -----+------ | | | | | /--* MUL long
[000025] -----+------ | | | | | | \--* CAST long <- int
[000024] -----+------ | | | | | | \--* CNS_INT int 2
[000029] -----+------ | | | | \--* ADD long
[000023] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000032] ---XG+------ | | \--* ADD int
[000133] ---XG+------ | | | /--* CAST int <- long
[000021] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000020] *--XG+------ | | | | \--* IND long
[000018] -----+------ | | | | | /--* CAST long <- int
[000017] -----+------ | | | | | | \--* CNS_INT int 8
[000019] -----+------ | | | | \--* ADD long
[000016] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000022] ---XG+------ | | \--* ADD int
[000132] ---XG+------ | | \--* CAST int <- long
[000015] ---XG+------ | | \--* HWIntrinsic long PopCount
[000014] *--XG+------ | | \--* IND long
[000013] -----+------ | | \--* LCL_VAR long V03 loc0
[000044] ---XG+------ | /--* SUB int
[000012] -----+------ | | \--* LCL_VAR int V02 arg2
[000046] -A-XG+------ \--* ASG int
[000045] D----+-N---- \--* LCL_VAR int V02 arg2
***** BB02, stmt 3
[000057] ------------ * STMT void (IL 0x034...0x03A)
[000052] -----+------ | /--* CAST long <- int
[000051] -----+------ | | \--* CNS_INT int 8
[000053] -----+------ | /--* MUL long
[000050] -----+------ | | \--* CAST long <- int
[000049] -----+------ | | \--* CNS_INT int 4
[000054] -----+------ | /--* ADD long
[000048] -----+------ | | \--* LCL_VAR long V03 loc0
[000056] -A---+------ \--* ASG long
[000055] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
***** BB03, stmt 4
[000010] ------------ * STMT void (IL 0x03B...0x041)
[000009] -----+------ \--* JTRUE void
[000007] -----+------ | /--* CNS_INT int 256
[000008] J----+-N---- \--* GE int
[000006] -----+------ \--* LCL_VAR int V02 arg2
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
***** BB04, stmt 5
[000062] ------------ * STMT void (IL 0x043...0x044)
[000059] -----+------ | /--* LCL_VAR int V02 arg2
[000061] -A---+------ \--* ASG int
[000060] D----+-N---- \--* LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
***** BB05, stmt 6
[000073] ------------ * STMT void (IL 0x047...0x048)
[000070] -----+------ | /--* LCL_VAR int V02 arg2
[000072] -A---+------ \--* ASG int
[000071] D----+-N---- \--* LCL_VAR int V04 loc1
***** BB05, stmt 7
[000082] ------------ * STMT void (IL 0x049...0x053)
[000078] ---XG+------ | /--* CAST int <- long
[000077] ---XG+------ | | \--* HWIntrinsic long PopCount
[000076] *--XG+------ | | \--* IND long
[000075] -----+------ | | \--* LCL_VAR long V03 loc0
[000079] ---XG+------ | /--* SUB int
[000074] -----+------ | | \--* LCL_VAR int V02 arg2
[000081] -A-XG+------ \--* ASG int
[000080] D----+-N---- \--* LCL_VAR int V02 arg2
***** BB05, stmt 8
[000089] ------------ * STMT void (IL 0x055...0x058)
[000085] -----+------ | /--* CAST long <- int
[000084] -----+------ | | \--* CNS_INT int 8
[000086] -----+------ | /--* ADD long
[000083] -----+------ | | \--* LCL_VAR long V03 loc0
[000088] -A---+------ \--* ASG long
[000087] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
***** BB06, stmt 9
[000068] ------------ * STMT void (IL 0x059...0x05B)
[000067] -----+------ \--* JTRUE void
[000065] -----+------ | /--* CNS_INT int 0
[000066] J----+-N---- \--* GT int
[000064] -----+------ \--* LCL_VAR int V02 arg2
------------ BB07 [05D..086) (return), preds={BB06} succs={}
***** BB07, stmt 10
[000097] ------------ * STMT void (IL 0x05D...0x060)
[000093] -----+------ | /--* CAST long <- int
[000092] -----+------ | | \--* CNS_INT int 8
[000094] -----+------ | /--* SUB long
[000091] -----+------ | | \--* LCL_VAR long V03 loc0
[000096] -A---+------ \--* ASG long
[000095] D----+-N---- \--* LCL_VAR long V03 loc0
***** BB07, stmt 11
[000113] ------------ * STMT void (IL 0x061...0x077)
[000110] ---XG+------ | /--* CAST int <- long
[000109] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG+------ | | | /--* IND long
[000106] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000108] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000103] -----+------ | | | /--* CNS_INT int 63
[000104] -----+------ | | | /--* AND int
[000101] -----+------ | | | | | /--* CNS_INT int -1
[000102] -----+------ | | | | \--* ADD int
[000100] -----+------ | | | | \--* LCL_VAR int V04 loc1
[000105] -----+------ | | \--* LSH long
[000099] -----+------ | | \--* CAST long <- int
[000098] -----+------ | | \--* CNS_INT int 1
[000112] -A-XG+------ \--* ASG int
[000111] D----+-N---- \--* LCL_VAR int V05 loc2
***** BB07, stmt 12
[000127] ------------ * STMT void (IL 0x078...0x085)
[000126] ---X-+------ \--* RETURN int
[000124] -----+------ | /--* LCL_VAR int V05 loc2
[000125] ---X-+------ \--* ADD int
[000121] -----+------ | /--* NOP int
[000120] -----+------ | | \--* CNS_INT int 64
[000122] ---X-+------ \--* MUL int
[000134] ---X-+------ \--* CAST int <- long
[000118] -----+------ | /--* CAST long <- int
[000117] -----+------ | | \--* CNS_INT int 8
[000119] ---X-+------ \--* DIV long
[000115] -----+------ | /--* LCL_VAR long V00 arg0
[000116] -----+------ \--* SUB long
[000114] -----+------ \--* LCL_VAR long V03 loc0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 38 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
***** BB01, stmt 1
( 7, 5) [000004] ------------ * STMT void (IL 0x000...0x001)
N001 ( 3, 2) [000001] ------------ | /--* LCL_VAR long V00 arg0
N003 ( 7, 5) [000003] -A------R--- \--* ASG long
N002 ( 3, 2) [000002] D------N---- \--* LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
***** BB02, stmt 2
( 61, 58) [000047] ------------ * STMT void (IL 0x004...0x032)
N033 ( 16, 16) [000129] ---XG------- | /--* CAST int <- long
N032 ( 15, 14) [000041] ---XG------- | | \--* HWIntrinsic long PopCount
N031 ( 14, 13) [000040] *--XG------- | | \--* IND long
N028 ( 2, 3) [000037] ------------ | | | /--* CAST long <- int
N027 ( 1, 1) [000036] ------------ | | | | \--* CNS_INT int 8
N029 ( 8, 9) [000038] ------------ | | | /--* MUL long
N026 ( 2, 3) [000035] ------------ | | | | \--* CAST long <- int
N025 ( 1, 1) [000034] ------------ | | | | \--* CNS_INT int 3
N030 ( 11, 11) [000039] -------N---- | | \--* ADD long
N024 ( 3, 2) [000033] ------------ | | \--* LCL_VAR long V03 loc0
N034 ( 53, 52) [000042] ---XG------- | /--* ADD int
N022 ( 16, 16) [000131] ---XG------- | | | /--* CAST int <- long
N021 ( 15, 14) [000031] ---XG------- | | | | \--* HWIntrinsic long PopCount
N020 ( 14, 13) [000030] *--XG------- | | | | \--* IND long
N017 ( 2, 3) [000027] ------------ | | | | | /--* CAST long <- int
N016 ( 1, 1) [000026] ------------ | | | | | | \--* CNS_INT int 8
N018 ( 8, 9) [000028] ------------ | | | | | /--* MUL long
N015 ( 2, 3) [000025] ------------ | | | | | | \--* CAST long <- int
N014 ( 1, 1) [000024] ------------ | | | | | | \--* CNS_INT int 2
N019 ( 11, 11) [000029] -------N---- | | | | \--* ADD long
N013 ( 3, 2) [000023] ------------ | | | | \--* LCL_VAR long V03 loc0
N023 ( 36, 35) [000032] ---XG------- | | \--* ADD int
N011 ( 10, 10) [000133] ---XG------- | | | /--* CAST int <- long
N010 ( 9, 8) [000021] ---XG------- | | | | \--* HWIntrinsic long PopCount
N009 ( 8, 7) [000020] *--XG------- | | | | \--* IND long
N007 ( 2, 3) [000018] ------------ | | | | | /--* CAST long <- int
N006 ( 1, 1) [000017] ------------ | | | | | | \--* CNS_INT int 8
N008 ( 5, 5) [000019] -------N---- | | | | \--* ADD long
N005 ( 3, 2) [000016] ------------ | | | | \--* LCL_VAR long V03 loc0
N012 ( 19, 18) [000022] ---XG------- | | \--* ADD int
N004 ( 8, 7) [000132] ---XG------- | | \--* CAST int <- long
N003 ( 7, 5) [000015] ---XG------- | | \--* HWIntrinsic long PopCount
N002 ( 6, 4) [000014] *--XG------- | | \--* IND long
N001 ( 3, 2) [000013] ------------ | | \--* LCL_VAR long V03 loc0
N036 ( 57, 55) [000044] ---XG---R--- | /--* SUB int
N035 ( 3, 2) [000012] ------------ | | \--* LCL_VAR int V02 arg2
N038 ( 61, 58) [000046] -A-XG---R--- \--* ASG int
N037 ( 3, 2) [000045] D------N---- \--* LCL_VAR int V02 arg2
***** BB02, stmt 3
( 16, 15) [000057] ------------ * STMT void (IL 0x034...0x03A)
N005 ( 2, 3) [000052] ------------ | /--* CAST long <- int
N004 ( 1, 1) [000051] ------------ | | \--* CNS_INT int 8
N006 ( 8, 9) [000053] ------------ | /--* MUL long
N003 ( 2, 3) [000050] ------------ | | \--* CAST long <- int
N002 ( 1, 1) [000049] ------------ | | \--* CNS_INT int 4
N007 ( 12, 12) [000054] ------------ | /--* ADD long
N001 ( 3, 2) [000048] ------------ | | \--* LCL_VAR long V03 loc0
N009 ( 16, 15) [000056] -A------R--- \--* ASG long
N008 ( 3, 2) [000055] D------N---- \--* LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
***** BB03, stmt 4
( 7, 9) [000010] ------------ * STMT void (IL 0x03B...0x041)
N004 ( 7, 9) [000009] ------------ \--* JTRUE void
N002 ( 1, 4) [000007] ------------ | /--* CNS_INT int 256
N003 ( 5, 7) [000008] J------N---- \--* GE int
N001 ( 3, 2) [000006] ------------ \--* LCL_VAR int V02 arg2
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
***** BB04, stmt 5
( 7, 5) [000062] ------------ * STMT void (IL 0x043...0x044)
N001 ( 3, 2) [000059] ------------ | /--* LCL_VAR int V02 arg2
N003 ( 7, 5) [000061] -A------R--- \--* ASG int
N002 ( 3, 2) [000060] D------N---- \--* LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
***** BB05, stmt 6
( 7, 5) [000073] ------------ * STMT void (IL 0x047...0x048)
N001 ( 3, 2) [000070] ------------ | /--* LCL_VAR int V02 arg2
N003 ( 7, 5) [000072] -A------R--- \--* ASG int
N002 ( 3, 2) [000071] D------N---- \--* LCL_VAR int V04 loc1
***** BB05, stmt 7
( 16, 13) [000082] ------------ * STMT void (IL 0x049...0x053)
N005 ( 8, 7) [000078] ---XG------- | /--* CAST int <- long
N004 ( 7, 5) [000077] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 6, 4) [000076] *--XG------- | | \--* IND long
N002 ( 3, 2) [000075] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 12, 10) [000079] ---XG------- | /--* SUB int
N001 ( 3, 2) [000074] ------------ | | \--* LCL_VAR int V02 arg2
N008 ( 16, 13) [000081] -A-XG---R--- \--* ASG int
N007 ( 3, 2) [000080] D------N---- \--* LCL_VAR int V02 arg2
***** BB05, stmt 8
( 10, 9) [000089] ------------ * STMT void (IL 0x055...0x058)
N003 ( 2, 3) [000085] ------------ | /--* CAST long <- int
N002 ( 1, 1) [000084] ------------ | | \--* CNS_INT int 8
N004 ( 6, 6) [000086] ------------ | /--* ADD long
N001 ( 3, 2) [000083] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 10, 9) [000088] -A------R--- \--* ASG long
N005 ( 3, 2) [000087] D------N---- \--* LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
***** BB06, stmt 9
( 7, 6) [000068] ------------ * STMT void (IL 0x059...0x05B)
N004 ( 7, 6) [000067] ------------ \--* JTRUE void
N002 ( 1, 1) [000065] ------------ | /--* CNS_INT int 0
N003 ( 5, 4) [000066] J------N---- \--* GT int
N001 ( 3, 2) [000064] ------------ \--* LCL_VAR int V02 arg2
------------ BB07 [05D..086) (return), preds={BB06} succs={}
***** BB07, stmt 10
( 10, 9) [000097] ------------ * STMT void (IL 0x05D...0x060)
N003 ( 2, 3) [000093] ------------ | /--* CAST long <- int
N002 ( 1, 1) [000092] ------------ | | \--* CNS_INT int 8
N004 ( 6, 6) [000094] ------------ | /--* SUB long
N001 ( 3, 2) [000091] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 10, 9) [000096] -A------R--- \--* ASG long
N005 ( 3, 2) [000095] D------N---- \--* LCL_VAR long V03 loc0
***** BB07, stmt 11
( 26, 21) [000113] ------------ * STMT void (IL 0x061...0x077)
N013 ( 22, 18) [000110] ---XG------- | /--* CAST int <- long
N012 ( 21, 16) [000109] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
N010 ( 6, 4) [000107] *--XG------- | | | /--* IND long
N009 ( 3, 2) [000106] ------------ | | | | \--* LCL_VAR long V03 loc0
N011 ( 20, 15) [000108] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000103] ------------ | | | /--* CNS_INT int 63
N005 ( 7, 6) [000104] ------------ | | | /--* AND int
N002 ( 1, 1) [000101] ------------ | | | | | /--* CNS_INT int -1
N003 ( 5, 4) [000102] ------------ | | | | \--* ADD int
N001 ( 3, 2) [000100] ------------ | | | | \--* LCL_VAR int V04 loc1
N008 ( 13, 10) [000105] --------R--- | | \--* LSH long
N007 ( 2, 3) [000099] ------------ | | \--* CAST long <- int
N006 ( 1, 1) [000098] ------------ | | \--* CNS_INT int 1
N015 ( 26, 21) [000112] -A-XG---R--- \--* ASG int
N014 ( 3, 2) [000111] D------N---- \--* LCL_VAR int V05 loc2
***** BB07, stmt 12
( 40, 21) [000127] ------------ * STMT void (IL 0x078...0x085)
N013 ( 40, 21) [000126] ---X-------- \--* RETURN int
N011 ( 3, 2) [000124] ------------ | /--* LCL_VAR int V05 loc2
N012 ( 39, 20) [000125] ---X-------- \--* ADD int
N009 ( 1, 1) [000121] ------------ | /--* NOP int
N008 ( 1, 1) [000120] ------------ | | \--* CNS_INT int 64
N010 ( 35, 17) [000122] ---X-------- \--* MUL int
N007 ( 30, 13) [000134] ---X-------- \--* CAST int <- long
N005 ( 2, 3) [000118] ------------ | /--* CAST long <- int
N004 ( 1, 1) [000117] ------------ | | \--* CNS_INT int 8
N006 ( 29, 11) [000119] ---X-------- \--* DIV long
N002 ( 3, 2) [000115] ------------ | /--* LCL_VAR long V00 arg0
N003 ( 7, 5) [000116] ------------ \--* SUB long
N001 ( 3, 2) [000114] ------------ \--* LCL_VAR long V03 loc0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
***** BB01, stmt 1
( 7, 5) [000004] ------------ * STMT void (IL 0x000...0x001)
N001 ( 3, 2) [000001] ------------ | /--* LCL_VAR long V00 arg0
N003 ( 7, 5) [000003] -A------R--- \--* ASG long
N002 ( 3, 2) [000002] D------N---- \--* LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
***** BB02, stmt 2
( 61, 58) [000047] ------------ * STMT void (IL 0x004...0x032)
N033 ( 16, 16) [000129] ---XG------- | /--* CAST int <- long
N032 ( 15, 14) [000041] ---XG------- | | \--* HWIntrinsic long PopCount
N031 ( 14, 13) [000040] *--XG------- | | \--* IND long
N028 ( 2, 3) [000037] ------------ | | | /--* CAST long <- int
N027 ( 1, 1) [000036] ------------ | | | | \--* CNS_INT int 8
N029 ( 8, 9) [000038] ------------ | | | /--* MUL long
N026 ( 2, 3) [000035] ------------ | | | | \--* CAST long <- int
N025 ( 1, 1) [000034] ------------ | | | | \--* CNS_INT int 3
N030 ( 11, 11) [000039] -------N---- | | \--* ADD long
N024 ( 3, 2) [000033] ------------ | | \--* LCL_VAR long V03 loc0
N034 ( 53, 52) [000042] ---XG------- | /--* ADD int
N022 ( 16, 16) [000131] ---XG------- | | | /--* CAST int <- long
N021 ( 15, 14) [000031] ---XG------- | | | | \--* HWIntrinsic long PopCount
N020 ( 14, 13) [000030] *--XG------- | | | | \--* IND long
N017 ( 2, 3) [000027] ------------ | | | | | /--* CAST long <- int
N016 ( 1, 1) [000026] ------------ | | | | | | \--* CNS_INT int 8
N018 ( 8, 9) [000028] ------------ | | | | | /--* MUL long
N015 ( 2, 3) [000025] ------------ | | | | | | \--* CAST long <- int
N014 ( 1, 1) [000024] ------------ | | | | | | \--* CNS_INT int 2
N019 ( 11, 11) [000029] -------N---- | | | | \--* ADD long
N013 ( 3, 2) [000023] ------------ | | | | \--* LCL_VAR long V03 loc0
N023 ( 36, 35) [000032] ---XG------- | | \--* ADD int
N011 ( 10, 10) [000133] ---XG------- | | | /--* CAST int <- long
N010 ( 9, 8) [000021] ---XG------- | | | | \--* HWIntrinsic long PopCount
N009 ( 8, 7) [000020] *--XG------- | | | | \--* IND long
N007 ( 2, 3) [000018] ------------ | | | | | /--* CAST long <- int
N006 ( 1, 1) [000017] ------------ | | | | | | \--* CNS_INT int 8
N008 ( 5, 5) [000019] -------N---- | | | | \--* ADD long
N005 ( 3, 2) [000016] ------------ | | | | \--* LCL_VAR long V03 loc0
N012 ( 19, 18) [000022] ---XG------- | | \--* ADD int
N004 ( 8, 7) [000132] ---XG------- | | \--* CAST int <- long
N003 ( 7, 5) [000015] ---XG------- | | \--* HWIntrinsic long PopCount
N002 ( 6, 4) [000014] *--XG------- | | \--* IND long
N001 ( 3, 2) [000013] ------------ | | \--* LCL_VAR long V03 loc0
N036 ( 57, 55) [000044] ---XG---R--- | /--* SUB int
N035 ( 3, 2) [000012] ------------ | | \--* LCL_VAR int V02 arg2
N038 ( 61, 58) [000046] -A-XG---R--- \--* ASG int
N037 ( 3, 2) [000045] D------N---- \--* LCL_VAR int V02 arg2
***** BB02, stmt 3
( 16, 15) [000057] ------------ * STMT void (IL 0x034...0x03A)
N005 ( 2, 3) [000052] ------------ | /--* CAST long <- int
N004 ( 1, 1) [000051] ------------ | | \--* CNS_INT int 8
N006 ( 8, 9) [000053] ------------ | /--* MUL long
N003 ( 2, 3) [000050] ------------ | | \--* CAST long <- int
N002 ( 1, 1) [000049] ------------ | | \--* CNS_INT int 4
N007 ( 12, 12) [000054] ------------ | /--* ADD long
N001 ( 3, 2) [000048] ------------ | | \--* LCL_VAR long V03 loc0
N009 ( 16, 15) [000056] -A------R--- \--* ASG long
N008 ( 3, 2) [000055] D------N---- \--* LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
***** BB03, stmt 4
( 7, 9) [000010] ------------ * STMT void (IL 0x03B...0x041)
N004 ( 7, 9) [000009] ------------ \--* JTRUE void
N002 ( 1, 4) [000007] ------------ | /--* CNS_INT int 256
N003 ( 5, 7) [000008] J------N---- \--* GE int
N001 ( 3, 2) [000006] ------------ \--* LCL_VAR int V02 arg2
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
***** BB04, stmt 5
( 7, 5) [000062] ------------ * STMT void (IL 0x043...0x044)
N001 ( 3, 2) [000059] ------------ | /--* LCL_VAR int V02 arg2
N003 ( 7, 5) [000061] -A------R--- \--* ASG int
N002 ( 3, 2) [000060] D------N---- \--* LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
***** BB05, stmt 6
( 7, 5) [000073] ------------ * STMT void (IL 0x047...0x048)
N001 ( 3, 2) [000070] ------------ | /--* LCL_VAR int V02 arg2
N003 ( 7, 5) [000072] -A------R--- \--* ASG int
N002 ( 3, 2) [000071] D------N---- \--* LCL_VAR int V04 loc1
***** BB05, stmt 7
( 16, 13) [000082] ------------ * STMT void (IL 0x049...0x053)
N005 ( 8, 7) [000078] ---XG------- | /--* CAST int <- long
N004 ( 7, 5) [000077] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 6, 4) [000076] *--XG------- | | \--* IND long
N002 ( 3, 2) [000075] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 12, 10) [000079] ---XG------- | /--* SUB int
N001 ( 3, 2) [000074] ------------ | | \--* LCL_VAR int V02 arg2
N008 ( 16, 13) [000081] -A-XG---R--- \--* ASG int
N007 ( 3, 2) [000080] D------N---- \--* LCL_VAR int V02 arg2
***** BB05, stmt 8
( 10, 9) [000089] ------------ * STMT void (IL 0x055...0x058)
N003 ( 2, 3) [000085] ------------ | /--* CAST long <- int
N002 ( 1, 1) [000084] ------------ | | \--* CNS_INT int 8
N004 ( 6, 6) [000086] ------------ | /--* ADD long
N001 ( 3, 2) [000083] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 10, 9) [000088] -A------R--- \--* ASG long
N005 ( 3, 2) [000087] D------N---- \--* LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
***** BB06, stmt 9
( 7, 6) [000068] ------------ * STMT void (IL 0x059...0x05B)
N004 ( 7, 6) [000067] ------------ \--* JTRUE void
N002 ( 1, 1) [000065] ------------ | /--* CNS_INT int 0
N003 ( 5, 4) [000066] J------N---- \--* GT int
N001 ( 3, 2) [000064] ------------ \--* LCL_VAR int V02 arg2
------------ BB07 [05D..086) (return), preds={BB06} succs={}
***** BB07, stmt 10
( 10, 9) [000097] ------------ * STMT void (IL 0x05D...0x060)
N003 ( 2, 3) [000093] ------------ | /--* CAST long <- int
N002 ( 1, 1) [000092] ------------ | | \--* CNS_INT int 8
N004 ( 6, 6) [000094] ------------ | /--* SUB long
N001 ( 3, 2) [000091] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 10, 9) [000096] -A------R--- \--* ASG long
N005 ( 3, 2) [000095] D------N---- \--* LCL_VAR long V03 loc0
***** BB07, stmt 11
( 26, 21) [000113] ------------ * STMT void (IL 0x061...0x077)
N013 ( 22, 18) [000110] ---XG------- | /--* CAST int <- long
N012 ( 21, 16) [000109] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
N010 ( 6, 4) [000107] *--XG------- | | | /--* IND long
N009 ( 3, 2) [000106] ------------ | | | | \--* LCL_VAR long V03 loc0
N011 ( 20, 15) [000108] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000103] ------------ | | | /--* CNS_INT int 63
N005 ( 7, 6) [000104] ------------ | | | /--* AND int
N002 ( 1, 1) [000101] ------------ | | | | | /--* CNS_INT int -1
N003 ( 5, 4) [000102] ------------ | | | | \--* ADD int
N001 ( 3, 2) [000100] ------------ | | | | \--* LCL_VAR int V04 loc1
N008 ( 13, 10) [000105] --------R--- | | \--* LSH long
N007 ( 2, 3) [000099] ------------ | | \--* CAST long <- int
N006 ( 1, 1) [000098] ------------ | | \--* CNS_INT int 1
N015 ( 26, 21) [000112] -A-XG---R--- \--* ASG int
N014 ( 3, 2) [000111] D------N---- \--* LCL_VAR int V05 loc2
***** BB07, stmt 12
( 40, 21) [000127] ------------ * STMT void (IL 0x078...0x085)
N013 ( 40, 21) [000126] ---X-------- \--* RETURN int
N011 ( 3, 2) [000124] ------------ | /--* LCL_VAR int V05 loc2
N012 ( 39, 20) [000125] ---X-------- \--* ADD int
N009 ( 1, 1) [000121] ------------ | /--* NOP int
N008 ( 1, 1) [000120] ------------ | | \--* CNS_INT int 64
N010 ( 35, 17) [000122] ---X-------- \--* MUL int
N007 ( 30, 13) [000134] ---X-------- \--* CAST int <- long
N005 ( 2, 3) [000118] ------------ | /--* CAST long <- int
N004 ( 1, 1) [000117] ------------ | | \--* CNS_INT int 8
N006 ( 29, 11) [000119] ---X-------- \--* DIV long
N002 ( 3, 2) [000115] ------------ | /--* LCL_VAR long V00 arg0
N003 ( 7, 5) [000116] ------------ \--* SUB long
N001 ( 3, 2) [000114] ------------ \--* LCL_VAR long V03 loc0
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0
/--* t1 long
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4
N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0
/--* t13 long
N002 ( 6, 4) [000014] *--XG------- t14 = * IND long
/--* t14 long
N003 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount
/--* t15 long
N004 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long
N005 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0
N006 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8
/--* t17 int
N007 ( 2, 3) [000018] ------------ t18 = * CAST long <- int
/--* t16 long
+--* t18 long
N008 ( 5, 5) [000019] -------N---- t19 = * ADD long
/--* t19 long
N009 ( 8, 7) [000020] *--XG------- t20 = * IND long
/--* t20 long
N010 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount
/--* t21 long
N011 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long
/--* t132 int
+--* t133 int
N012 ( 19, 18) [000022] ---XG------- t22 = * ADD int
N013 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0
N014 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2
/--* t24 int
N015 ( 2, 3) [000025] ------------ t25 = * CAST long <- int
N016 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8
/--* t26 int
N017 ( 2, 3) [000027] ------------ t27 = * CAST long <- int
/--* t25 long
+--* t27 long
N018 ( 8, 9) [000028] ------------ t28 = * MUL long
/--* t23 long
+--* t28 long
N019 ( 11, 11) [000029] -------N---- t29 = * ADD long
/--* t29 long
N020 ( 14, 13) [000030] *--XG------- t30 = * IND long
/--* t30 long
N021 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount
/--* t31 long
N022 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long
/--* t22 int
+--* t131 int
N023 ( 36, 35) [000032] ---XG------- t32 = * ADD int
N024 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0
N025 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3
/--* t34 int
N026 ( 2, 3) [000035] ------------ t35 = * CAST long <- int
N027 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8
/--* t36 int
N028 ( 2, 3) [000037] ------------ t37 = * CAST long <- int
/--* t35 long
+--* t37 long
N029 ( 8, 9) [000038] ------------ t38 = * MUL long
/--* t33 long
+--* t38 long
N030 ( 11, 11) [000039] -------N---- t39 = * ADD long
/--* t39 long
N031 ( 14, 13) [000040] *--XG------- t40 = * IND long
/--* t40 long
N032 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount
/--* t41 long
N033 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long
/--* t32 int
+--* t129 int
N034 ( 53, 52) [000042] ---XG------- t42 = * ADD int
N035 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2
/--* t12 int
+--* t42 int
N036 ( 57, 55) [000044] ---XG------- t44 = * SUB int
/--* t44 int
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34
N001 ( 3, 2) [000048] ------------ t48 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4
/--* t49 int
N003 ( 2, 3) [000050] ------------ t50 = * CAST long <- int
N004 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8
/--* t51 int
N005 ( 2, 3) [000052] ------------ t52 = * CAST long <- int
/--* t50 long
+--* t52 long
N006 ( 8, 9) [000053] ------------ t53 = * MUL long
/--* t48 long
+--* t53 long
N007 ( 12, 12) [000054] ------------ t54 = * ADD long
/--* t54 long
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b
N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR int V02 arg2
N002 ( 1, 4) [000007] ------------ t7 = CNS_INT int 256
/--* t6 int
+--* t7 int
N003 ( 5, 7) [000008] J------N---- t8 = * GE int
/--* t8 int
N004 ( 7, 9) [000009] ------------ * JTRUE void
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2
/--* t59 int
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2
/--* t70 int
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49
N001 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2
N002 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0
/--* t75 long
N003 ( 6, 4) [000076] *--XG------- t76 = * IND long
/--* t76 long
N004 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount
/--* t77 long
N005 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long
/--* t74 int
+--* t78 int
N006 ( 12, 10) [000079] ---XG------- t79 = * SUB int
/--* t79 int
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55
N001 ( 3, 2) [000083] ------------ t83 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8
/--* t84 int
N003 ( 2, 3) [000085] ------------ t85 = * CAST long <- int
/--* t83 long
+--* t85 long
N004 ( 6, 6) [000086] ------------ t86 = * ADD long
/--* t86 long
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59
N001 ( 3, 2) [000064] ------------ t64 = LCL_VAR int V02 arg2
N002 ( 1, 1) [000065] ------------ t65 = CNS_INT int 0
/--* t64 int
+--* t65 int
N003 ( 5, 4) [000066] J------N---- t66 = * GT int
/--* t66 int
N004 ( 7, 6) [000067] ------------ * JTRUE void
------------ BB07 [05D..086) (return), preds={BB06} succs={}
( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8
/--* t92 int
N003 ( 2, 3) [000093] ------------ t93 = * CAST long <- int
/--* t91 long
+--* t93 long
N004 ( 6, 6) [000094] ------------ t94 = * SUB long
/--* t94 long
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61
N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1
N002 ( 1, 1) [000101] ------------ t101 = CNS_INT int -1
/--* t100 int
+--* t101 int
N003 ( 5, 4) [000102] ------------ t102 = * ADD int
N004 ( 1, 1) [000103] ------------ t103 = CNS_INT int 63
/--* t102 int
+--* t103 int
N005 ( 7, 6) [000104] ------------ t104 = * AND int
N006 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1
/--* t98 int
N007 ( 2, 3) [000099] ------------ t99 = * CAST long <- int
/--* t99 long
+--* t104 int
N008 ( 13, 10) [000105] ------------ t105 = * LSH long
N009 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0
/--* t106 long
N010 ( 6, 4) [000107] *--XG------- t107 = * IND long
/--* t105 long
+--* t107 long
N011 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit
/--* t108 long
N012 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount
/--* t109 long
N013 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long
/--* t110 int
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78
N001 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0
N002 ( 3, 2) [000115] ------------ t115 = LCL_VAR long V00 arg0
/--* t114 long
+--* t115 long
N003 ( 7, 5) [000116] ------------ t116 = * SUB long
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8
/--* t117 int
N005 ( 2, 3) [000118] ------------ t118 = * CAST long <- int
/--* t116 long
+--* t118 long
N006 ( 29, 11) [000119] ---X-------- t119 = * DIV long
/--* t119 long
N007 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long
N008 ( 1, 1) [000120] ------------ t120 = CNS_INT int 64
/--* t134 int
+--* t120 int
N010 ( 35, 17) [000122] ---X-------- t122 = * MUL int
N011 ( 3, 2) [000124] ------------ t124 = LCL_VAR int V05 loc2
/--* t122 int
+--* t124 int
N012 ( 39, 20) [000125] ---X-------- t125 = * ADD int
/--* t125 int
N013 ( 40, 21) [000126] ---X-------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0
/--* t1 long
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4
N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0
/--* t13 long
N002 ( 6, 4) [000014] *--XG------- t14 = * IND long
/--* t14 long
N003 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount
/--* t15 long
N004 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long
N005 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0
N006 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8
/--* t17 int
N007 ( 2, 3) [000018] ------------ t18 = * CAST long <- int
/--* t16 long
+--* t18 long
N008 ( 5, 5) [000019] -------N---- t19 = * ADD long
/--* t19 long
N009 ( 8, 7) [000020] *--XG------- t20 = * IND long
/--* t20 long
N010 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount
/--* t21 long
N011 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long
/--* t132 int
+--* t133 int
N012 ( 19, 18) [000022] ---XG------- t22 = * ADD int
N013 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0
N014 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2
/--* t24 int
N015 ( 2, 3) [000025] ------------ t25 = * CAST long <- int
N016 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8
/--* t26 int
N017 ( 2, 3) [000027] ------------ t27 = * CAST long <- int
/--* t25 long
+--* t27 long
N018 ( 8, 9) [000028] ------------ t28 = * MUL long
/--* t23 long
+--* t28 long
N019 ( 11, 11) [000029] -------N---- t29 = * ADD long
/--* t29 long
N020 ( 14, 13) [000030] *--XG------- t30 = * IND long
/--* t30 long
N021 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount
/--* t31 long
N022 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long
/--* t22 int
+--* t131 int
N023 ( 36, 35) [000032] ---XG------- t32 = * ADD int
N024 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0
N025 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3
/--* t34 int
N026 ( 2, 3) [000035] ------------ t35 = * CAST long <- int
N027 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8
/--* t36 int
N028 ( 2, 3) [000037] ------------ t37 = * CAST long <- int
/--* t35 long
+--* t37 long
N029 ( 8, 9) [000038] ------------ t38 = * MUL long
/--* t33 long
+--* t38 long
N030 ( 11, 11) [000039] -------N---- t39 = * ADD long
/--* t39 long
N031 ( 14, 13) [000040] *--XG------- t40 = * IND long
/--* t40 long