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damageboy/POPCNTAndBMI2Unrolled.fixed.txt

Created September 15, 2018 06:43
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POPCNTAndBMI2Unrolled.fixed.txt
****** START compiling Program:POPCNTAndBMI2Unrolled(int):int (MethodHash=8edbbc1e)
Generating code for Unix x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 7e 03 00 00 04 ldsfld 0x4000003
IL_0005 20 00 04 00 00 ldc.i4 0x400
IL_000a 02 ldarg.0
IL_000b 28 14 00 00 0a call 0xA000014
IL_0010 2a ret
Arg #0 passed in register(s) rdi
lvaGrabTemp returning 1 (V01 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for Program:POPCNTAndBMI2Unrolled(int):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 1
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 011h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for Program:POPCNTAndBMI2Unrolled(int):int
Jump targets:
none
New Basic Block BB01 [0000] created.
BB01 [000..011)
CLFLG_MINOPT set for method Program:POPCNTAndBMI2Unrolled(int):int
IL Code Size,Instr 17, 5, Basic Block count 1, Local Variable Num,Ref count 2, 1 for method Program:POPCNTAndBMI2Unrolled(int):int
IL Code Size,Instr 17, 5, Basic Block count 1, Local Variable Num,Ref count 2, 1 for method Program:POPCNTAndBMI2Unrolled(int):int
OPTIONS: opts.MinOpts() == true
Basic block list for 'Program:POPCNTAndBMI2Unrolled(int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for Program:POPCNTAndBMI2Unrolled(int):int
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'Program:POPCNTAndBMI2Unrolled(int):int'
[ 0] 0 (0x000) ldsfld 04000003
[ 1] 5 (0x005) ldc.i4 1024
[ 2] 10 (0x00a) ldarg.0
[ 3] 11 (0x00b) call 0A000014
In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0
[ 1] 16 (0x010) ret
[000009] ------------ * STMT void (IL 0x000... ???)
[000008] --C-G------- \--* RETURN int
[000004] --C-G------- \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
promotion opt flag not enabled
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'Program:POPCNTAndBMI2Unrolled(int):int'
fgMorphTree BB01, stmt 1 (before)
[000008] --C-G------- * RETURN int
[000004] --C-G------- \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] ----G------- arg0 +--* FIELD long _bits
[000002] ------------ arg1 +--* CNS_INT int 0x400
[000003] ------------ arg2 \--* LCL_VAR int V00 arg0
Morphing args for 4.CALL:
argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0
Sorting the arguments:
Deferred argument ('rdi'):
[000001] x---G+------ * IND long
[000010] -----+------ \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
Replaced with placeholder node:
[000011] ----------L- * ARGPLACE long
Deferred argument ('rdx'):
[000003] -----+------ * LCL_VAR int V00 arg0
Replaced with placeholder node:
[000013] ----------L- * ARGPLACE int
Deferred argument ('rsi'):
[000002] -----+------ * CNS_INT int 0x400
Replaced with placeholder node:
[000015] ----------L- * ARGPLACE int
Shuffled argument table: rdi rdx rsi
fgArgTabEntry[arg 0 1.IND, 1 reg: rdi, align=1, lateArgInx=0, processed]
fgArgTabEntry[arg 2 3.LCL_VAR, 1 reg: rdx, align=1, lateArgInx=1, processed]
fgArgTabEntry[arg 1 2.CNS_INT, 1 reg: rsi, align=1, lateArgInx=2, processed]
fgMorphTree BB01, stmt 1 (after)
[000008] --CXG+------ * RETURN int
[000004] --CXG+------ \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] x---G+------ arg0 in rdi +--* IND long
[000010] -----+------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
[000003] -----+------ arg2 in rdx +--* LCL_VAR int V00 arg0
[000002] -----+------ arg1 in rsi \--* CNS_INT int 0x400
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeBlockAndEdgeWeights()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing, so not computing edge weights
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
***** BB01, stmt 1
[000009] ------------ * STMT void (IL 0x000...0x010)
[000008] --CXG+------ \--* RETURN int
[000004] --CXG+------ \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] x---G+------ arg0 in rdi +--* IND long
[000010] -----+------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
[000003] -----+------ arg2 in rdx +--* LCL_VAR int V00 arg0
[000002] -----+------ arg1 in rsi \--* CNS_INT int 0x400
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
***** BB01, stmt 1
[000009] ------------ * STMT void (IL 0x000...0x010)
[000008] --CXG+------ \--* RETURN int
[000004] --CXG+------ \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
[000001] x---G+------ arg0 in rdi +--* IND long
[000010] -----+------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
[000003] -----+------ arg2 in rdx +--* LCL_VAR int V00 arg0
[000002] -----+------ arg1 in rsi \--* CNS_INT int 0x400
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 15 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
***** BB01, stmt 1
( 24, 27) [000009] ------------ * STMT void (IL 0x000...0x010)
N015 ( 24, 27) [000008] --CXG------- \--* RETURN int
N014 ( 23, 26) [000004] --CXG------- \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
N008 ( 5, 12) [000001] x---G------- arg0 in rdi +--* IND long
N007 ( 3, 10) [000010] ------------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
N009 ( 3, 2) [000003] ------------ arg2 in rdx +--* LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ arg1 in rsi \--* CNS_INT int 0x400
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
***** BB01, stmt 1
( 24, 27) [000009] ------------ * STMT void (IL 0x000...0x010)
N015 ( 24, 27) [000008] --CXG------- \--* RETURN int
N014 ( 23, 26) [000004] --CXG------- \--* CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
N008 ( 5, 12) [000001] x---G------- arg0 in rdi +--* IND long
N007 ( 3, 10) [000010] ------------ | \--* CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
N009 ( 3, 2) [000003] ------------ arg2 in rdx +--* LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ arg1 in rsi \--* CNS_INT int 0x400
-------------------------------------------------------------------------------------------------------------------
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t1 long arg0 in rdi
+--* t3 int arg2 in rdx
+--* t2 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
outgoingArgSpaceSize 0 sufficient for call [000004], which needs 0
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t1 long arg0 in rdi
+--* t3 int arg2 in rdx
+--* t2 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
No addressing mode:
N007 ( 3, 10) [000010] ------------ * CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
lowering call (before):
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t1 long arg0 in rdi
+--* t3 int arg2 in rdx
+--* t2 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
objp:
======
args:
======
lowering arg : N001 ( 0, 0) [000011] ----------L- * ARGPLACE long
lowering arg : N002 ( 0, 0) [000015] ----------L- * ARGPLACE int
lowering arg : N003 ( 0, 0) [000013] ----------L- * ARGPLACE int
late:
======
lowering arg : N008 ( 5, 12) [000001] x---G------- * IND long
new node is : [000017] ----G------- * PUTARG_REG long REG rdi
lowering arg : N009 ( 3, 2) [000003] ------------ * LCL_VAR int V00 arg0
new node is : [000018] ------------ * PUTARG_REG int REG rdx
lowering arg : N010 ( 1, 4) [000002] ------------ * CNS_INT int 0x400
new node is : [000019] ------------ * PUTARG_REG int REG rsi
lowering call (after):
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
lowering GT_RETURN
N015 ( 24, 27) [000008] ---XG------- * RETURN int
============Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 int
; V01 OutArgs lclBlk ( 0)
In fgLocalVarLivenessInit
*************** In fgPerBlockLocalVarLiveness()
*************** In fgInterBlockLocalVarLiveness()
*** lvaComputeRefCounts ***
Liveness pass finished after lowering, IR:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0
N007 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits]
/--* t10 long
N008 ( 5, 12) [000001] x---G------- t1 = * IND long
/--* t1 long
[000017] ----G------- t17 = * PUTARG_REG long REG rdi
N009 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0
/--* t3 int
[000018] ------------ t18 = * PUTARG_REG int REG rdx
N010 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400
/--* t2 int
[000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N014 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N015 ( 24, 27) [000008] ---XG------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{}
{}
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
; Decided to create an EBP based frame for ETW stackwalking (Debug Code)
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 )
BB01 [000..011) (return), preds={} succs={}
=====
N000. IL_OFFSET IL offset: 0x0
N007. t10* = CNS_INT(h) 0x7fec25be4cb8 static Fseq[_bits]
N008. t1 = IND ; t10*
N000. t17 = PUTARG_REG; t1
N009. t3 = V00 MEM
N000. t18 = PUTARG_REG; t3
N010. t2 = CNS_INT 0x400
N000. t19 = PUTARG_REG; t2
N014. t4 = CALL ; t17,t18,t19
N015. RETURN ; t4
buildIntervals second part ========
Int arg V00 in reg rdi
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N002 ( 24, 27) [000009] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N004 ( 3, 10) [000010] ------------ * CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits] REG NA
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N004.t10. CNS_INT }
N006 ( 5, 12) [000001] x---G------- * IND long REG NA
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #3 @7 RefTypeDef <Ivl:1> IND BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N006.t1. IND }
N008 (???,???) [000017] ----G------- * PUTARG_REG long REG rdi
<RefPosition #4 @8 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #5 @8 RefTypeUse <Ivl:1> BB01 regmask=[rdi] minReg=1 last fixed>
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #6 @9 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #7 @9 RefTypeDef <Ivl:2> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N008.t17. PUTARG_REG }
N010 ( 3, 2) [000003] ------------ * LCL_VAR int V00 arg0 NA REG NA
Interval 3: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #8 @11 RefTypeDef <Ivl:3> LCL_VAR BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N008.t17. PUTARG_REG; N010.t3. LCL_VAR }
N012 (???,???) [000018] ------------ * PUTARG_REG int REG rdx
<RefPosition #9 @12 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #10 @12 RefTypeUse <Ivl:3> BB01 regmask=[rdx] minReg=1 last fixed>
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #11 @13 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #12 @13 RefTypeDef <Ivl:4> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N008.t17. PUTARG_REG; N012.t18. PUTARG_REG }
N014 ( 1, 4) [000002] ------------ * CNS_INT int 0x400 REG NA
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #13 @15 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N008.t17. PUTARG_REG; N012.t18. PUTARG_REG; N014.t2. CNS_INT }
N016 (???,???) [000019] ------------ * PUTARG_REG int REG rsi
<RefPosition #14 @16 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #15 @16 RefTypeUse <Ivl:5> BB01 regmask=[rsi] minReg=1 last fixed>
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #16 @17 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #17 @17 RefTypeDef <Ivl:6> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N008.t17. PUTARG_REG; N012.t18. PUTARG_REG; N016.t19. PUTARG_REG }
N018 ( 23, 26) [000004] --CXG------- * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
<RefPosition #18 @18 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #19 @18 RefTypeUse <Ivl:2> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #20 @18 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #21 @18 RefTypeUse <Ivl:4> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #22 @18 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #23 @18 RefTypeUse <Ivl:6> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #24 @19 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #25 @19 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1>
<RefPosition #26 @19 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #27 @19 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #28 @19 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #29 @19 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1>
<RefPosition #30 @19 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1>
<RefPosition #31 @19 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1>
<RefPosition #32 @19 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1>
Interval 7: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #33 @19 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @19 RefTypeDef <Ivl:7> CALL BB01 regmask=[rax] minReg=1 fixed>
+<TreeNodeInfo 1=3 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 3 produce=1
DefList: { N018.t4. CALL }
N020 ( 24, 27) [000008] ---XG------- * RETURN int REG NA
<RefPosition #35 @20 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #36 @20 RefTypeUse <Ivl:7> BB01 regmask=[rax] minReg=1 last fixed>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: (constant) RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#3@7 #5@8} physReg:NA Preferences=[rdi]
Interval 2: RefPositions {#7@9 #19@18} physReg:NA Preferences=[rdi]
Interval 3: RefPositions {#8@11 #10@12} physReg:NA Preferences=[rdx]
Interval 4: RefPositions {#12@13 #21@18} physReg:NA Preferences=[rdx]
Interval 5: (constant) RefPositions {#13@15 #15@16} physReg:NA Preferences=[rsi]
Interval 6: RefPositions {#17@17 #23@18} physReg:NA Preferences=[rsi]
Interval 7: RefPositions {#34@19 #36@20} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @7 RefTypeDef <Ivl:1> IND BB01 regmask=[rdi] minReg=1>
<RefPosition #4 @8 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #5 @8 RefTypeUse <Ivl:1> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #6 @9 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #7 @9 RefTypeDef <Ivl:2> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
<RefPosition #8 @11 RefTypeDef <Ivl:3> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #9 @12 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #10 @12 RefTypeUse <Ivl:3> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #11 @13 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #12 @13 RefTypeDef <Ivl:4> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #13 @15 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[rsi] minReg=1>
<RefPosition #14 @16 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #15 @16 RefTypeUse <Ivl:5> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #16 @17 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #17 @17 RefTypeDef <Ivl:6> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed>
<RefPosition #18 @18 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #19 @18 RefTypeUse <Ivl:2> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #20 @18 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #21 @18 RefTypeUse <Ivl:4> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #22 @18 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #23 @18 RefTypeUse <Ivl:6> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #24 @19 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #25 @19 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #26 @19 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #27 @19 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #28 @19 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #29 @19 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #30 @19 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #31 @19 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #32 @19 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #33 @19 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @19 RefTypeDef <Ivl:7> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #35 @20 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #36 @20 RefTypeUse <Ivl:7> BB01 regmask=[rax] minReg=1 last fixed>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [000..011) (return), preds={} succs={}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. CNS_INT(h) 0x7fec25be4cb8 static Fseq[_bits] REG NA
Def:<I0>(#1)
N006. IND
Use:<I0>(#2) *
Def:<I1>(#3)
N008. PUTARG_REG
Use:<I1>(#5) Fixed:rdi(#4) *
Def:<I2>(#7) rdi
N010. V00 MEM
Def:<I3>(#8)
N012. PUTARG_REG
Use:<I3>(#10) Fixed:rdx(#9) *
Def:<I4>(#12) rdx
N014. CNS_INT 0x400 REG NA
Def:<I5>(#13)
N016. PUTARG_REG
Use:<I5>(#15) Fixed:rsi(#14) *
Def:<I6>(#17) rsi
N018. CALL
Use:<I2>(#19) Fixed:rdi(#18) *
Use:<I4>(#21) Fixed:rdx(#20) *
Use:<I6>(#23) Fixed:rsi(#22) *
Kill: rax rcx rdx rsi rdi r8 r9 r10 r11
Def:<I7>(#34) rax
N020. RETURN
Use:<I7>(#36) Fixed:rax(#35) *
Linear scan intervals after buildIntervals:
Interval 0: (constant) RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#3@7 #5@8} physReg:NA Preferences=[rdi]
Interval 2: RefPositions {#7@9 #19@18} physReg:NA Preferences=[rdi]
Interval 3: RefPositions {#8@11 #10@12} physReg:NA Preferences=[rdx]
Interval 4: RefPositions {#12@13 #21@18} physReg:NA Preferences=[rdx]
Interval 5: (constant) RefPositions {#13@15 #15@16} physReg:NA Preferences=[rsi]
Interval 6: RefPositions {#17@17 #23@18} physReg:NA Preferences=[rsi]
Interval 7: RefPositions {#34@19 #36@20} physReg:NA Preferences=[rax]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: (constant) RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#3@7 #5@8} physReg:NA Preferences=[rdi]
Interval 2: RefPositions {#7@9 #19@18} physReg:NA Preferences=[rdi]
Interval 3: RefPositions {#8@11 #10@12} physReg:NA Preferences=[rdx]
Interval 4: RefPositions {#12@13 #21@18} physReg:NA Preferences=[rdx]
Interval 5: (constant) RefPositions {#13@15 #15@16} physReg:NA Preferences=[rsi]
Interval 6: RefPositions {#17@17 #23@18} physReg:NA Preferences=[rsi]
Interval 7: RefPositions {#34@19 #36@20} physReg:NA Preferences=[rax]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @7 RefTypeDef <Ivl:1> IND BB01 regmask=[rdi] minReg=1>
<RefPosition #4 @8 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #5 @8 RefTypeUse <Ivl:1> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #6 @9 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #7 @9 RefTypeDef <Ivl:2> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
<RefPosition #8 @11 RefTypeDef <Ivl:3> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #9 @12 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #10 @12 RefTypeUse <Ivl:3> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #11 @13 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #12 @13 RefTypeDef <Ivl:4> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #13 @15 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[rsi] minReg=1>
<RefPosition #14 @16 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #15 @16 RefTypeUse <Ivl:5> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #16 @17 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #17 @17 RefTypeDef <Ivl:6> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed>
<RefPosition #18 @18 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #19 @18 RefTypeUse <Ivl:2> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #20 @18 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #21 @18 RefTypeUse <Ivl:4> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #22 @18 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #23 @18 RefTypeUse <Ivl:6> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #24 @19 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #25 @19 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #26 @19 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #27 @19 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #28 @19 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #29 @19 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #30 @19 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #31 @19 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #32 @19 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #33 @19 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @19 RefTypeDef <Ivl:7> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #35 @20 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #36 @20 RefTypeUse <Ivl:7> BB01 regmask=[rax] minReg=1 last fixed>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
------------------------------+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rbx |r12 |r13 |
------------------------------+----+----+----+----+----+
| | | | | |
0.#0 BB1 PredBB0 | | | | | |
------------------------------+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rbx |rdi |r12 |r13 |
------------------------------+----+----+----+----+----+----+
5.#1 C0 Def Alloc rdi | | | |C0 a| | |
6.#2 C0 Use * Keep rdi | | | |C0 a| | |
7.#3 I1 Def Alloc rdi | | | |I1 a| | |
8.#4 rdi Fixd Keep rdi | | | |I1 a| | |
8.#5 I1 Use * Keep rdi | | | |I1 a| | |
9.#6 rdi Fixd Keep rdi | | | | | | |
9.#7 I2 Def Alloc rdi | | | |I2 a| | |
------------------------------+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
------------------------------+----+----+----+----+----+----+----+
11.#8 I3 Def Alloc rdx | | |I3 a| |I2 a| | |
12.#9 rdx Fixd Keep rdx | | |I3 a| |I2 a| | |
12.#10 I3 Use * Keep rdx | | |I3 a| |I2 a| | |
13.#11 rdx Fixd Keep rdx | | | | |I2 a| | |
13.#12 I4 Def Alloc rdx | | |I4 a| |I2 a| | |
------------------------------+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
------------------------------+----+----+----+----+----+----+----+----+
15.#13 C5 Def Alloc rsi | | |I4 a| |C5 a|I2 a| | |
16.#14 rsi Fixd Keep rsi | | |I4 a| |C5 a|I2 a| | |
16.#15 C5 Use * Keep rsi | | |I4 a| |C5 a|I2 a| | |
17.#16 rsi Fixd Keep rsi | | |I4 a| | |I2 a| | |
17.#17 I6 Def Alloc rsi | | |I4 a| |I6 a|I2 a| | |
18.#18 rdi Fixd Keep rdi | | |I4 a| |I6 a|I2 a| | |
18.#19 I2 Use * Keep rdi | | |I4 a| |I6 a|I2 a| | |
18.#20 rdx Fixd Keep rdx | | |I4 a| |I6 a|I2 a| | |
18.#21 I4 Use * Keep rdx | | |I4 a| |I6 a|I2 a| | |
18.#22 rsi Fixd Keep rsi | | |I4 a| |I6 a|I2 a| | |
18.#23 I6 Use * Keep rsi | | |I4 a| |I6 a|I2 a| | |
19.#24 rax Kill Keep rax | | | | | | | | |
19.#25 rcx Kill Keep rcx | | | | | | | | |
19.#26 rdx Kill Keep rdx | | | | | | | | |
19.#27 rsi Kill Keep rsi | | | | | | | | |
19.#28 rdi Kill Keep rdi | | | | | | | | |
19.#29 r8 Kill Keep r8 | | | | | | | | |
19.#30 r9 Kill Keep r9 | | | | | | | | |
19.#31 r10 Kill Keep r10 | | | | | | | | |
19.#32 r11 Kill Keep r11 | | | | | | | | |
19.#33 rax Fixd Keep rax | | | | | | | | |
19.#34 I7 Def Alloc rax |I7 a| | | | | | | |
20.#35 rax Fixd Keep rax |I7 a| | | | | | | |
20.#36 I7 Use * Keep rax | | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[rdi] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #3 @7 RefTypeDef <Ivl:1> IND BB01 regmask=[rdi] minReg=1>
<RefPosition #4 @8 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #5 @8 RefTypeUse <Ivl:1> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #6 @9 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #7 @9 RefTypeDef <Ivl:2> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed>
<RefPosition #8 @11 RefTypeDef <Ivl:3> LCL_VAR BB01 regmask=[rdx] minReg=1>
<RefPosition #9 @12 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #10 @12 RefTypeUse <Ivl:3> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #11 @13 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #12 @13 RefTypeDef <Ivl:4> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed>
<RefPosition #13 @15 RefTypeDef <Ivl:5> CNS_INT BB01 regmask=[rsi] minReg=1>
<RefPosition #14 @16 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #15 @16 RefTypeUse <Ivl:5> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #16 @17 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #17 @17 RefTypeDef <Ivl:6> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed>
<RefPosition #18 @18 RefTypeFixedReg <Reg:rdi> BB01 regmask=[rdi] minReg=1>
<RefPosition #19 @18 RefTypeUse <Ivl:2> BB01 regmask=[rdi] minReg=1 last fixed>
<RefPosition #20 @18 RefTypeFixedReg <Reg:rdx> BB01 regmask=[rdx] minReg=1>
<RefPosition #21 @18 RefTypeUse <Ivl:4> BB01 regmask=[rdx] minReg=1 last fixed>
<RefPosition #22 @18 RefTypeFixedReg <Reg:rsi> BB01 regmask=[rsi] minReg=1>
<RefPosition #23 @18 RefTypeUse <Ivl:6> BB01 regmask=[rsi] minReg=1 last fixed>
<RefPosition #24 @19 RefTypeKill <Reg:rax> BB01 regmask=[rax] minReg=1 last>
<RefPosition #25 @19 RefTypeKill <Reg:rcx> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #26 @19 RefTypeKill <Reg:rdx> BB01 regmask=[rdx] minReg=1 last>
<RefPosition #27 @19 RefTypeKill <Reg:rsi> BB01 regmask=[rsi] minReg=1 last>
<RefPosition #28 @19 RefTypeKill <Reg:rdi> BB01 regmask=[rdi] minReg=1 last>
<RefPosition #29 @19 RefTypeKill <Reg:r8 > BB01 regmask=[r8] minReg=1 last>
<RefPosition #30 @19 RefTypeKill <Reg:r9 > BB01 regmask=[r9] minReg=1 last>
<RefPosition #31 @19 RefTypeKill <Reg:r10> BB01 regmask=[r10] minReg=1 last>
<RefPosition #32 @19 RefTypeKill <Reg:r11> BB01 regmask=[r11] minReg=1 last>
<RefPosition #33 @19 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #34 @19 RefTypeDef <Ivl:7> CALL BB01 regmask=[rax] minReg=1 fixed>
<RefPosition #35 @20 RefTypeFixedReg <Reg:rax> BB01 regmask=[rax] minReg=1>
<RefPosition #36 @20 RefTypeUse <Ivl:7> BB01 regmask=[rax] minReg=1 last fixed>
Active intervals at end of allocation:
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..011) (return), preds={} succs={}
N002 ( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N004 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits] REG rdi
/--* t10 long
N006 ( 5, 12) [000001] x---G------- t1 = * IND long REG rdi
/--* t1 long
N008 (???,???) [000017] ----G------- t17 = * PUTARG_REG long REG rdi
N010 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0 rdx REG rdx
/--* t3 int
N012 (???,???) [000018] ------------ t18 = * PUTARG_REG int REG rdx
N014 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400 REG rsi
/--* t2 int
N016 (???,???) [000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
N018 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
/--* t4 int
N020 ( 24, 27) [000008] ---XG------- * RETURN int REG NA
-------------------------------------------------------------------------------------------------------------------
Final allocation
------------------------------+----+----+----+----+----+----+----+----+
LocRP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r12 |r13 |
------------------------------+----+----+----+----+----+----+----+----+
0.#0 BB1 PredBB0 | | | | | | | | |
5.#1 C0 Def Alloc rdi | | | | | |C0 a| | |
6.#2 C0 Use * Keep rdi | | | | | |C0 i| | |
7.#3 I1 Def Alloc rdi | | | | | |I1 a| | |
8.#4 rdi Fixd Keep rdi | | | | | |I1 a| | |
8.#5 I1 Use * Keep rdi | | | | | |I1 i| | |
9.#6 rdi Fixd Keep rdi | | | | | | | | |
9.#7 I2 Def Alloc rdi | | | | | |I2 a| | |
11.#8 I3 Def Alloc rdx | | |I3 a| | |I2 a| | |
12.#9 rdx Fixd Keep rdx | | |I3 a| | |I2 a| | |
12.#10 I3 Use * Keep rdx | | |I3 i| | |I2 a| | |
13.#11 rdx Fixd Keep rdx | | | | | |I2 a| | |
13.#12 I4 Def Alloc rdx | | |I4 a| | |I2 a| | |
15.#13 C5 Def Alloc rsi | | |I4 a| |C5 a|I2 a| | |
16.#14 rsi Fixd Keep rsi | | |I4 a| |C5 a|I2 a| | |
16.#15 C5 Use * Keep rsi | | |I4 a| |C5 i|I2 a| | |
17.#16 rsi Fixd Keep rsi | | |I4 a| | |I2 a| | |
17.#17 I6 Def Alloc rsi | | |I4 a| |I6 a|I2 a| | |
18.#18 rdi Fixd Keep rdi | | |I4 a| |I6 a|I2 a| | |
18.#19 I2 Use * Keep rdi | | |I4 a| |I6 a|I2 i| | |
18.#20 rdx Fixd Keep rdx | | |I4 a| |I6 a| | | |
18.#21 I4 Use * Keep rdx | | |I4 i| |I6 a| | | |
18.#22 rsi Fixd Keep rsi | | | | |I6 a| | | |
18.#23 I6 Use * Keep rsi | | | | |I6 i| | | |
19.#24 rax Kill Keep rax | | | | | | | | |
19.#25 rcx Kill Keep rcx | | | | | | | | |
19.#26 rdx Kill Keep rdx | | | | | | | | |
19.#27 rsi Kill Keep rsi | | | | | | | | |
19.#28 rdi Kill Keep rdi | | | | | | | | |
19.#29 r8 Kill Keep r8 | | | | | | | | |
19.#30 r9 Kill Keep r9 | | | | | | | | |
19.#31 r10 Kill Keep r10 | | | | | | | | |
19.#32 r11 Kill Keep r11 | | | | | | | | |
19.#33 rax Fixd Keep rax | | | | | | | | |
19.#34 I7 Def Alloc rax |I7 a| | | | | | | |
20.#35 rax Fixd Keep rax |I7 a| | | | | | | |
20.#36 I7 Use * Keep rax |I7 i| | | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 0
Total Reg Cand Vars: 0
Total number of Intervals: 7
Total number of RefPositions: 36
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [000..011) (return), preds={} succs={}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. rdi* = CNS_INT(h) 0x7fec25be4cb8 static Fseq[_bits] REG rdi
N006. rdi = IND ; rdi*
N008. rdi = PUTARG_REG; rdi
N010. rdx = V00 MEM
N012. rdx = PUTARG_REG; rdx
N014. rsi = CNS_INT 0x400 REG rsi
N016. rsi = PUTARG_REG; rsi
N018. rax = CALL ; rdi,rdx,rsi
N020. RETURN ; rax
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..011) (return) i label target gcsafe LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Modified regs: [rax rcx rdx rsi rdi r8-r11]
Callee-saved registers pushed: 0 []
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V00 arg0, size=4, stkOffs=-0x14
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) int -> [rbp-0x04]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
;
; Lcl frame size = 16
=============== Generating BB01 [000..011) (return), preds={} succs={} flags=0x00000000.400b0020: i label target gcsafe LIR
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M17377_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Setting stack level from -572662307 to 0
Scope info: begin block BB01, IL range [000..011)
Scope info: open scopes =
<none>
Added IP mapping: 0x0000 STACK_EMPTY (G_M17377_IG02,ins#0,ofs#0) label
Generating: N002 ( 24, 27) [000009] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N004 ( 3, 10) [000010] ------------ t10 = CNS_INT(h) long 0x7fec25be4cb8 static Fseq[_bits] REG rdi
IN0001: mov rdi, 0x7FEC25BE4CB8
/--* t10 long
Generating: N006 ( 5, 12) [000001] x---G------- t1 = * IND long REG rdi
IN0002: mov rdi, qword ptr [rdi]
/--* t1 long
Generating: N008 (???,???) [000017] ----G------- t17 = * PUTARG_REG long REG rdi
Generating: N010 ( 3, 2) [000003] ------------ t3 = LCL_VAR int V00 arg0 rdx REG rdx
IN0003: mov edx, dword ptr [V00 rbp-04H]
/--* t3 int
Generating: N012 (???,???) [000018] ------------ t18 = * PUTARG_REG int REG rdx
Generating: N014 ( 1, 4) [000002] ------------ t2 = CNS_INT int 0x400 REG rsi
IN0004: mov esi, 0x400
/--* t2 int
Generating: N016 (???,???) [000019] ------------ t19 = * PUTARG_REG int REG rsi
/--* t17 long arg0 in rdi
+--* t18 int arg2 in rdx
+--* t19 int arg1 in rsi
Generating: N018 ( 23, 26) [000004] --CXG------- t4 = * CALL int GetNthBitOffset.POPCNTAndBMI2Unrolled
Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0005: call GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
/--* t4 int
Generating: N020 ( 24, 27) [000008] ---XG------- * RETURN int REG NA
Scope info: end block BB01, IL range [000..011)
Scope info: ending scope, LVnum=0 [000..011)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M17377_IG02,ins#5,ofs#26) label
Reserving epilog IG for block BB01
IN0006: nop
G_M17377_IG02: ; offs=000000H, funclet=00
*************** After placeholder IG creation
G_M17377_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M17377_IG02: ; offs=000000H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M17377_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 24, compSizeEstimate = 27 Program:POPCNTAndBMI2Unrolled(int):int
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) int -> [rbp-0x04]
;# V01 OutArgs [V01 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
;
; Lcl frame size = 16
*************** Before prolog / epilog generation
G_M17377_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M17377_IG02: ; offs=000000H, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M17377_IG03: ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M17377_IG01,ins#0,ofs#0) label
__prolog:
IN0007: push rbp
IN0008: sub rsp, 16
IN0009: lea rbp, [rsp+10H]
*************** In genClearStackVec3ArgUpperBits()
*************** In genFnPrologCalleeRegArgs() for int regs
IN000a: mov dword ptr [V00 rbp-04H], edi
*************** In genEnregisterIncomingStackArgs()
G_M17377_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN000b: lea rsp, [rbp]
IN000c: pop rbp
IN000d: ret
G_M17377_IG03: ; offs=00001BH, funclet=00
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M17377_IG01: ; func=00, offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M17377_IG02: ; offs=00000DH, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M17377_IG03: ; offs=000028H, size=0006H, epilog, nogc, emitadd
*************** In emitJumpDistBind()
Hot code size = 0x2E bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M17377_IG01: ; func=00, offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0007: 000000 55 push rbp
IN0008: 000001 4883EC10 sub rsp, 16
IN0009: 000005 488D6C2410 lea rbp, [rsp+10H]
IN000a: 00000A 897DFC mov dword ptr [rbp-04H], edi
G_M17377_IG02: ; func=00, offs=00000DH, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 00000D 48BFB84CBE25EC7F0000 mov rdi, 0x7FEC25BE4CB8
IN0002: 000017 488B3F mov rdi, qword ptr [rdi]
IN0003: 00001A 8B55FC mov edx, dword ptr [rbp-04H]
IN0004: 00001D BE00040000 mov esi, 0x400
; Call at 0022 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
IN0005: 000022 E821D9FFFF call GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
IN0006: 000027 90 nop
G_M17377_IG03: ; func=00, offs=000028H, size=0006H, epilog, nogc, emitadd
IN000b: 000028 488D6500 lea rsp, [rbp]
IN000c: 00002C 5D pop rbp
IN000d: 00002D C3 ret
Allocated method code size = 46 , actual size = 46
*************** After end code gen, before unwindEmit()
G_M17377_IG01: ; func=00, offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0007: 000000 push rbp
IN0008: 000001 sub rsp, 16
IN0009: 000005 lea rbp, [rsp+10H]
IN000a: 00000A mov dword ptr [V00 rbp-04H], edi
G_M17377_IG02: ; offs=00000DH, size=001BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 00000D mov rdi, 0x7FEC25BE4CB8
IN0002: 000017 mov rdi, qword ptr [rdi]
IN0003: 00001A mov edx, dword ptr [V00 rbp-04H]
IN0004: 00001D mov esi, 0x400
IN0005: 000022 call GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
IN0006: 000027 nop
G_M17377_IG03: ; offs=000028H, size=0006H, epilog, nogc, emitadd
IN000b: 000028 lea rsp, [rbp]
IN000c: 00002C pop rbp
IN000d: 00002D ret
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x00002e (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x05
CountOfUnwindCodes: 2
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x05 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 1 * 8 + 8 = 16 = 0x10
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x00007FEC268639A0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x2e, unwindSize=0x8, pUnwindBlock=0x0000000001401128, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 3
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000000D ( STACK_EMPTY )
IL offs EPILOG : 0x00000027 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 1
*************** Variable debug info
1 vars
0( UNKNOWN) : From 00000000h to 0000000Dh, in rdi
*************** In gcInfoBlockHdrSave()
Set code length to 46.
Set ReturnKind to Scalar.
Set stack base register to rbp.
Set Outgoing stack arg area size to 0.
Defining 0 call sites:
Method code size: 46
Allocations for Program:POPCNTAndBMI2Unrolled(int):int (MethodHash=8edbbc1e)
count: 184, size: 20915, max = 2600
allocateMemory: 65536, nraUsed: 23288
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 0 | 0.00%
ASTNode | 2560 | 12.24%
InstDesc | 2568 | 12.28%
ImpStack | 384 | 1.84%
BasicBlock | 864 | 4.13%
fgArgInfo | 192 | 0.92%
fgArgInfoPtrArr | 24 | 0.11%
FlowList | 0 | 0.00%
TreeStatementList | 0 | 0.00%
SiScope | 72 | 0.34%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 0 | 0.00%
LSRA | 2960 | 14.15%
LSRA_Interval | 640 | 3.06%
LSRA_RefPosition | 2368 | 11.32%
Reachability | 0 | 0.00%
SSA | 0 | 0.00%
ValueNumber | 0 | 0.00%
LvaTable | 1792 | 8.57%
UnwindInfo | 0 | 0.00%
hashBv | 40 | 0.19%
bitset | 56 | 0.27%
FixedBitVect | 8 | 0.04%
Generic | 638 | 3.05%
IndirAssignMap | 0 | 0.00%
FieldSeqStore | 176 | 0.84%
ZeroOffsetFieldMap | 0 | 0.00%
ArrayInfoMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 0 | 0.00%
GC | 1288 | 6.16%
CorSig | 104 | 0.50%
Inlining | 128 | 0.61%
ArrayStack | 0 | 0.00%
DebugInfo | 168 | 0.80%
DebugOnly | 2644 | 12.64%
Codegen | 1144 | 5.47%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 97 | 0.46%
RangeCheck | 0 | 0.00%
CopyProp | 0 | 0.00%
SideEffects | 0 | 0.00%
****** DONE compiling Program:POPCNTAndBMI2Unrolled(int):int
****** START compiling GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int (MethodHash=cbde5985)
Generating code for Unix x64
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC = false
OPTIONS: compProcedureSplitting = false
OPTIONS: compProcedureSplittingEH = false
OPTIONS: Stack probing is DISABLED
IL to import:
IL_0000 02 ldarg.0
IL_0001 0a stloc.0
IL_0002 2b 37 br.s 55 (IL_003b)
IL_0004 04 ldarg.2
IL_0005 06 ldloc.0
IL_0006 4c ldind.i8
IL_0007 28 0d 00 00 0a call 0xA00000D
IL_000c 06 ldloc.0
IL_000d 1e ldc.i4.8
IL_000e 58 add
IL_000f 4c ldind.i8
IL_0010 28 0d 00 00 0a call 0xA00000D
IL_0015 58 add
IL_0016 06 ldloc.0
IL_0017 18 ldc.i4.2
IL_0018 d3 conv.i
IL_0019 1e ldc.i4.8
IL_001a 5a mul
IL_001b 58 add
IL_001c 4c ldind.i8
IL_001d 28 0d 00 00 0a call 0xA00000D
IL_0022 58 add
IL_0023 06 ldloc.0
IL_0024 19 ldc.i4.3
IL_0025 d3 conv.i
IL_0026 1e ldc.i4.8
IL_0027 5a mul
IL_0028 58 add
IL_0029 4c ldind.i8
IL_002a 28 0d 00 00 0a call 0xA00000D
IL_002f 58 add
IL_0030 69 conv.i4
IL_0031 59 sub
IL_0032 10 02 starg.s 0x2
IL_0034 06 ldloc.0
IL_0035 1a ldc.i4.4
IL_0036 d3 conv.i
IL_0037 1e ldc.i4.8
IL_0038 5a mul
IL_0039 58 add
IL_003a 0a stloc.0
IL_003b 04 ldarg.2
IL_003c 20 00 01 00 00 ldc.i4 0x100
IL_0041 2f c1 bge.s -63 (IL_0004)
IL_0043 04 ldarg.2
IL_0044 0b stloc.1
IL_0045 2b 12 br.s 18 (IL_0059)
IL_0047 04 ldarg.2
IL_0048 0b stloc.1
IL_0049 04 ldarg.2
IL_004a 06 ldloc.0
IL_004b 4c ldind.i8
IL_004c 28 0d 00 00 0a call 0xA00000D
IL_0051 69 conv.i4
IL_0052 59 sub
IL_0053 10 02 starg.s 0x2
IL_0055 06 ldloc.0
IL_0056 1e ldc.i4.8
IL_0057 58 add
IL_0058 0a stloc.0
IL_0059 04 ldarg.2
IL_005a 16 ldc.i4.0
IL_005b 30 ea bgt.s -22 (IL_0047)
IL_005d 06 ldloc.0
IL_005e 1e ldc.i4.8
IL_005f 59 sub
IL_0060 0a stloc.0
IL_0061 17 ldc.i4.1
IL_0062 6a conv.i8
IL_0063 07 ldloc.1
IL_0064 17 ldc.i4.1
IL_0065 59 sub
IL_0066 1f 3f ldc.i4.s 0x3F
IL_0068 5f and
IL_0069 62 shl
IL_006a 06 ldloc.0
IL_006b 4c ldind.i8
IL_006c 28 11 00 00 0a call 0xA000011
IL_0071 28 12 00 00 0a call 0xA000012
IL_0076 69 conv.i4
IL_0077 0c stloc.2
IL_0078 06 ldloc.0
IL_0079 02 ldarg.0
IL_007a 59 sub
IL_007b 1e ldc.i4.8
IL_007c 5b div
IL_007d 6a conv.i8
IL_007e 1f 40 ldc.i4.s 0x40
IL_0080 6a conv.i8
IL_0081 5a mul
IL_0082 69 conv.i4
IL_0083 08 ldloc.2
IL_0084 58 add
IL_0085 2a ret
Arg #0 passed in register(s) rdi
Arg #1 passed in register(s) rsi
Arg #2 passed in register(s) rdx
lvaGrabTemp returning 6 (V06 tmp0) (a long lifetime temp) called for OutgoingArgSpace.
; Initial local variable assignments
;
; V00 arg0 long
; V01 arg1 int
; V02 arg2 int
; V03 loc0 long
; V04 loc1 int
; V05 loc2 int
; V06 OutArgs lclBlk (na)
*************** In compInitDebuggingInfo() for GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 6
VarNum LVNum Name Beg End
0: 00h 00h V00 arg0 000h 086h
1: 01h 01h V01 arg1 000h 086h
2: 02h 02h V02 arg2 000h 086h
3: 03h 03h V03 loc0 000h 086h
4: 04h 04h V04 loc1 000h 086h
5: 05h 05h V05 loc2 000h 086h
info.compStmtOffsetsCount = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
Jump targets:
IL_0004
IL_003b
IL_0047
IL_0059
New Basic Block BB01 [0000] created.
BB01 [000..004)
New Basic Block BB02 [0001] created.
BB02 [004..03B)
New Basic Block BB03 [0002] created.
BB03 [03B..043)
New Basic Block BB04 [0003] created.
BB04 [043..047)
New Basic Block BB05 [0004] created.
BB05 [047..059)
New Basic Block BB06 [0005] created.
BB06 [059..05D)
New Basic Block BB07 [0006] created.
BB07 [05D..086)
CLFLG_MINOPT set for method GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
IL Code Size,Instr 134, 94, Basic Block count 7, Local Variable Num,Ref count 7, 29 for method GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
IL Code Size,Instr 134, 94, Basic Block count 7, Local Variable Num,Ref count 7, 29 for method GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
OPTIONS: opts.MinOpts() == true
Basic block list for 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always)
BB02 [0001] 1 1 [004..03B) bwd
BB03 [0002] 2 1 [03B..043)-> BB02 ( cond ) bwd
BB04 [0003] 1 1 [043..047)-> BB06 (always)
BB05 [0004] 1 1 [047..059) bwd
BB06 [0005] 2 1 [059..05D)-> BB05 ( cond ) bwd
BB07 [0006] 1 1 [05D..086) (return)
--------------------------------------------------------------------------------------------------------------------------------------
*************** In impImport() for GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
impImportBlockPending for BB01
Importing BB01 (PC=000) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 0 (0x000) ldarg.0
[ 1] 1 (0x001) stloc.0
[000004] ------------ * STMT void (IL 0x000... ???)
[000001] ------------ | /--* LCL_VAR long V00 arg0
[000003] -A---------- \--* ASG long
[000002] D------N---- \--* LCL_VAR long V03 loc0
[ 0] 2 (0x002) br.s
impImportBlockPending for BB03
Importing BB03 (PC=059) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 59 (0x03b) ldarg.2
[ 1] 60 (0x03c) ldc.i4 256
[ 2] 65 (0x041) bge.s
[000010] ------------ * STMT void (IL 0x03B... ???)
[000009] ------------ \--* JTRUE void
[000007] ------------ | /--* CNS_INT int 256
[000008] ------------ \--* GE int
[000006] ------------ \--* LCL_VAR int V02 arg2
impImportBlockPending for BB04
impImportBlockPending for BB02
Importing BB02 (PC=004) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 4 (0x004) ldarg.2
[ 1] 5 (0x005) ldloc.0
[ 2] 6 (0x006) ldind.i8
[ 2] 7 (0x007) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 2] 12 (0x00c) ldloc.0
[ 3] 13 (0x00d) ldc.i4.8 8
[ 4] 14 (0x00e) add
[ 3] 15 (0x00f) ldind.i8
[ 3] 16 (0x010) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 3] 21 (0x015) add
[ 2] 22 (0x016) ldloc.0
[ 3] 23 (0x017) ldc.i4.2 2
[ 4] 24 (0x018) conv.i
[ 4] 25 (0x019) ldc.i4.8 8
[ 5] 26 (0x01a) mul
[ 4] 27 (0x01b) add
[ 3] 28 (0x01c) ldind.i8
[ 3] 29 (0x01d) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 3] 34 (0x022) add
[ 2] 35 (0x023) ldloc.0
[ 3] 36 (0x024) ldc.i4.3 3
[ 4] 37 (0x025) conv.i
[ 4] 38 (0x026) ldc.i4.8 8
[ 5] 39 (0x027) mul
[ 4] 40 (0x028) add
[ 3] 41 (0x029) ldind.i8
[ 3] 42 (0x02a) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 3] 47 (0x02f) add
[ 2] 48 (0x030) conv.i4
[ 2] 49 (0x031) sub
[ 1] 50 (0x032) starg.s 2
[000047] ------------ * STMT void (IL 0x004... ???)
[000043] ---XG------- | /--* CAST int <- long
[000041] ---XG------- | | | /--* HWIntrinsic long PopCount
[000040] *--XG------- | | | | \--* IND long
[000037] ------------ | | | | | /--* CAST long <- int
[000036] ------------ | | | | | | \--* CNS_INT int 8
[000038] ------------ | | | | | /--* MUL long
[000035] ------------ | | | | | | \--* CAST long <- int
[000034] ------------ | | | | | | \--* CNS_INT int 3
[000039] ------------ | | | | \--* ADD long
[000033] ------------ | | | | \--* LCL_VAR long V03 loc0
[000042] ---XG------- | | \--* ADD long
[000031] ---XG------- | | | /--* HWIntrinsic long PopCount
[000030] *--XG------- | | | | \--* IND long
[000027] ------------ | | | | | /--* CAST long <- int
[000026] ------------ | | | | | | \--* CNS_INT int 8
[000028] ------------ | | | | | /--* MUL long
[000025] ------------ | | | | | | \--* CAST long <- int
[000024] ------------ | | | | | | \--* CNS_INT int 2
[000029] ------------ | | | | \--* ADD long
[000023] ------------ | | | | \--* LCL_VAR long V03 loc0
[000032] ---XG------- | | \--* ADD long
[000021] ---XG------- | | | /--* HWIntrinsic long PopCount
[000020] *--XG------- | | | | \--* IND long
[000018] ------------ | | | | | /--* CAST long <- int
[000017] ------------ | | | | | | \--* CNS_INT int 8
[000019] ------------ | | | | \--* ADD long
[000016] ------------ | | | | \--* LCL_VAR long V03 loc0
[000022] ---XG------- | | \--* ADD long
[000015] ---XG------- | | \--* HWIntrinsic long PopCount
[000014] *--XG------- | | \--* IND long
[000013] ------------ | | \--* LCL_VAR long V03 loc0
[000044] ---XG------- | /--* SUB int
[000012] ------------ | | \--* LCL_VAR int V02 arg2
[000046] -A-XG------- \--* ASG int
[000045] D------N---- \--* LCL_VAR int V02 arg2
[ 0] 52 (0x034) ldloc.0
[ 1] 53 (0x035) ldc.i4.4 4
[ 2] 54 (0x036) conv.i
[ 2] 55 (0x037) ldc.i4.8 8
[ 3] 56 (0x038) mul
[ 2] 57 (0x039) add
[ 1] 58 (0x03a) stloc.0
[000057] ------------ * STMT void (IL 0x034... ???)
[000052] ------------ | /--* CAST long <- int
[000051] ------------ | | \--* CNS_INT int 8
[000053] ------------ | /--* MUL long
[000050] ------------ | | \--* CAST long <- int
[000049] ------------ | | \--* CNS_INT int 4
[000054] ------------ | /--* ADD long
[000048] ------------ | | \--* LCL_VAR long V03 loc0
[000056] -A---------- \--* ASG long
[000055] D------N---- \--* LCL_VAR long V03 loc0
impImportBlockPending for BB03
Importing BB04 (PC=067) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 67 (0x043) ldarg.2
[ 1] 68 (0x044) stloc.1
[000062] ------------ * STMT void (IL 0x043... ???)
[000059] ------------ | /--* LCL_VAR int V02 arg2
[000061] -A---------- \--* ASG int
[000060] D------N---- \--* LCL_VAR int V04 loc1
[ 0] 69 (0x045) br.s
impImportBlockPending for BB06
Importing BB06 (PC=089) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 89 (0x059) ldarg.2
[ 1] 90 (0x05a) ldc.i4.0 0
[ 2] 91 (0x05b) bgt.s
[000068] ------------ * STMT void (IL 0x059... ???)
[000067] ------------ \--* JTRUE void
[000065] ------------ | /--* CNS_INT int 0
[000066] ------------ \--* GT int
[000064] ------------ \--* LCL_VAR int V02 arg2
impImportBlockPending for BB07
impImportBlockPending for BB05
Importing BB05 (PC=071) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 71 (0x047) ldarg.2
[ 1] 72 (0x048) stloc.1
[000073] ------------ * STMT void (IL 0x047... ???)
[000070] ------------ | /--* LCL_VAR int V02 arg2
[000072] -A---------- \--* ASG int
[000071] D------N---- \--* LCL_VAR int V04 loc1
[ 0] 73 (0x049) ldarg.2
[ 1] 74 (0x04a) ldloc.0
[ 2] 75 (0x04b) ldind.i8
[ 2] 76 (0x04c) call 0A00000D
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 2] 81 (0x051) conv.i4
[ 2] 82 (0x052) sub
[ 1] 83 (0x053) starg.s 2
[000082] ------------ * STMT void (IL 0x049... ???)
[000078] ---XG------- | /--* CAST int <- long
[000077] ---XG------- | | \--* HWIntrinsic long PopCount
[000076] *--XG------- | | \--* IND long
[000075] ------------ | | \--* LCL_VAR long V03 loc0
[000079] ---XG------- | /--* SUB int
[000074] ------------ | | \--* LCL_VAR int V02 arg2
[000081] -A-XG------- \--* ASG int
[000080] D------N---- \--* LCL_VAR int V02 arg2
[ 0] 85 (0x055) ldloc.0
[ 1] 86 (0x056) ldc.i4.8 8
[ 2] 87 (0x057) add
[ 1] 88 (0x058) stloc.0
[000089] ------------ * STMT void (IL 0x055... ???)
[000085] ------------ | /--* CAST long <- int
[000084] ------------ | | \--* CNS_INT int 8
[000086] ------------ | /--* ADD long
[000083] ------------ | | \--* LCL_VAR long V03 loc0
[000088] -A---------- \--* ASG long
[000087] D------N---- \--* LCL_VAR long V03 loc0
impImportBlockPending for BB06
Importing BB07 (PC=093) of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
[ 0] 93 (0x05d) ldloc.0
[ 1] 94 (0x05e) ldc.i4.8 8
[ 2] 95 (0x05f) sub
[ 1] 96 (0x060) stloc.0
[000097] ------------ * STMT void (IL 0x05D... ???)
[000093] ------------ | /--* CAST long <- int
[000092] ------------ | | \--* CNS_INT int 8
[000094] ------------ | /--* SUB long
[000091] ------------ | | \--* LCL_VAR long V03 loc0
[000096] -A---------- \--* ASG long
[000095] D------N---- \--* LCL_VAR long V03 loc0
[ 0] 97 (0x061) ldc.i4.1 1
[ 1] 98 (0x062) conv.i8
[ 1] 99 (0x063) ldloc.1
[ 2] 100 (0x064) ldc.i4.1 1
[ 3] 101 (0x065) sub
[ 2] 102 (0x066) ldc.i4.s 63
[ 3] 104 (0x068) and
[ 2] 105 (0x069) shl
[ 1] 106 (0x06a) ldloc.0
[ 2] 107 (0x06b) ldind.i8
[ 2] 108 (0x06c) call 0A000011
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 1] 113 (0x071) call 0A000012
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0
[ 1] 118 (0x076) conv.i4
[ 1] 119 (0x077) stloc.2
[000113] ------------ * STMT void (IL 0x061... ???)
[000110] ---XG------- | /--* CAST int <- long
[000109] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG------- | | | /--* IND long
[000106] ------------ | | | | \--* LCL_VAR long V03 loc0
[000108] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
[000103] ------------ | | | /--* CNS_INT int 63
[000104] ------------ | | | /--* AND int
[000101] ------------ | | | | | /--* CNS_INT int 1
[000102] ------------ | | | | \--* SUB int
[000100] ------------ | | | | \--* LCL_VAR int V04 loc1
[000105] ------------ | | \--* LSH long
[000099] ------------ | | \--* CAST long <- int
[000098] ------------ | | \--* CNS_INT int 1
[000112] -A-XG------- \--* ASG int
[000111] D------N---- \--* LCL_VAR int V05 loc2
[ 0] 120 (0x078) ldloc.0
[ 1] 121 (0x079) ldarg.0
[ 2] 122 (0x07a) sub
[ 1] 123 (0x07b) ldc.i4.8 8
[ 2] 124 (0x07c) div
[ 1] 125 (0x07d) conv.i8
[ 1] 126 (0x07e) ldc.i4.s 64
[ 2] 128 (0x080) conv.i8
[ 2] 129 (0x081) mul
[ 1] 130 (0x082) conv.i4
[ 1] 131 (0x083) ldloc.2
[ 2] 132 (0x084) add
[ 1] 133 (0x085) ret
[000127] ------------ * STMT void (IL 0x078... ???)
[000126] ---X-------- \--* RETURN int
[000124] ------------ | /--* LCL_VAR int V05 loc2
[000125] ---X-------- \--* ADD int
[000123] ---X-------- \--* CAST int <- long
[000121] ------------ | /--* CAST long <- int
[000120] ------------ | | \--* CNS_INT int 64
[000122] ---X-------- \--* MUL long
[000118] ------------ | /--* CAST long <- int
[000117] ------------ | | \--* CNS_INT int 8
[000119] ---X-------- \--* DIV long
[000115] ------------ | /--* LCL_VAR long V00 arg0
[000116] ------------ \--* SUB long
[000114] ------------ \--* LCL_VAR long V03 loc0
New BlockSet epoch 1, # of blocks (including unused BB00): 8, bitset array size: 1 (short)
*************** In fgMorph()
*************** In fgDebugCheckBBlist
*************** After fgAddInternal()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i
BB02 [0001] 1 1 [004..03B) i bwd
BB03 [0002] 2 1 [03B..043)-> BB02 ( cond ) i bwd
BB04 [0003] 1 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 1 [047..059) i bwd
BB06 [0005] 2 1 [059..05D)-> BB05 ( cond ) i bwd
BB07 [0006] 1 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.
*************** In fgRemoveEmptyFinally()
No EH in this method, nothing to remove.
*************** In fgMergeFinallyChains()
No EH in this method, nothing to merge.
*************** In fgCloneFinally()
No EH in this method, no cloning.
*************** In fgPromoteStructs()
promotion opt flag not enabled
*************** In fgMarkAddressExposedLocals()
*************** In fgMorphBlocks()
Morphing BB01 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB01, stmt 1 (before)
[000001] ------------ /--* LCL_VAR long V00 arg0
[000003] -A---------- * ASG long
[000002] D------N---- \--* LCL_VAR long V03 loc0
Morphing BB02 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB02, stmt 2 (before)
[000043] ---XG------- /--* CAST int <- long
[000041] ---XG------- | | /--* HWIntrinsic long PopCount
[000040] *--XG------- | | | \--* IND long
[000037] ------------ | | | | /--* CAST long <- int
[000036] ------------ | | | | | \--* CNS_INT int 8
[000038] ------------ | | | | /--* MUL long
[000035] ------------ | | | | | \--* CAST long <- int
[000034] ------------ | | | | | \--* CNS_INT int 3
[000039] ------------ | | | \--* ADD long
[000033] ------------ | | | \--* LCL_VAR long V03 loc0
[000042] ---XG------- | \--* ADD long
[000031] ---XG------- | | /--* HWIntrinsic long PopCount
[000030] *--XG------- | | | \--* IND long
[000027] ------------ | | | | /--* CAST long <- int
[000026] ------------ | | | | | \--* CNS_INT int 8
[000028] ------------ | | | | /--* MUL long
[000025] ------------ | | | | | \--* CAST long <- int
[000024] ------------ | | | | | \--* CNS_INT int 2
[000029] ------------ | | | \--* ADD long
[000023] ------------ | | | \--* LCL_VAR long V03 loc0
[000032] ---XG------- | \--* ADD long
[000021] ---XG------- | | /--* HWIntrinsic long PopCount
[000020] *--XG------- | | | \--* IND long
[000018] ------------ | | | | /--* CAST long <- int
[000017] ------------ | | | | | \--* CNS_INT int 8
[000019] ------------ | | | \--* ADD long
[000016] ------------ | | | \--* LCL_VAR long V03 loc0
[000022] ---XG------- | \--* ADD long
[000015] ---XG------- | \--* HWIntrinsic long PopCount
[000014] *--XG------- | \--* IND long
[000013] ------------ | \--* LCL_VAR long V03 loc0
[000044] ---XG------- /--* SUB int
[000012] ------------ | \--* LCL_VAR int V02 arg2
[000046] -A-XG------- * ASG int
[000045] D------N---- \--* LCL_VAR int V02 arg2
fgMorphTree BB02, stmt 2 (after)
[000129] ---XG+------ /--* CAST int <- long
[000041] ---XG+------ | \--* HWIntrinsic long PopCount
[000040] *--XG+------ | \--* IND long
[000037] -----+------ | | /--* CAST long <- int
[000036] -----+------ | | | \--* CNS_INT int 8
[000038] -----+------ | | /--* MUL long
[000035] -----+------ | | | \--* CAST long <- int
[000034] -----+------ | | | \--* CNS_INT int 3
[000039] -----+------ | \--* ADD long
[000033] -----+------ | \--* LCL_VAR long V03 loc0
[000042] ---XG+------ /--* ADD int
[000131] ---XG+------ | | /--* CAST int <- long
[000031] ---XG+------ | | | \--* HWIntrinsic long PopCount
[000030] *--XG+------ | | | \--* IND long
[000027] -----+------ | | | | /--* CAST long <- int
[000026] -----+------ | | | | | \--* CNS_INT int 8
[000028] -----+------ | | | | /--* MUL long
[000025] -----+------ | | | | | \--* CAST long <- int
[000024] -----+------ | | | | | \--* CNS_INT int 2
[000029] -----+------ | | | \--* ADD long
[000023] -----+------ | | | \--* LCL_VAR long V03 loc0
[000032] ---XG+------ | \--* ADD int
[000133] ---XG+------ | | /--* CAST int <- long
[000021] ---XG+------ | | | \--* HWIntrinsic long PopCount
[000020] *--XG+------ | | | \--* IND long
[000018] -----+------ | | | | /--* CAST long <- int
[000017] -----+------ | | | | | \--* CNS_INT int 8
[000019] -----+------ | | | \--* ADD long
[000016] -----+------ | | | \--* LCL_VAR long V03 loc0
[000022] ---XG+------ | \--* ADD int
[000132] ---XG+------ | \--* CAST int <- long
[000015] ---XG+------ | \--* HWIntrinsic long PopCount
[000014] *--XG+------ | \--* IND long
[000013] -----+------ | \--* LCL_VAR long V03 loc0
[000044] ---XG+------ /--* SUB int
[000012] -----+------ | \--* LCL_VAR int V02 arg2
[000046] -A-XG+------ * ASG int
[000045] D----+-N---- \--* LCL_VAR int V02 arg2
fgMorphTree BB02, stmt 3 (before)
[000052] ------------ /--* CAST long <- int
[000051] ------------ | \--* CNS_INT int 8
[000053] ------------ /--* MUL long
[000050] ------------ | \--* CAST long <- int
[000049] ------------ | \--* CNS_INT int 4
[000054] ------------ /--* ADD long
[000048] ------------ | \--* LCL_VAR long V03 loc0
[000056] -A---------- * ASG long
[000055] D------N---- \--* LCL_VAR long V03 loc0
Morphing BB03 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB03, stmt 4 (before)
[000009] ------------ * JTRUE void
[000007] ------------ | /--* CNS_INT int 256
[000008] ------------ \--* GE int
[000006] ------------ \--* LCL_VAR int V02 arg2
Morphing BB04 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB04, stmt 5 (before)
[000059] ------------ /--* LCL_VAR int V02 arg2
[000061] -A---------- * ASG int
[000060] D------N---- \--* LCL_VAR int V04 loc1
Morphing BB05 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB05, stmt 6 (before)
[000070] ------------ /--* LCL_VAR int V02 arg2
[000072] -A---------- * ASG int
[000071] D------N---- \--* LCL_VAR int V04 loc1
fgMorphTree BB05, stmt 7 (before)
[000078] ---XG------- /--* CAST int <- long
[000077] ---XG------- | \--* HWIntrinsic long PopCount
[000076] *--XG------- | \--* IND long
[000075] ------------ | \--* LCL_VAR long V03 loc0
[000079] ---XG------- /--* SUB int
[000074] ------------ | \--* LCL_VAR int V02 arg2
[000081] -A-XG------- * ASG int
[000080] D------N---- \--* LCL_VAR int V02 arg2
fgMorphTree BB05, stmt 8 (before)
[000085] ------------ /--* CAST long <- int
[000084] ------------ | \--* CNS_INT int 8
[000086] ------------ /--* ADD long
[000083] ------------ | \--* LCL_VAR long V03 loc0
[000088] -A---------- * ASG long
[000087] D------N---- \--* LCL_VAR long V03 loc0
Morphing BB06 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB06, stmt 9 (before)
[000067] ------------ * JTRUE void
[000065] ------------ | /--* CNS_INT int 0
[000066] ------------ \--* GT int
[000064] ------------ \--* LCL_VAR int V02 arg2
Morphing BB07 of 'GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int'
fgMorphTree BB07, stmt 10 (before)
[000093] ------------ /--* CAST long <- int
[000092] ------------ | \--* CNS_INT int 8
[000094] ------------ /--* SUB long
[000091] ------------ | \--* LCL_VAR long V03 loc0
[000096] -A---------- * ASG long
[000095] D------N---- \--* LCL_VAR long V03 loc0
fgMorphTree BB07, stmt 11 (before)
[000110] ---XG------- /--* CAST int <- long
[000109] ---XG------- | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG------- | | /--* IND long
[000106] ------------ | | | \--* LCL_VAR long V03 loc0
[000108] ---XG------- | \--* HWIntrinsic long ParallelBitDeposit
[000103] ------------ | | /--* CNS_INT int 63
[000104] ------------ | | /--* AND int
[000101] ------------ | | | | /--* CNS_INT int 1
[000102] ------------ | | | \--* SUB int
[000100] ------------ | | | \--* LCL_VAR int V04 loc1
[000105] ------------ | \--* LSH long
[000099] ------------ | \--* CAST long <- int
[000098] ------------ | \--* CNS_INT int 1
[000112] -A-XG------- * ASG int
[000111] D------N---- \--* LCL_VAR int V05 loc2
fgMorphTree BB07, stmt 11 (after)
[000110] ---XG+------ /--* CAST int <- long
[000109] ---XG+------ | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG+------ | | /--* IND long
[000106] -----+------ | | | \--* LCL_VAR long V03 loc0
[000108] ---XG+------ | \--* HWIntrinsic long ParallelBitDeposit
[000103] -----+------ | | /--* CNS_INT int 63
[000104] -----+------ | | /--* AND int
[000101] -----+------ | | | | /--* CNS_INT int -1
[000102] -----+------ | | | \--* ADD int
[000100] -----+------ | | | \--* LCL_VAR int V04 loc1
[000105] -----+------ | \--* LSH long
[000099] -----+------ | \--* CAST long <- int
[000098] -----+------ | \--* CNS_INT int 1
[000112] -A-XG+------ * ASG int
[000111] D----+-N---- \--* LCL_VAR int V05 loc2
fgMorphTree BB07, stmt 12 (before)
[000126] ---X-------- * RETURN int
[000124] ------------ | /--* LCL_VAR int V05 loc2
[000125] ---X-------- \--* ADD int
[000123] ---X-------- \--* CAST int <- long
[000121] ------------ | /--* CAST long <- int
[000120] ------------ | | \--* CNS_INT int 64
[000122] ---X-------- \--* MUL long
[000118] ------------ | /--* CAST long <- int
[000117] ------------ | | \--* CNS_INT int 8
[000119] ---X-------- \--* DIV long
[000115] ------------ | /--* LCL_VAR long V00 arg0
[000116] ------------ \--* SUB long
[000114] ------------ \--* LCL_VAR long V03 loc0
fgMorphTree BB07, stmt 12 (after)
[000126] ---X-+------ * RETURN int
[000124] -----+------ | /--* LCL_VAR int V05 loc2
[000125] ---X-+------ \--* ADD int
[000121] -----+------ | /--* NOP int
[000120] -----+------ | | \--* CNS_INT int 64
[000122] ---X-+------ \--* MUL int
[000134] ---X-+------ \--* CAST int <- long
[000118] -----+------ | /--* CAST long <- int
[000117] -----+------ | | \--* CNS_INT int 8
[000119] ---X-+------ \--* DIV long
[000115] -----+------ | /--* LCL_VAR long V00 arg0
[000116] -----+------ \--* SUB long
[000114] -----+------ \--* LCL_VAR long V03 loc0
Renumbering the basic blocks for fgComputePred
*************** Before renumbering the basic blocks
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i
BB02 [0001] 1 1 [004..03B) i bwd
BB03 [0002] 2 1 [03B..043)-> BB02 ( cond ) i bwd
BB04 [0003] 1 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 1 [047..059) i bwd
BB06 [0005] 2 1 [059..05D)-> BB05 ( cond ) i bwd
BB07 [0006] 1 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** After renumbering the basic blocks
=============== No blocks renumbered!
*************** In fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i
BB02 [0001] 1 1 [004..03B) i bwd
BB03 [0002] 2 1 [03B..043)-> BB02 ( cond ) i bwd
BB04 [0003] 1 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 1 [047..059) i bwd
BB06 [0005] 2 1 [059..05D)-> BB05 ( cond ) i bwd
BB07 [0006] 1 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** After fgComputePreds()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgComputeBlockAndEdgeWeights()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
-- no profile data, so using default called count
-- not optimizing, so not computing edge weights
*************** In fgCreateFunclets()
After fgCreateFunclets()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
*************** Exception Handling table is empty
*************** In fgDebugCheckBBlist
*************** In Allocate Objects
Trees before Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
***** BB01, stmt 1
[000004] ------------ * STMT void (IL 0x000...0x001)
[000001] -----+------ | /--* LCL_VAR long V00 arg0
[000003] -A---+------ \--* ASG long
[000002] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
***** BB02, stmt 2
[000047] ------------ * STMT void (IL 0x004...0x032)
[000129] ---XG+------ | /--* CAST int <- long
[000041] ---XG+------ | | \--* HWIntrinsic long PopCount
[000040] *--XG+------ | | \--* IND long
[000037] -----+------ | | | /--* CAST long <- int
[000036] -----+------ | | | | \--* CNS_INT int 8
[000038] -----+------ | | | /--* MUL long
[000035] -----+------ | | | | \--* CAST long <- int
[000034] -----+------ | | | | \--* CNS_INT int 3
[000039] -----+------ | | \--* ADD long
[000033] -----+------ | | \--* LCL_VAR long V03 loc0
[000042] ---XG+------ | /--* ADD int
[000131] ---XG+------ | | | /--* CAST int <- long
[000031] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000030] *--XG+------ | | | | \--* IND long
[000027] -----+------ | | | | | /--* CAST long <- int
[000026] -----+------ | | | | | | \--* CNS_INT int 8
[000028] -----+------ | | | | | /--* MUL long
[000025] -----+------ | | | | | | \--* CAST long <- int
[000024] -----+------ | | | | | | \--* CNS_INT int 2
[000029] -----+------ | | | | \--* ADD long
[000023] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000032] ---XG+------ | | \--* ADD int
[000133] ---XG+------ | | | /--* CAST int <- long
[000021] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000020] *--XG+------ | | | | \--* IND long
[000018] -----+------ | | | | | /--* CAST long <- int
[000017] -----+------ | | | | | | \--* CNS_INT int 8
[000019] -----+------ | | | | \--* ADD long
[000016] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000022] ---XG+------ | | \--* ADD int
[000132] ---XG+------ | | \--* CAST int <- long
[000015] ---XG+------ | | \--* HWIntrinsic long PopCount
[000014] *--XG+------ | | \--* IND long
[000013] -----+------ | | \--* LCL_VAR long V03 loc0
[000044] ---XG+------ | /--* SUB int
[000012] -----+------ | | \--* LCL_VAR int V02 arg2
[000046] -A-XG+------ \--* ASG int
[000045] D----+-N---- \--* LCL_VAR int V02 arg2
***** BB02, stmt 3
[000057] ------------ * STMT void (IL 0x034...0x03A)
[000052] -----+------ | /--* CAST long <- int
[000051] -----+------ | | \--* CNS_INT int 8
[000053] -----+------ | /--* MUL long
[000050] -----+------ | | \--* CAST long <- int
[000049] -----+------ | | \--* CNS_INT int 4
[000054] -----+------ | /--* ADD long
[000048] -----+------ | | \--* LCL_VAR long V03 loc0
[000056] -A---+------ \--* ASG long
[000055] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
***** BB03, stmt 4
[000010] ------------ * STMT void (IL 0x03B...0x041)
[000009] -----+------ \--* JTRUE void
[000007] -----+------ | /--* CNS_INT int 256
[000008] J----+-N---- \--* GE int
[000006] -----+------ \--* LCL_VAR int V02 arg2
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
***** BB04, stmt 5
[000062] ------------ * STMT void (IL 0x043...0x044)
[000059] -----+------ | /--* LCL_VAR int V02 arg2
[000061] -A---+------ \--* ASG int
[000060] D----+-N---- \--* LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
***** BB05, stmt 6
[000073] ------------ * STMT void (IL 0x047...0x048)
[000070] -----+------ | /--* LCL_VAR int V02 arg2
[000072] -A---+------ \--* ASG int
[000071] D----+-N---- \--* LCL_VAR int V04 loc1
***** BB05, stmt 7
[000082] ------------ * STMT void (IL 0x049...0x053)
[000078] ---XG+------ | /--* CAST int <- long
[000077] ---XG+------ | | \--* HWIntrinsic long PopCount
[000076] *--XG+------ | | \--* IND long
[000075] -----+------ | | \--* LCL_VAR long V03 loc0
[000079] ---XG+------ | /--* SUB int
[000074] -----+------ | | \--* LCL_VAR int V02 arg2
[000081] -A-XG+------ \--* ASG int
[000080] D----+-N---- \--* LCL_VAR int V02 arg2
***** BB05, stmt 8
[000089] ------------ * STMT void (IL 0x055...0x058)
[000085] -----+------ | /--* CAST long <- int
[000084] -----+------ | | \--* CNS_INT int 8
[000086] -----+------ | /--* ADD long
[000083] -----+------ | | \--* LCL_VAR long V03 loc0
[000088] -A---+------ \--* ASG long
[000087] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
***** BB06, stmt 9
[000068] ------------ * STMT void (IL 0x059...0x05B)
[000067] -----+------ \--* JTRUE void
[000065] -----+------ | /--* CNS_INT int 0
[000066] J----+-N---- \--* GT int
[000064] -----+------ \--* LCL_VAR int V02 arg2
------------ BB07 [05D..086) (return), preds={BB06} succs={}
***** BB07, stmt 10
[000097] ------------ * STMT void (IL 0x05D...0x060)
[000093] -----+------ | /--* CAST long <- int
[000092] -----+------ | | \--* CNS_INT int 8
[000094] -----+------ | /--* SUB long
[000091] -----+------ | | \--* LCL_VAR long V03 loc0
[000096] -A---+------ \--* ASG long
[000095] D----+-N---- \--* LCL_VAR long V03 loc0
***** BB07, stmt 11
[000113] ------------ * STMT void (IL 0x061...0x077)
[000110] ---XG+------ | /--* CAST int <- long
[000109] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG+------ | | | /--* IND long
[000106] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000108] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000103] -----+------ | | | /--* CNS_INT int 63
[000104] -----+------ | | | /--* AND int
[000101] -----+------ | | | | | /--* CNS_INT int -1
[000102] -----+------ | | | | \--* ADD int
[000100] -----+------ | | | | \--* LCL_VAR int V04 loc1
[000105] -----+------ | | \--* LSH long
[000099] -----+------ | | \--* CAST long <- int
[000098] -----+------ | | \--* CNS_INT int 1
[000112] -A-XG+------ \--* ASG int
[000111] D----+-N---- \--* LCL_VAR int V05 loc2
***** BB07, stmt 12
[000127] ------------ * STMT void (IL 0x078...0x085)
[000126] ---X-+------ \--* RETURN int
[000124] -----+------ | /--* LCL_VAR int V05 loc2
[000125] ---X-+------ \--* ADD int
[000121] -----+------ | /--* NOP int
[000120] -----+------ | | \--* CNS_INT int 64
[000122] ---X-+------ \--* MUL int
[000134] ---X-+------ \--* CAST int <- long
[000118] -----+------ | /--* CAST long <- int
[000117] -----+------ | | \--* CNS_INT int 8
[000119] ---X-+------ \--* DIV long
[000115] -----+------ | /--* LCL_VAR long V00 arg0
[000116] -----+------ \--* SUB long
[000114] -----+------ \--* LCL_VAR long V03 loc0
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Allocate Objects
Trees after Allocate Objects
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
***** BB01, stmt 1
[000004] ------------ * STMT void (IL 0x000...0x001)
[000001] -----+------ | /--* LCL_VAR long V00 arg0
[000003] -A---+------ \--* ASG long
[000002] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
***** BB02, stmt 2
[000047] ------------ * STMT void (IL 0x004...0x032)
[000129] ---XG+------ | /--* CAST int <- long
[000041] ---XG+------ | | \--* HWIntrinsic long PopCount
[000040] *--XG+------ | | \--* IND long
[000037] -----+------ | | | /--* CAST long <- int
[000036] -----+------ | | | | \--* CNS_INT int 8
[000038] -----+------ | | | /--* MUL long
[000035] -----+------ | | | | \--* CAST long <- int
[000034] -----+------ | | | | \--* CNS_INT int 3
[000039] -----+------ | | \--* ADD long
[000033] -----+------ | | \--* LCL_VAR long V03 loc0
[000042] ---XG+------ | /--* ADD int
[000131] ---XG+------ | | | /--* CAST int <- long
[000031] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000030] *--XG+------ | | | | \--* IND long
[000027] -----+------ | | | | | /--* CAST long <- int
[000026] -----+------ | | | | | | \--* CNS_INT int 8
[000028] -----+------ | | | | | /--* MUL long
[000025] -----+------ | | | | | | \--* CAST long <- int
[000024] -----+------ | | | | | | \--* CNS_INT int 2
[000029] -----+------ | | | | \--* ADD long
[000023] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000032] ---XG+------ | | \--* ADD int
[000133] ---XG+------ | | | /--* CAST int <- long
[000021] ---XG+------ | | | | \--* HWIntrinsic long PopCount
[000020] *--XG+------ | | | | \--* IND long
[000018] -----+------ | | | | | /--* CAST long <- int
[000017] -----+------ | | | | | | \--* CNS_INT int 8
[000019] -----+------ | | | | \--* ADD long
[000016] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000022] ---XG+------ | | \--* ADD int
[000132] ---XG+------ | | \--* CAST int <- long
[000015] ---XG+------ | | \--* HWIntrinsic long PopCount
[000014] *--XG+------ | | \--* IND long
[000013] -----+------ | | \--* LCL_VAR long V03 loc0
[000044] ---XG+------ | /--* SUB int
[000012] -----+------ | | \--* LCL_VAR int V02 arg2
[000046] -A-XG+------ \--* ASG int
[000045] D----+-N---- \--* LCL_VAR int V02 arg2
***** BB02, stmt 3
[000057] ------------ * STMT void (IL 0x034...0x03A)
[000052] -----+------ | /--* CAST long <- int
[000051] -----+------ | | \--* CNS_INT int 8
[000053] -----+------ | /--* MUL long
[000050] -----+------ | | \--* CAST long <- int
[000049] -----+------ | | \--* CNS_INT int 4
[000054] -----+------ | /--* ADD long
[000048] -----+------ | | \--* LCL_VAR long V03 loc0
[000056] -A---+------ \--* ASG long
[000055] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
***** BB03, stmt 4
[000010] ------------ * STMT void (IL 0x03B...0x041)
[000009] -----+------ \--* JTRUE void
[000007] -----+------ | /--* CNS_INT int 256
[000008] J----+-N---- \--* GE int
[000006] -----+------ \--* LCL_VAR int V02 arg2
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
***** BB04, stmt 5
[000062] ------------ * STMT void (IL 0x043...0x044)
[000059] -----+------ | /--* LCL_VAR int V02 arg2
[000061] -A---+------ \--* ASG int
[000060] D----+-N---- \--* LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
***** BB05, stmt 6
[000073] ------------ * STMT void (IL 0x047...0x048)
[000070] -----+------ | /--* LCL_VAR int V02 arg2
[000072] -A---+------ \--* ASG int
[000071] D----+-N---- \--* LCL_VAR int V04 loc1
***** BB05, stmt 7
[000082] ------------ * STMT void (IL 0x049...0x053)
[000078] ---XG+------ | /--* CAST int <- long
[000077] ---XG+------ | | \--* HWIntrinsic long PopCount
[000076] *--XG+------ | | \--* IND long
[000075] -----+------ | | \--* LCL_VAR long V03 loc0
[000079] ---XG+------ | /--* SUB int
[000074] -----+------ | | \--* LCL_VAR int V02 arg2
[000081] -A-XG+------ \--* ASG int
[000080] D----+-N---- \--* LCL_VAR int V02 arg2
***** BB05, stmt 8
[000089] ------------ * STMT void (IL 0x055...0x058)
[000085] -----+------ | /--* CAST long <- int
[000084] -----+------ | | \--* CNS_INT int 8
[000086] -----+------ | /--* ADD long
[000083] -----+------ | | \--* LCL_VAR long V03 loc0
[000088] -A---+------ \--* ASG long
[000087] D----+-N---- \--* LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
***** BB06, stmt 9
[000068] ------------ * STMT void (IL 0x059...0x05B)
[000067] -----+------ \--* JTRUE void
[000065] -----+------ | /--* CNS_INT int 0
[000066] J----+-N---- \--* GT int
[000064] -----+------ \--* LCL_VAR int V02 arg2
------------ BB07 [05D..086) (return), preds={BB06} succs={}
***** BB07, stmt 10
[000097] ------------ * STMT void (IL 0x05D...0x060)
[000093] -----+------ | /--* CAST long <- int
[000092] -----+------ | | \--* CNS_INT int 8
[000094] -----+------ | /--* SUB long
[000091] -----+------ | | \--* LCL_VAR long V03 loc0
[000096] -A---+------ \--* ASG long
[000095] D----+-N---- \--* LCL_VAR long V03 loc0
***** BB07, stmt 11
[000113] ------------ * STMT void (IL 0x061...0x077)
[000110] ---XG+------ | /--* CAST int <- long
[000109] ---XG+------ | | \--* HWIntrinsic long TrailingZeroCount
[000107] *--XG+------ | | | /--* IND long
[000106] -----+------ | | | | \--* LCL_VAR long V03 loc0
[000108] ---XG+------ | | \--* HWIntrinsic long ParallelBitDeposit
[000103] -----+------ | | | /--* CNS_INT int 63
[000104] -----+------ | | | /--* AND int
[000101] -----+------ | | | | | /--* CNS_INT int -1
[000102] -----+------ | | | | \--* ADD int
[000100] -----+------ | | | | \--* LCL_VAR int V04 loc1
[000105] -----+------ | | \--* LSH long
[000099] -----+------ | | \--* CAST long <- int
[000098] -----+------ | | \--* CNS_INT int 1
[000112] -A-XG+------ \--* ASG int
[000111] D----+-N---- \--* LCL_VAR int V05 loc2
***** BB07, stmt 12
[000127] ------------ * STMT void (IL 0x078...0x085)
[000126] ---X-+------ \--* RETURN int
[000124] -----+------ | /--* LCL_VAR int V05 loc2
[000125] ---X-+------ \--* ADD int
[000121] -----+------ | /--* NOP int
[000120] -----+------ | | \--* CNS_INT int 64
[000122] ---X-+------ \--* MUL int
[000134] ---X-+------ \--* CAST int <- long
[000118] -----+------ | /--* CAST long <- int
[000117] -----+------ | | \--* CNS_INT int 8
[000119] ---X-+------ \--* DIV long
[000115] -----+------ | /--* LCL_VAR long V00 arg0
[000116] -----+------ \--* SUB long
[000114] -----+------ \--* LCL_VAR long V03 loc0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***
*************** In fgFindOperOrder()
*************** In fgSetBlockOrder()
The biggest BB has 38 tree nodes
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
***** BB01, stmt 1
( 7, 5) [000004] ------------ * STMT void (IL 0x000...0x001)
N001 ( 3, 2) [000001] ------------ | /--* LCL_VAR long V00 arg0
N003 ( 7, 5) [000003] -A------R--- \--* ASG long
N002 ( 3, 2) [000002] D------N---- \--* LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
***** BB02, stmt 2
( 61, 58) [000047] ------------ * STMT void (IL 0x004...0x032)
N033 ( 16, 16) [000129] ---XG------- | /--* CAST int <- long
N032 ( 15, 14) [000041] ---XG------- | | \--* HWIntrinsic long PopCount
N031 ( 14, 13) [000040] *--XG------- | | \--* IND long
N028 ( 2, 3) [000037] ------------ | | | /--* CAST long <- int
N027 ( 1, 1) [000036] ------------ | | | | \--* CNS_INT int 8
N029 ( 8, 9) [000038] ------------ | | | /--* MUL long
N026 ( 2, 3) [000035] ------------ | | | | \--* CAST long <- int
N025 ( 1, 1) [000034] ------------ | | | | \--* CNS_INT int 3
N030 ( 11, 11) [000039] -------N---- | | \--* ADD long
N024 ( 3, 2) [000033] ------------ | | \--* LCL_VAR long V03 loc0
N034 ( 53, 52) [000042] ---XG------- | /--* ADD int
N022 ( 16, 16) [000131] ---XG------- | | | /--* CAST int <- long
N021 ( 15, 14) [000031] ---XG------- | | | | \--* HWIntrinsic long PopCount
N020 ( 14, 13) [000030] *--XG------- | | | | \--* IND long
N017 ( 2, 3) [000027] ------------ | | | | | /--* CAST long <- int
N016 ( 1, 1) [000026] ------------ | | | | | | \--* CNS_INT int 8
N018 ( 8, 9) [000028] ------------ | | | | | /--* MUL long
N015 ( 2, 3) [000025] ------------ | | | | | | \--* CAST long <- int
N014 ( 1, 1) [000024] ------------ | | | | | | \--* CNS_INT int 2
N019 ( 11, 11) [000029] -------N---- | | | | \--* ADD long
N013 ( 3, 2) [000023] ------------ | | | | \--* LCL_VAR long V03 loc0
N023 ( 36, 35) [000032] ---XG------- | | \--* ADD int
N011 ( 10, 10) [000133] ---XG------- | | | /--* CAST int <- long
N010 ( 9, 8) [000021] ---XG------- | | | | \--* HWIntrinsic long PopCount
N009 ( 8, 7) [000020] *--XG------- | | | | \--* IND long
N007 ( 2, 3) [000018] ------------ | | | | | /--* CAST long <- int
N006 ( 1, 1) [000017] ------------ | | | | | | \--* CNS_INT int 8
N008 ( 5, 5) [000019] -------N---- | | | | \--* ADD long
N005 ( 3, 2) [000016] ------------ | | | | \--* LCL_VAR long V03 loc0
N012 ( 19, 18) [000022] ---XG------- | | \--* ADD int
N004 ( 8, 7) [000132] ---XG------- | | \--* CAST int <- long
N003 ( 7, 5) [000015] ---XG------- | | \--* HWIntrinsic long PopCount
N002 ( 6, 4) [000014] *--XG------- | | \--* IND long
N001 ( 3, 2) [000013] ------------ | | \--* LCL_VAR long V03 loc0
N036 ( 57, 55) [000044] ---XG---R--- | /--* SUB int
N035 ( 3, 2) [000012] ------------ | | \--* LCL_VAR int V02 arg2
N038 ( 61, 58) [000046] -A-XG---R--- \--* ASG int
N037 ( 3, 2) [000045] D------N---- \--* LCL_VAR int V02 arg2
***** BB02, stmt 3
( 16, 15) [000057] ------------ * STMT void (IL 0x034...0x03A)
N005 ( 2, 3) [000052] ------------ | /--* CAST long <- int
N004 ( 1, 1) [000051] ------------ | | \--* CNS_INT int 8
N006 ( 8, 9) [000053] ------------ | /--* MUL long
N003 ( 2, 3) [000050] ------------ | | \--* CAST long <- int
N002 ( 1, 1) [000049] ------------ | | \--* CNS_INT int 4
N007 ( 12, 12) [000054] ------------ | /--* ADD long
N001 ( 3, 2) [000048] ------------ | | \--* LCL_VAR long V03 loc0
N009 ( 16, 15) [000056] -A------R--- \--* ASG long
N008 ( 3, 2) [000055] D------N---- \--* LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
***** BB03, stmt 4
( 7, 9) [000010] ------------ * STMT void (IL 0x03B...0x041)
N004 ( 7, 9) [000009] ------------ \--* JTRUE void
N002 ( 1, 4) [000007] ------------ | /--* CNS_INT int 256
N003 ( 5, 7) [000008] J------N---- \--* GE int
N001 ( 3, 2) [000006] ------------ \--* LCL_VAR int V02 arg2
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
***** BB04, stmt 5
( 7, 5) [000062] ------------ * STMT void (IL 0x043...0x044)
N001 ( 3, 2) [000059] ------------ | /--* LCL_VAR int V02 arg2
N003 ( 7, 5) [000061] -A------R--- \--* ASG int
N002 ( 3, 2) [000060] D------N---- \--* LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
***** BB05, stmt 6
( 7, 5) [000073] ------------ * STMT void (IL 0x047...0x048)
N001 ( 3, 2) [000070] ------------ | /--* LCL_VAR int V02 arg2
N003 ( 7, 5) [000072] -A------R--- \--* ASG int
N002 ( 3, 2) [000071] D------N---- \--* LCL_VAR int V04 loc1
***** BB05, stmt 7
( 16, 13) [000082] ------------ * STMT void (IL 0x049...0x053)
N005 ( 8, 7) [000078] ---XG------- | /--* CAST int <- long
N004 ( 7, 5) [000077] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 6, 4) [000076] *--XG------- | | \--* IND long
N002 ( 3, 2) [000075] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 12, 10) [000079] ---XG------- | /--* SUB int
N001 ( 3, 2) [000074] ------------ | | \--* LCL_VAR int V02 arg2
N008 ( 16, 13) [000081] -A-XG---R--- \--* ASG int
N007 ( 3, 2) [000080] D------N---- \--* LCL_VAR int V02 arg2
***** BB05, stmt 8
( 10, 9) [000089] ------------ * STMT void (IL 0x055...0x058)
N003 ( 2, 3) [000085] ------------ | /--* CAST long <- int
N002 ( 1, 1) [000084] ------------ | | \--* CNS_INT int 8
N004 ( 6, 6) [000086] ------------ | /--* ADD long
N001 ( 3, 2) [000083] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 10, 9) [000088] -A------R--- \--* ASG long
N005 ( 3, 2) [000087] D------N---- \--* LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
***** BB06, stmt 9
( 7, 6) [000068] ------------ * STMT void (IL 0x059...0x05B)
N004 ( 7, 6) [000067] ------------ \--* JTRUE void
N002 ( 1, 1) [000065] ------------ | /--* CNS_INT int 0
N003 ( 5, 4) [000066] J------N---- \--* GT int
N001 ( 3, 2) [000064] ------------ \--* LCL_VAR int V02 arg2
------------ BB07 [05D..086) (return), preds={BB06} succs={}
***** BB07, stmt 10
( 10, 9) [000097] ------------ * STMT void (IL 0x05D...0x060)
N003 ( 2, 3) [000093] ------------ | /--* CAST long <- int
N002 ( 1, 1) [000092] ------------ | | \--* CNS_INT int 8
N004 ( 6, 6) [000094] ------------ | /--* SUB long
N001 ( 3, 2) [000091] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 10, 9) [000096] -A------R--- \--* ASG long
N005 ( 3, 2) [000095] D------N---- \--* LCL_VAR long V03 loc0
***** BB07, stmt 11
( 26, 21) [000113] ------------ * STMT void (IL 0x061...0x077)
N013 ( 22, 18) [000110] ---XG------- | /--* CAST int <- long
N012 ( 21, 16) [000109] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
N010 ( 6, 4) [000107] *--XG------- | | | /--* IND long
N009 ( 3, 2) [000106] ------------ | | | | \--* LCL_VAR long V03 loc0
N011 ( 20, 15) [000108] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000103] ------------ | | | /--* CNS_INT int 63
N005 ( 7, 6) [000104] ------------ | | | /--* AND int
N002 ( 1, 1) [000101] ------------ | | | | | /--* CNS_INT int -1
N003 ( 5, 4) [000102] ------------ | | | | \--* ADD int
N001 ( 3, 2) [000100] ------------ | | | | \--* LCL_VAR int V04 loc1
N008 ( 13, 10) [000105] --------R--- | | \--* LSH long
N007 ( 2, 3) [000099] ------------ | | \--* CAST long <- int
N006 ( 1, 1) [000098] ------------ | | \--* CNS_INT int 1
N015 ( 26, 21) [000112] -A-XG---R--- \--* ASG int
N014 ( 3, 2) [000111] D------N---- \--* LCL_VAR int V05 loc2
***** BB07, stmt 12
( 40, 21) [000127] ------------ * STMT void (IL 0x078...0x085)
N013 ( 40, 21) [000126] ---X-------- \--* RETURN int
N011 ( 3, 2) [000124] ------------ | /--* LCL_VAR int V05 loc2
N012 ( 39, 20) [000125] ---X-------- \--* ADD int
N009 ( 1, 1) [000121] ------------ | /--* NOP int
N008 ( 1, 1) [000120] ------------ | | \--* CNS_INT int 64
N010 ( 35, 17) [000122] ---X-------- \--* MUL int
N007 ( 30, 13) [000134] ---X-------- \--* CAST int <- long
N005 ( 2, 3) [000118] ------------ | /--* CAST long <- int
N004 ( 1, 1) [000117] ------------ | | \--* CNS_INT int 8
N006 ( 29, 11) [000119] ---X-------- \--* DIV long
N002 ( 3, 2) [000115] ------------ | /--* LCL_VAR long V00 arg0
N003 ( 7, 5) [000116] ------------ \--* SUB long
N001 ( 3, 2) [000114] ------------ \--* LCL_VAR long V03 loc0
-------------------------------------------------------------------------------------------------------------------
*************** In fgDetermineFirstColdBlock()
No procedure splitting will be done for this method
*************** In IR Rationalize
Trees before IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i
BB05 [0004] 1 BB06 1 [047..059) i label target bwd
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd
BB07 [0006] 1 BB06 1 [05D..086) (return) i
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
***** BB01, stmt 1
( 7, 5) [000004] ------------ * STMT void (IL 0x000...0x001)
N001 ( 3, 2) [000001] ------------ | /--* LCL_VAR long V00 arg0
N003 ( 7, 5) [000003] -A------R--- \--* ASG long
N002 ( 3, 2) [000002] D------N---- \--* LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
***** BB02, stmt 2
( 61, 58) [000047] ------------ * STMT void (IL 0x004...0x032)
N033 ( 16, 16) [000129] ---XG------- | /--* CAST int <- long
N032 ( 15, 14) [000041] ---XG------- | | \--* HWIntrinsic long PopCount
N031 ( 14, 13) [000040] *--XG------- | | \--* IND long
N028 ( 2, 3) [000037] ------------ | | | /--* CAST long <- int
N027 ( 1, 1) [000036] ------------ | | | | \--* CNS_INT int 8
N029 ( 8, 9) [000038] ------------ | | | /--* MUL long
N026 ( 2, 3) [000035] ------------ | | | | \--* CAST long <- int
N025 ( 1, 1) [000034] ------------ | | | | \--* CNS_INT int 3
N030 ( 11, 11) [000039] -------N---- | | \--* ADD long
N024 ( 3, 2) [000033] ------------ | | \--* LCL_VAR long V03 loc0
N034 ( 53, 52) [000042] ---XG------- | /--* ADD int
N022 ( 16, 16) [000131] ---XG------- | | | /--* CAST int <- long
N021 ( 15, 14) [000031] ---XG------- | | | | \--* HWIntrinsic long PopCount
N020 ( 14, 13) [000030] *--XG------- | | | | \--* IND long
N017 ( 2, 3) [000027] ------------ | | | | | /--* CAST long <- int
N016 ( 1, 1) [000026] ------------ | | | | | | \--* CNS_INT int 8
N018 ( 8, 9) [000028] ------------ | | | | | /--* MUL long
N015 ( 2, 3) [000025] ------------ | | | | | | \--* CAST long <- int
N014 ( 1, 1) [000024] ------------ | | | | | | \--* CNS_INT int 2
N019 ( 11, 11) [000029] -------N---- | | | | \--* ADD long
N013 ( 3, 2) [000023] ------------ | | | | \--* LCL_VAR long V03 loc0
N023 ( 36, 35) [000032] ---XG------- | | \--* ADD int
N011 ( 10, 10) [000133] ---XG------- | | | /--* CAST int <- long
N010 ( 9, 8) [000021] ---XG------- | | | | \--* HWIntrinsic long PopCount
N009 ( 8, 7) [000020] *--XG------- | | | | \--* IND long
N007 ( 2, 3) [000018] ------------ | | | | | /--* CAST long <- int
N006 ( 1, 1) [000017] ------------ | | | | | | \--* CNS_INT int 8
N008 ( 5, 5) [000019] -------N---- | | | | \--* ADD long
N005 ( 3, 2) [000016] ------------ | | | | \--* LCL_VAR long V03 loc0
N012 ( 19, 18) [000022] ---XG------- | | \--* ADD int
N004 ( 8, 7) [000132] ---XG------- | | \--* CAST int <- long
N003 ( 7, 5) [000015] ---XG------- | | \--* HWIntrinsic long PopCount
N002 ( 6, 4) [000014] *--XG------- | | \--* IND long
N001 ( 3, 2) [000013] ------------ | | \--* LCL_VAR long V03 loc0
N036 ( 57, 55) [000044] ---XG---R--- | /--* SUB int
N035 ( 3, 2) [000012] ------------ | | \--* LCL_VAR int V02 arg2
N038 ( 61, 58) [000046] -A-XG---R--- \--* ASG int
N037 ( 3, 2) [000045] D------N---- \--* LCL_VAR int V02 arg2
***** BB02, stmt 3
( 16, 15) [000057] ------------ * STMT void (IL 0x034...0x03A)
N005 ( 2, 3) [000052] ------------ | /--* CAST long <- int
N004 ( 1, 1) [000051] ------------ | | \--* CNS_INT int 8
N006 ( 8, 9) [000053] ------------ | /--* MUL long
N003 ( 2, 3) [000050] ------------ | | \--* CAST long <- int
N002 ( 1, 1) [000049] ------------ | | \--* CNS_INT int 4
N007 ( 12, 12) [000054] ------------ | /--* ADD long
N001 ( 3, 2) [000048] ------------ | | \--* LCL_VAR long V03 loc0
N009 ( 16, 15) [000056] -A------R--- \--* ASG long
N008 ( 3, 2) [000055] D------N---- \--* LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
***** BB03, stmt 4
( 7, 9) [000010] ------------ * STMT void (IL 0x03B...0x041)
N004 ( 7, 9) [000009] ------------ \--* JTRUE void
N002 ( 1, 4) [000007] ------------ | /--* CNS_INT int 256
N003 ( 5, 7) [000008] J------N---- \--* GE int
N001 ( 3, 2) [000006] ------------ \--* LCL_VAR int V02 arg2
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
***** BB04, stmt 5
( 7, 5) [000062] ------------ * STMT void (IL 0x043...0x044)
N001 ( 3, 2) [000059] ------------ | /--* LCL_VAR int V02 arg2
N003 ( 7, 5) [000061] -A------R--- \--* ASG int
N002 ( 3, 2) [000060] D------N---- \--* LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
***** BB05, stmt 6
( 7, 5) [000073] ------------ * STMT void (IL 0x047...0x048)
N001 ( 3, 2) [000070] ------------ | /--* LCL_VAR int V02 arg2
N003 ( 7, 5) [000072] -A------R--- \--* ASG int
N002 ( 3, 2) [000071] D------N---- \--* LCL_VAR int V04 loc1
***** BB05, stmt 7
( 16, 13) [000082] ------------ * STMT void (IL 0x049...0x053)
N005 ( 8, 7) [000078] ---XG------- | /--* CAST int <- long
N004 ( 7, 5) [000077] ---XG------- | | \--* HWIntrinsic long PopCount
N003 ( 6, 4) [000076] *--XG------- | | \--* IND long
N002 ( 3, 2) [000075] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 12, 10) [000079] ---XG------- | /--* SUB int
N001 ( 3, 2) [000074] ------------ | | \--* LCL_VAR int V02 arg2
N008 ( 16, 13) [000081] -A-XG---R--- \--* ASG int
N007 ( 3, 2) [000080] D------N---- \--* LCL_VAR int V02 arg2
***** BB05, stmt 8
( 10, 9) [000089] ------------ * STMT void (IL 0x055...0x058)
N003 ( 2, 3) [000085] ------------ | /--* CAST long <- int
N002 ( 1, 1) [000084] ------------ | | \--* CNS_INT int 8
N004 ( 6, 6) [000086] ------------ | /--* ADD long
N001 ( 3, 2) [000083] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 10, 9) [000088] -A------R--- \--* ASG long
N005 ( 3, 2) [000087] D------N---- \--* LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
***** BB06, stmt 9
( 7, 6) [000068] ------------ * STMT void (IL 0x059...0x05B)
N004 ( 7, 6) [000067] ------------ \--* JTRUE void
N002 ( 1, 1) [000065] ------------ | /--* CNS_INT int 0
N003 ( 5, 4) [000066] J------N---- \--* GT int
N001 ( 3, 2) [000064] ------------ \--* LCL_VAR int V02 arg2
------------ BB07 [05D..086) (return), preds={BB06} succs={}
***** BB07, stmt 10
( 10, 9) [000097] ------------ * STMT void (IL 0x05D...0x060)
N003 ( 2, 3) [000093] ------------ | /--* CAST long <- int
N002 ( 1, 1) [000092] ------------ | | \--* CNS_INT int 8
N004 ( 6, 6) [000094] ------------ | /--* SUB long
N001 ( 3, 2) [000091] ------------ | | \--* LCL_VAR long V03 loc0
N006 ( 10, 9) [000096] -A------R--- \--* ASG long
N005 ( 3, 2) [000095] D------N---- \--* LCL_VAR long V03 loc0
***** BB07, stmt 11
( 26, 21) [000113] ------------ * STMT void (IL 0x061...0x077)
N013 ( 22, 18) [000110] ---XG------- | /--* CAST int <- long
N012 ( 21, 16) [000109] ---XG------- | | \--* HWIntrinsic long TrailingZeroCount
N010 ( 6, 4) [000107] *--XG------- | | | /--* IND long
N009 ( 3, 2) [000106] ------------ | | | | \--* LCL_VAR long V03 loc0
N011 ( 20, 15) [000108] ---XG------- | | \--* HWIntrinsic long ParallelBitDeposit
N004 ( 1, 1) [000103] ------------ | | | /--* CNS_INT int 63
N005 ( 7, 6) [000104] ------------ | | | /--* AND int
N002 ( 1, 1) [000101] ------------ | | | | | /--* CNS_INT int -1
N003 ( 5, 4) [000102] ------------ | | | | \--* ADD int
N001 ( 3, 2) [000100] ------------ | | | | \--* LCL_VAR int V04 loc1
N008 ( 13, 10) [000105] --------R--- | | \--* LSH long
N007 ( 2, 3) [000099] ------------ | | \--* CAST long <- int
N006 ( 1, 1) [000098] ------------ | | \--* CNS_INT int 1
N015 ( 26, 21) [000112] -A-XG---R--- \--* ASG int
N014 ( 3, 2) [000111] D------N---- \--* LCL_VAR int V05 loc2
***** BB07, stmt 12
( 40, 21) [000127] ------------ * STMT void (IL 0x078...0x085)
N013 ( 40, 21) [000126] ---X-------- \--* RETURN int
N011 ( 3, 2) [000124] ------------ | /--* LCL_VAR int V05 loc2
N012 ( 39, 20) [000125] ---X-------- \--* ADD int
N009 ( 1, 1) [000121] ------------ | /--* NOP int
N008 ( 1, 1) [000120] ------------ | | \--* CNS_INT int 64
N010 ( 35, 17) [000122] ---X-------- \--* MUL int
N007 ( 30, 13) [000134] ---X-------- \--* CAST int <- long
N005 ( 2, 3) [000118] ------------ | /--* CAST long <- int
N004 ( 1, 1) [000117] ------------ | | \--* CNS_INT int 8
N006 ( 29, 11) [000119] ---X-------- \--* DIV long
N002 ( 3, 2) [000115] ------------ | /--* LCL_VAR long V00 arg0
N003 ( 7, 5) [000116] ------------ \--* SUB long
N001 ( 3, 2) [000114] ------------ \--* LCL_VAR long V03 loc0
-------------------------------------------------------------------------------------------------------------------
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X)
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
*************** Exiting IR Rationalize
Trees after IR Rationalize
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0
/--* t1 long
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4
N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0
/--* t13 long
N002 ( 6, 4) [000014] *--XG------- t14 = * IND long
/--* t14 long
N003 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount
/--* t15 long
N004 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long
N005 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0
N006 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8
/--* t17 int
N007 ( 2, 3) [000018] ------------ t18 = * CAST long <- int
/--* t16 long
+--* t18 long
N008 ( 5, 5) [000019] -------N---- t19 = * ADD long
/--* t19 long
N009 ( 8, 7) [000020] *--XG------- t20 = * IND long
/--* t20 long
N010 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount
/--* t21 long
N011 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long
/--* t132 int
+--* t133 int
N012 ( 19, 18) [000022] ---XG------- t22 = * ADD int
N013 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0
N014 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2
/--* t24 int
N015 ( 2, 3) [000025] ------------ t25 = * CAST long <- int
N016 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8
/--* t26 int
N017 ( 2, 3) [000027] ------------ t27 = * CAST long <- int
/--* t25 long
+--* t27 long
N018 ( 8, 9) [000028] ------------ t28 = * MUL long
/--* t23 long
+--* t28 long
N019 ( 11, 11) [000029] -------N---- t29 = * ADD long
/--* t29 long
N020 ( 14, 13) [000030] *--XG------- t30 = * IND long
/--* t30 long
N021 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount
/--* t31 long
N022 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long
/--* t22 int
+--* t131 int
N023 ( 36, 35) [000032] ---XG------- t32 = * ADD int
N024 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0
N025 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3
/--* t34 int
N026 ( 2, 3) [000035] ------------ t35 = * CAST long <- int
N027 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8
/--* t36 int
N028 ( 2, 3) [000037] ------------ t37 = * CAST long <- int
/--* t35 long
+--* t37 long
N029 ( 8, 9) [000038] ------------ t38 = * MUL long
/--* t33 long
+--* t38 long
N030 ( 11, 11) [000039] -------N---- t39 = * ADD long
/--* t39 long
N031 ( 14, 13) [000040] *--XG------- t40 = * IND long
/--* t40 long
N032 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount
/--* t41 long
N033 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long
/--* t32 int
+--* t129 int
N034 ( 53, 52) [000042] ---XG------- t42 = * ADD int
N035 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2
/--* t12 int
+--* t42 int
N036 ( 57, 55) [000044] ---XG------- t44 = * SUB int
/--* t44 int
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34
N001 ( 3, 2) [000048] ------------ t48 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4
/--* t49 int
N003 ( 2, 3) [000050] ------------ t50 = * CAST long <- int
N004 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8
/--* t51 int
N005 ( 2, 3) [000052] ------------ t52 = * CAST long <- int
/--* t50 long
+--* t52 long
N006 ( 8, 9) [000053] ------------ t53 = * MUL long
/--* t48 long
+--* t53 long
N007 ( 12, 12) [000054] ------------ t54 = * ADD long
/--* t54 long
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b
N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR int V02 arg2
N002 ( 1, 4) [000007] ------------ t7 = CNS_INT int 256
/--* t6 int
+--* t7 int
N003 ( 5, 7) [000008] J------N---- t8 = * GE int
/--* t8 int
N004 ( 7, 9) [000009] ------------ * JTRUE void
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2
/--* t59 int
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2
/--* t70 int
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49
N001 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2
N002 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0
/--* t75 long
N003 ( 6, 4) [000076] *--XG------- t76 = * IND long
/--* t76 long
N004 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount
/--* t77 long
N005 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long
/--* t74 int
+--* t78 int
N006 ( 12, 10) [000079] ---XG------- t79 = * SUB int
/--* t79 int
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55
N001 ( 3, 2) [000083] ------------ t83 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8
/--* t84 int
N003 ( 2, 3) [000085] ------------ t85 = * CAST long <- int
/--* t83 long
+--* t85 long
N004 ( 6, 6) [000086] ------------ t86 = * ADD long
/--* t86 long
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59
N001 ( 3, 2) [000064] ------------ t64 = LCL_VAR int V02 arg2
N002 ( 1, 1) [000065] ------------ t65 = CNS_INT int 0
/--* t64 int
+--* t65 int
N003 ( 5, 4) [000066] J------N---- t66 = * GT int
/--* t66 int
N004 ( 7, 6) [000067] ------------ * JTRUE void
------------ BB07 [05D..086) (return), preds={BB06} succs={}
( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8
/--* t92 int
N003 ( 2, 3) [000093] ------------ t93 = * CAST long <- int
/--* t91 long
+--* t93 long
N004 ( 6, 6) [000094] ------------ t94 = * SUB long
/--* t94 long
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61
N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1
N002 ( 1, 1) [000101] ------------ t101 = CNS_INT int -1
/--* t100 int
+--* t101 int
N003 ( 5, 4) [000102] ------------ t102 = * ADD int
N004 ( 1, 1) [000103] ------------ t103 = CNS_INT int 63
/--* t102 int
+--* t103 int
N005 ( 7, 6) [000104] ------------ t104 = * AND int
N006 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1
/--* t98 int
N007 ( 2, 3) [000099] ------------ t99 = * CAST long <- int
/--* t99 long
+--* t104 int
N008 ( 13, 10) [000105] ------------ t105 = * LSH long
N009 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0
/--* t106 long
N010 ( 6, 4) [000107] *--XG------- t107 = * IND long
/--* t105 long
+--* t107 long
N011 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit
/--* t108 long
N012 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount
/--* t109 long
N013 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long
/--* t110 int
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78
N001 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0
N002 ( 3, 2) [000115] ------------ t115 = LCL_VAR long V00 arg0
/--* t114 long
+--* t115 long
N003 ( 7, 5) [000116] ------------ t116 = * SUB long
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8
/--* t117 int
N005 ( 2, 3) [000118] ------------ t118 = * CAST long <- int
/--* t116 long
+--* t118 long
N006 ( 29, 11) [000119] ---X-------- t119 = * DIV long
/--* t119 long
N007 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long
N008 ( 1, 1) [000120] ------------ t120 = CNS_INT int 64
/--* t134 int
+--* t120 int
N010 ( 35, 17) [000122] ---X-------- t122 = * MUL int
N011 ( 3, 2) [000124] ------------ t124 = LCL_VAR int V05 loc2
/--* t122 int
+--* t124 int
N012 ( 39, 20) [000125] ---X-------- t125 = * ADD int
/--* t125 int
N013 ( 40, 21) [000126] ---X-------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In fgDebugCheckBBlist
*************** In Lowering
Trees before Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0
/--* t1 long
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4
N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0
/--* t13 long
N002 ( 6, 4) [000014] *--XG------- t14 = * IND long
/--* t14 long
N003 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount
/--* t15 long
N004 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long
N005 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0
N006 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8
/--* t17 int
N007 ( 2, 3) [000018] ------------ t18 = * CAST long <- int
/--* t16 long
+--* t18 long
N008 ( 5, 5) [000019] -------N---- t19 = * ADD long
/--* t19 long
N009 ( 8, 7) [000020] *--XG------- t20 = * IND long
/--* t20 long
N010 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount
/--* t21 long
N011 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long
/--* t132 int
+--* t133 int
N012 ( 19, 18) [000022] ---XG------- t22 = * ADD int
N013 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0
N014 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2
/--* t24 int
N015 ( 2, 3) [000025] ------------ t25 = * CAST long <- int
N016 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8
/--* t26 int
N017 ( 2, 3) [000027] ------------ t27 = * CAST long <- int
/--* t25 long
+--* t27 long
N018 ( 8, 9) [000028] ------------ t28 = * MUL long
/--* t23 long
+--* t28 long
N019 ( 11, 11) [000029] -------N---- t29 = * ADD long
/--* t29 long
N020 ( 14, 13) [000030] *--XG------- t30 = * IND long
/--* t30 long
N021 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount
/--* t31 long
N022 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long
/--* t22 int
+--* t131 int
N023 ( 36, 35) [000032] ---XG------- t32 = * ADD int
N024 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0
N025 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3
/--* t34 int
N026 ( 2, 3) [000035] ------------ t35 = * CAST long <- int
N027 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8
/--* t36 int
N028 ( 2, 3) [000037] ------------ t37 = * CAST long <- int
/--* t35 long
+--* t37 long
N029 ( 8, 9) [000038] ------------ t38 = * MUL long
/--* t33 long
+--* t38 long
N030 ( 11, 11) [000039] -------N---- t39 = * ADD long
/--* t39 long
N031 ( 14, 13) [000040] *--XG------- t40 = * IND long
/--* t40 long
N032 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount
/--* t41 long
N033 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long
/--* t32 int
+--* t129 int
N034 ( 53, 52) [000042] ---XG------- t42 = * ADD int
N035 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2
/--* t12 int
+--* t42 int
N036 ( 57, 55) [000044] ---XG------- t44 = * SUB int
/--* t44 int
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34
N001 ( 3, 2) [000048] ------------ t48 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4
/--* t49 int
N003 ( 2, 3) [000050] ------------ t50 = * CAST long <- int
N004 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8
/--* t51 int
N005 ( 2, 3) [000052] ------------ t52 = * CAST long <- int
/--* t50 long
+--* t52 long
N006 ( 8, 9) [000053] ------------ t53 = * MUL long
/--* t48 long
+--* t53 long
N007 ( 12, 12) [000054] ------------ t54 = * ADD long
/--* t54 long
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b
N001 ( 3, 2) [000006] ------------ t6 = LCL_VAR int V02 arg2
N002 ( 1, 4) [000007] ------------ t7 = CNS_INT int 256
/--* t6 int
+--* t7 int
N003 ( 5, 7) [000008] J------N---- t8 = * GE int
/--* t8 int
N004 ( 7, 9) [000009] ------------ * JTRUE void
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2
/--* t59 int
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2
/--* t70 int
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49
N001 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2
N002 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0
/--* t75 long
N003 ( 6, 4) [000076] *--XG------- t76 = * IND long
/--* t76 long
N004 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount
/--* t77 long
N005 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long
/--* t74 int
+--* t78 int
N006 ( 12, 10) [000079] ---XG------- t79 = * SUB int
/--* t79 int
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55
N001 ( 3, 2) [000083] ------------ t83 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8
/--* t84 int
N003 ( 2, 3) [000085] ------------ t85 = * CAST long <- int
/--* t83 long
+--* t85 long
N004 ( 6, 6) [000086] ------------ t86 = * ADD long
/--* t86 long
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59
N001 ( 3, 2) [000064] ------------ t64 = LCL_VAR int V02 arg2
N002 ( 1, 1) [000065] ------------ t65 = CNS_INT int 0
/--* t64 int
+--* t65 int
N003 ( 5, 4) [000066] J------N---- t66 = * GT int
/--* t66 int
N004 ( 7, 6) [000067] ------------ * JTRUE void
------------ BB07 [05D..086) (return), preds={BB06} succs={}
( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8
/--* t92 int
N003 ( 2, 3) [000093] ------------ t93 = * CAST long <- int
/--* t91 long
+--* t93 long
N004 ( 6, 6) [000094] ------------ t94 = * SUB long
/--* t94 long
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61
N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1
N002 ( 1, 1) [000101] ------------ t101 = CNS_INT int -1
/--* t100 int
+--* t101 int
N003 ( 5, 4) [000102] ------------ t102 = * ADD int
N004 ( 1, 1) [000103] ------------ t103 = CNS_INT int 63
/--* t102 int
+--* t103 int
N005 ( 7, 6) [000104] ------------ t104 = * AND int
N006 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1
/--* t98 int
N007 ( 2, 3) [000099] ------------ t99 = * CAST long <- int
/--* t99 long
+--* t104 int
N008 ( 13, 10) [000105] ------------ t105 = * LSH long
N009 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0
/--* t106 long
N010 ( 6, 4) [000107] *--XG------- t107 = * IND long
/--* t105 long
+--* t107 long
N011 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit
/--* t108 long
N012 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount
/--* t109 long
N013 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long
/--* t110 int
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78
N001 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0
N002 ( 3, 2) [000115] ------------ t115 = LCL_VAR long V00 arg0
/--* t114 long
+--* t115 long
N003 ( 7, 5) [000116] ------------ t116 = * SUB long
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8
/--* t117 int
N005 ( 2, 3) [000118] ------------ t118 = * CAST long <- int
/--* t116 long
+--* t118 long
N006 ( 29, 11) [000119] ---X-------- t119 = * DIV long
/--* t119 long
N007 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long
N008 ( 1, 1) [000120] ------------ t120 = CNS_INT int 64
/--* t134 int
+--* t120 int
N010 ( 35, 17) [000122] ---X-------- t122 = * MUL int
N011 ( 3, 2) [000124] ------------ t124 = LCL_VAR int V05 loc2
/--* t122 int
+--* t124 int
N012 ( 39, 20) [000125] ---X-------- t125 = * ADD int
/--* t125 int
N013 ( 40, 21) [000126] ---X-------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
No addressing mode:
N001 ( 3, 2) [000013] ------------ * LCL_VAR long V03 loc0
Addressing mode:
Base
N005 ( 3, 2) [000016] -c---------- * LCL_VAR long V03 loc0
+ Index * 1 + 0
N007 ( 2, 3) [000018] ------------ * CAST long <- int
New addressing mode node:
[000136] ------------ * LEA(b+(i*1)+0) long
Addressing mode:
Base
N013 ( 3, 2) [000023] -c---------- * LCL_VAR long V03 loc0
+ Index * 1 + 0
N018 ( 8, 9) [000028] ------------ * MUL long
New addressing mode node:
[000137] ------------ * LEA(b+(i*1)+0) long
Addressing mode:
Base
N024 ( 3, 2) [000033] -c---------- * LCL_VAR long V03 loc0
+ Index * 1 + 0
N029 ( 8, 9) [000038] ------------ * MUL long
New addressing mode node:
[000138] ------------ * LEA(b+(i*1)+0) long
No addressing mode:
N002 ( 3, 2) [000075] ------------ * LCL_VAR long V03 loc0
No addressing mode:
N009 ( 3, 2) [000106] ------------ * LCL_VAR long V03 loc0
lowering GT_RETURN
N013 ( 40, 21) [000126] ---X-------- * RETURN int
============Lower has completed modifying nodes.
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0
/--* t1 long
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4
N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0
/--* t13 long
N002 ( 6, 4) [000014] *c-XG------- t14 = * IND long
/--* t14 long
N003 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount
/--* t15 long
N004 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long
N005 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0
N006 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8
/--* t17 int
N007 ( 2, 3) [000018] ------------ t18 = * CAST long <- int
/--* t16 long
+--* t18 long
[000136] -c---------- t136 = * LEA(b+(i*1)+0) long
/--* t136 long
N009 ( 8, 7) [000020] *c-XG------- t20 = * IND long
/--* t20 long
N010 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount
/--* t21 long
N011 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long
/--* t132 int
+--* t133 int
N012 ( 19, 18) [000022] ---XG------- t22 = * ADD int
N013 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0
N014 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2
/--* t24 int
N015 ( 2, 3) [000025] ------------ t25 = * CAST long <- int
N016 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8
/--* t26 int
N017 ( 2, 3) [000027] ------------ t27 = * CAST long <- int
/--* t25 long
+--* t27 long
N018 ( 8, 9) [000028] ------------ t28 = * MUL long
/--* t23 long
+--* t28 long
[000137] -c---------- t137 = * LEA(b+(i*1)+0) long
/--* t137 long
N020 ( 14, 13) [000030] *c-XG------- t30 = * IND long
/--* t30 long
N021 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount
/--* t31 long
N022 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long
/--* t22 int
+--* t131 int
N023 ( 36, 35) [000032] ---XG------- t32 = * ADD int
N024 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0
N025 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3
/--* t34 int
N026 ( 2, 3) [000035] ------------ t35 = * CAST long <- int
N027 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8
/--* t36 int
N028 ( 2, 3) [000037] ------------ t37 = * CAST long <- int
/--* t35 long
+--* t37 long
N029 ( 8, 9) [000038] ------------ t38 = * MUL long
/--* t33 long
+--* t38 long
[000138] -c---------- t138 = * LEA(b+(i*1)+0) long
/--* t138 long
N031 ( 14, 13) [000040] *c-XG------- t40 = * IND long
/--* t40 long
N032 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount
/--* t41 long
N033 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long
/--* t32 int
+--* t129 int
N034 ( 53, 52) [000042] ---XG------- t42 = * ADD int
N035 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2
/--* t12 int
+--* t42 int
N036 ( 57, 55) [000044] ---XG------- t44 = * SUB int
/--* t44 int
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34
N001 ( 3, 2) [000048] -c---------- t48 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4
/--* t49 int
N003 ( 2, 3) [000050] ------------ t50 = * CAST long <- int
N004 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8
/--* t51 int
N005 ( 2, 3) [000052] ------------ t52 = * CAST long <- int
/--* t50 long
+--* t52 long
N006 ( 8, 9) [000053] ------------ t53 = * MUL long
/--* t48 long
+--* t53 long
N007 ( 12, 12) [000054] ------------ t54 = * ADD long
/--* t54 long
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b
N001 ( 3, 2) [000006] -c---------- t6 = LCL_VAR int V02 arg2
N002 ( 1, 4) [000007] -c---------- t7 = CNS_INT int 256
/--* t6 int
+--* t7 int
N003 ( 5, 7) [000008] J------N---- * GE void
N004 ( 7, 9) [000009] ------------ * JTRUE void
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2
/--* t59 int
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2
/--* t70 int
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49
N001 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2
N002 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0
/--* t75 long
N003 ( 6, 4) [000076] *c-XG------- t76 = * IND long
/--* t76 long
N004 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount
/--* t77 long
N005 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long
/--* t74 int
+--* t78 int
N006 ( 12, 10) [000079] ---XG------- t79 = * SUB int
/--* t79 int
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55
N001 ( 3, 2) [000083] -c---------- t83 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8
/--* t84 int
N003 ( 2, 3) [000085] ------------ t85 = * CAST long <- int
/--* t83 long
+--* t85 long
N004 ( 6, 6) [000086] ------------ t86 = * ADD long
/--* t86 long
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59
N001 ( 3, 2) [000064] -c---------- t64 = LCL_VAR int V02 arg2
N002 ( 1, 1) [000065] -c---------- t65 = CNS_INT int 0
/--* t64 int
+--* t65 int
N003 ( 5, 4) [000066] J------N---- * GT void
N004 ( 7, 6) [000067] ------------ * JTRUE void
------------ BB07 [05D..086) (return), preds={BB06} succs={}
( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8
/--* t92 int
N003 ( 2, 3) [000093] ------------ t93 = * CAST long <- int
/--* t91 long
+--* t93 long
N004 ( 6, 6) [000094] ------------ t94 = * SUB long
/--* t94 long
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61
N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1
N002 ( 1, 1) [000101] -c---------- t101 = CNS_INT int -1
/--* t100 int
+--* t101 int
N003 ( 5, 4) [000102] ------------ t102 = * ADD int
N006 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1
/--* t98 int
N007 ( 2, 3) [000099] ------------ t99 = * CAST long <- int
/--* t99 long
+--* t102 int
N008 ( 13, 10) [000105] ------------ t105 = * LSH long
N009 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0
/--* t106 long
N010 ( 6, 4) [000107] *c-XG------- t107 = * IND long
/--* t105 long
+--* t107 long
N011 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit
/--* t108 long
N012 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount
/--* t109 long
N013 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long
/--* t110 int
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78
N001 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0
N002 ( 3, 2) [000115] -c---------- t115 = LCL_VAR long V00 arg0
/--* t114 long
+--* t115 long
N003 ( 7, 5) [000116] ------------ t116 = * SUB long
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8
/--* t117 int
N005 ( 2, 3) [000118] ------------ t118 = * CAST long <- int
/--* t116 long
+--* t118 long
N006 ( 29, 11) [000119] ---X-------- t119 = * DIV long
/--* t119 long
N007 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long
N008 ( 1, 1) [000120] -c---------- t120 = CNS_INT int 64
/--* t134 int
+--* t120 int
N010 ( 35, 17) [000122] ---X-------- t122 = * MUL int
N011 ( 3, 2) [000124] -c---------- t124 = LCL_VAR int V05 loc2
/--* t122 int
+--* t124 int
N012 ( 39, 20) [000125] ---X-------- t125 = * ADD int
/--* t125 int
N013 ( 40, 21) [000126] ---X-------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*** lvaComputeRefCounts ***
*************** In fgLocalVarLiveness()
; Initial local variable assignments
;
; V00 arg0 long
; V01 arg1 int
; V02 arg2 int
; V03 loc0 long
; V04 loc1 int
; V05 loc2 int
; V06 OutArgs lclBlk ( 0)
In fgLocalVarLivenessInit
*************** In fgPerBlockLocalVarLiveness()
*************** In fgInterBlockLocalVarLiveness()
*** lvaComputeRefCounts ***
Liveness pass finished after lowering, IR:
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0
/--* t1 long
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4
N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0
/--* t13 long
N002 ( 6, 4) [000014] *c-XG------- t14 = * IND long
/--* t14 long
N003 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount
/--* t15 long
N004 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long
N005 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0
N006 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8
/--* t17 int
N007 ( 2, 3) [000018] ------------ t18 = * CAST long <- int
/--* t16 long
+--* t18 long
[000136] -c---------- t136 = * LEA(b+(i*1)+0) long
/--* t136 long
N009 ( 8, 7) [000020] *c-XG------- t20 = * IND long
/--* t20 long
N010 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount
/--* t21 long
N011 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long
/--* t132 int
+--* t133 int
N012 ( 19, 18) [000022] ---XG------- t22 = * ADD int
N013 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0
N014 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2
/--* t24 int
N015 ( 2, 3) [000025] ------------ t25 = * CAST long <- int
N016 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8
/--* t26 int
N017 ( 2, 3) [000027] ------------ t27 = * CAST long <- int
/--* t25 long
+--* t27 long
N018 ( 8, 9) [000028] ------------ t28 = * MUL long
/--* t23 long
+--* t28 long
[000137] -c---------- t137 = * LEA(b+(i*1)+0) long
/--* t137 long
N020 ( 14, 13) [000030] *c-XG------- t30 = * IND long
/--* t30 long
N021 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount
/--* t31 long
N022 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long
/--* t22 int
+--* t131 int
N023 ( 36, 35) [000032] ---XG------- t32 = * ADD int
N024 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0
N025 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3
/--* t34 int
N026 ( 2, 3) [000035] ------------ t35 = * CAST long <- int
N027 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8
/--* t36 int
N028 ( 2, 3) [000037] ------------ t37 = * CAST long <- int
/--* t35 long
+--* t37 long
N029 ( 8, 9) [000038] ------------ t38 = * MUL long
/--* t33 long
+--* t38 long
[000138] -c---------- t138 = * LEA(b+(i*1)+0) long
/--* t138 long
N031 ( 14, 13) [000040] *c-XG------- t40 = * IND long
/--* t40 long
N032 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount
/--* t41 long
N033 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long
/--* t32 int
+--* t129 int
N034 ( 53, 52) [000042] ---XG------- t42 = * ADD int
N035 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2
/--* t12 int
+--* t42 int
N036 ( 57, 55) [000044] ---XG------- t44 = * SUB int
/--* t44 int
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34
N001 ( 3, 2) [000048] -c---------- t48 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4
/--* t49 int
N003 ( 2, 3) [000050] ------------ t50 = * CAST long <- int
N004 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8
/--* t51 int
N005 ( 2, 3) [000052] ------------ t52 = * CAST long <- int
/--* t50 long
+--* t52 long
N006 ( 8, 9) [000053] ------------ t53 = * MUL long
/--* t48 long
+--* t53 long
N007 ( 12, 12) [000054] ------------ t54 = * ADD long
/--* t54 long
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b
N001 ( 3, 2) [000006] -c---------- t6 = LCL_VAR int V02 arg2
N002 ( 1, 4) [000007] -c---------- t7 = CNS_INT int 256
/--* t6 int
+--* t7 int
N003 ( 5, 7) [000008] J------N---- * GE void
N004 ( 7, 9) [000009] ------------ * JTRUE void
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2
/--* t59 int
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2
/--* t70 int
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49
N001 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2
N002 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0
/--* t75 long
N003 ( 6, 4) [000076] *c-XG------- t76 = * IND long
/--* t76 long
N004 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount
/--* t77 long
N005 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long
/--* t74 int
+--* t78 int
N006 ( 12, 10) [000079] ---XG------- t79 = * SUB int
/--* t79 int
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55
N001 ( 3, 2) [000083] -c---------- t83 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8
/--* t84 int
N003 ( 2, 3) [000085] ------------ t85 = * CAST long <- int
/--* t83 long
+--* t85 long
N004 ( 6, 6) [000086] ------------ t86 = * ADD long
/--* t86 long
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59
N001 ( 3, 2) [000064] -c---------- t64 = LCL_VAR int V02 arg2
N002 ( 1, 1) [000065] -c---------- t65 = CNS_INT int 0
/--* t64 int
+--* t65 int
N003 ( 5, 4) [000066] J------N---- * GT void
N004 ( 7, 6) [000067] ------------ * JTRUE void
------------ BB07 [05D..086) (return), preds={BB06} succs={}
( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8
/--* t92 int
N003 ( 2, 3) [000093] ------------ t93 = * CAST long <- int
/--* t91 long
+--* t93 long
N004 ( 6, 6) [000094] ------------ t94 = * SUB long
/--* t94 long
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61
N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1
N002 ( 1, 1) [000101] -c---------- t101 = CNS_INT int -1
/--* t100 int
+--* t101 int
N003 ( 5, 4) [000102] ------------ t102 = * ADD int
N006 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1
/--* t98 int
N007 ( 2, 3) [000099] ------------ t99 = * CAST long <- int
/--* t99 long
+--* t102 int
N008 ( 13, 10) [000105] ------------ t105 = * LSH long
N009 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0
/--* t106 long
N010 ( 6, 4) [000107] *c-XG------- t107 = * IND long
/--* t105 long
+--* t107 long
N011 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit
/--* t108 long
N012 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount
/--* t109 long
N013 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long
/--* t110 int
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78
N001 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0
N002 ( 3, 2) [000115] -c---------- t115 = LCL_VAR long V00 arg0
/--* t114 long
+--* t115 long
N003 ( 7, 5) [000116] ------------ t116 = * SUB long
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8
/--* t117 int
N005 ( 2, 3) [000118] ------------ t118 = * CAST long <- int
/--* t116 long
+--* t118 long
N006 ( 29, 11) [000119] ---X-------- t119 = * DIV long
/--* t119 long
N007 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long
N008 ( 1, 1) [000120] -c---------- t120 = CNS_INT int 64
/--* t134 int
+--* t120 int
N010 ( 35, 17) [000122] ---X-------- t122 = * MUL int
N011 ( 3, 2) [000124] -c---------- t124 = LCL_VAR int V05 loc2
/--* t122 int
+--* t124 int
N012 ( 39, 20) [000125] ---X-------- t125 = * ADD int
/--* t125 int
N013 ( 40, 21) [000126] ---X-------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** Exiting Lowering
Trees after Lowering
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0
/--* t1 long
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4
N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0
/--* t13 long
N002 ( 6, 4) [000014] *c-XG------- t14 = * IND long
/--* t14 long
N003 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount
/--* t15 long
N004 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long
N005 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0
N006 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8
/--* t17 int
N007 ( 2, 3) [000018] ------------ t18 = * CAST long <- int
/--* t16 long
+--* t18 long
[000136] -c---------- t136 = * LEA(b+(i*1)+0) long
/--* t136 long
N009 ( 8, 7) [000020] *c-XG------- t20 = * IND long
/--* t20 long
N010 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount
/--* t21 long
N011 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long
/--* t132 int
+--* t133 int
N012 ( 19, 18) [000022] ---XG------- t22 = * ADD int
N013 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0
N014 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2
/--* t24 int
N015 ( 2, 3) [000025] ------------ t25 = * CAST long <- int
N016 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8
/--* t26 int
N017 ( 2, 3) [000027] ------------ t27 = * CAST long <- int
/--* t25 long
+--* t27 long
N018 ( 8, 9) [000028] ------------ t28 = * MUL long
/--* t23 long
+--* t28 long
[000137] -c---------- t137 = * LEA(b+(i*1)+0) long
/--* t137 long
N020 ( 14, 13) [000030] *c-XG------- t30 = * IND long
/--* t30 long
N021 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount
/--* t31 long
N022 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long
/--* t22 int
+--* t131 int
N023 ( 36, 35) [000032] ---XG------- t32 = * ADD int
N024 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0
N025 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3
/--* t34 int
N026 ( 2, 3) [000035] ------------ t35 = * CAST long <- int
N027 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8
/--* t36 int
N028 ( 2, 3) [000037] ------------ t37 = * CAST long <- int
/--* t35 long
+--* t37 long
N029 ( 8, 9) [000038] ------------ t38 = * MUL long
/--* t33 long
+--* t38 long
[000138] -c---------- t138 = * LEA(b+(i*1)+0) long
/--* t138 long
N031 ( 14, 13) [000040] *c-XG------- t40 = * IND long
/--* t40 long
N032 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount
/--* t41 long
N033 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long
/--* t32 int
+--* t129 int
N034 ( 53, 52) [000042] ---XG------- t42 = * ADD int
N035 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2
/--* t12 int
+--* t42 int
N036 ( 57, 55) [000044] ---XG------- t44 = * SUB int
/--* t44 int
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34
N001 ( 3, 2) [000048] -c---------- t48 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4
/--* t49 int
N003 ( 2, 3) [000050] ------------ t50 = * CAST long <- int
N004 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8
/--* t51 int
N005 ( 2, 3) [000052] ------------ t52 = * CAST long <- int
/--* t50 long
+--* t52 long
N006 ( 8, 9) [000053] ------------ t53 = * MUL long
/--* t48 long
+--* t53 long
N007 ( 12, 12) [000054] ------------ t54 = * ADD long
/--* t54 long
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b
N001 ( 3, 2) [000006] -c---------- t6 = LCL_VAR int V02 arg2
N002 ( 1, 4) [000007] -c---------- t7 = CNS_INT int 256
/--* t6 int
+--* t7 int
N003 ( 5, 7) [000008] J------N---- * GE void
N004 ( 7, 9) [000009] ------------ * JTRUE void
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2
/--* t59 int
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2
/--* t70 int
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49
N001 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2
N002 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0
/--* t75 long
N003 ( 6, 4) [000076] *c-XG------- t76 = * IND long
/--* t76 long
N004 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount
/--* t77 long
N005 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long
/--* t74 int
+--* t78 int
N006 ( 12, 10) [000079] ---XG------- t79 = * SUB int
/--* t79 int
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55
N001 ( 3, 2) [000083] -c---------- t83 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8
/--* t84 int
N003 ( 2, 3) [000085] ------------ t85 = * CAST long <- int
/--* t83 long
+--* t85 long
N004 ( 6, 6) [000086] ------------ t86 = * ADD long
/--* t86 long
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59
N001 ( 3, 2) [000064] -c---------- t64 = LCL_VAR int V02 arg2
N002 ( 1, 1) [000065] -c---------- t65 = CNS_INT int 0
/--* t64 int
+--* t65 int
N003 ( 5, 4) [000066] J------N---- * GT void
N004 ( 7, 6) [000067] ------------ * JTRUE void
------------ BB07 [05D..086) (return), preds={BB06} succs={}
( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8
/--* t92 int
N003 ( 2, 3) [000093] ------------ t93 = * CAST long <- int
/--* t91 long
+--* t93 long
N004 ( 6, 6) [000094] ------------ t94 = * SUB long
/--* t94 long
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61
N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1
N002 ( 1, 1) [000101] -c---------- t101 = CNS_INT int -1
/--* t100 int
+--* t101 int
N003 ( 5, 4) [000102] ------------ t102 = * ADD int
N006 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1
/--* t98 int
N007 ( 2, 3) [000099] ------------ t99 = * CAST long <- int
/--* t99 long
+--* t102 int
N008 ( 13, 10) [000105] ------------ t105 = * LSH long
N009 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0
/--* t106 long
N010 ( 6, 4) [000107] *c-XG------- t107 = * IND long
/--* t105 long
+--* t107 long
N011 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit
/--* t108 long
N012 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount
/--* t109 long
N013 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long
/--* t110 int
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78
N001 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0
N002 ( 3, 2) [000115] -c---------- t115 = LCL_VAR long V00 arg0
/--* t114 long
+--* t115 long
N003 ( 7, 5) [000116] ------------ t116 = * SUB long
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8
/--* t117 int
N005 ( 2, 3) [000118] ------------ t118 = * CAST long <- int
/--* t116 long
+--* t118 long
N006 ( 29, 11) [000119] ---X-------- t119 = * DIV long
/--* t119 long
N007 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long
N008 ( 1, 1) [000120] -c---------- t120 = CNS_INT int 64
/--* t134 int
+--* t120 int
N010 ( 35, 17) [000122] ---X-------- t122 = * MUL int
N011 ( 3, 2) [000124] -c---------- t124 = LCL_VAR int V05 loc2
/--* t122 int
+--* t124 int
N012 ( 39, 20) [000125] ---X-------- t125 = * ADD int
/--* t125 int
N013 ( 40, 21) [000126] ---X-------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
*************** In StackLevelSetter
Trees before StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0
/--* t1 long
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4
N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0
/--* t13 long
N002 ( 6, 4) [000014] *c-XG------- t14 = * IND long
/--* t14 long
N003 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount
/--* t15 long
N004 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long
N005 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0
N006 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8
/--* t17 int
N007 ( 2, 3) [000018] ------------ t18 = * CAST long <- int
/--* t16 long
+--* t18 long
[000136] -c---------- t136 = * LEA(b+(i*1)+0) long
/--* t136 long
N009 ( 8, 7) [000020] *c-XG------- t20 = * IND long
/--* t20 long
N010 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount
/--* t21 long
N011 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long
/--* t132 int
+--* t133 int
N012 ( 19, 18) [000022] ---XG------- t22 = * ADD int
N013 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0
N014 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2
/--* t24 int
N015 ( 2, 3) [000025] ------------ t25 = * CAST long <- int
N016 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8
/--* t26 int
N017 ( 2, 3) [000027] ------------ t27 = * CAST long <- int
/--* t25 long
+--* t27 long
N018 ( 8, 9) [000028] ------------ t28 = * MUL long
/--* t23 long
+--* t28 long
[000137] -c---------- t137 = * LEA(b+(i*1)+0) long
/--* t137 long
N020 ( 14, 13) [000030] *c-XG------- t30 = * IND long
/--* t30 long
N021 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount
/--* t31 long
N022 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long
/--* t22 int
+--* t131 int
N023 ( 36, 35) [000032] ---XG------- t32 = * ADD int
N024 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0
N025 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3
/--* t34 int
N026 ( 2, 3) [000035] ------------ t35 = * CAST long <- int
N027 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8
/--* t36 int
N028 ( 2, 3) [000037] ------------ t37 = * CAST long <- int
/--* t35 long
+--* t37 long
N029 ( 8, 9) [000038] ------------ t38 = * MUL long
/--* t33 long
+--* t38 long
[000138] -c---------- t138 = * LEA(b+(i*1)+0) long
/--* t138 long
N031 ( 14, 13) [000040] *c-XG------- t40 = * IND long
/--* t40 long
N032 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount
/--* t41 long
N033 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long
/--* t32 int
+--* t129 int
N034 ( 53, 52) [000042] ---XG------- t42 = * ADD int
N035 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2
/--* t12 int
+--* t42 int
N036 ( 57, 55) [000044] ---XG------- t44 = * SUB int
/--* t44 int
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34
N001 ( 3, 2) [000048] -c---------- t48 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4
/--* t49 int
N003 ( 2, 3) [000050] ------------ t50 = * CAST long <- int
N004 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8
/--* t51 int
N005 ( 2, 3) [000052] ------------ t52 = * CAST long <- int
/--* t50 long
+--* t52 long
N006 ( 8, 9) [000053] ------------ t53 = * MUL long
/--* t48 long
+--* t53 long
N007 ( 12, 12) [000054] ------------ t54 = * ADD long
/--* t54 long
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b
N001 ( 3, 2) [000006] -c---------- t6 = LCL_VAR int V02 arg2
N002 ( 1, 4) [000007] -c---------- t7 = CNS_INT int 256
/--* t6 int
+--* t7 int
N003 ( 5, 7) [000008] J------N---- * GE void
N004 ( 7, 9) [000009] ------------ * JTRUE void
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2
/--* t59 int
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2
/--* t70 int
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49
N001 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2
N002 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0
/--* t75 long
N003 ( 6, 4) [000076] *c-XG------- t76 = * IND long
/--* t76 long
N004 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount
/--* t77 long
N005 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long
/--* t74 int
+--* t78 int
N006 ( 12, 10) [000079] ---XG------- t79 = * SUB int
/--* t79 int
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55
N001 ( 3, 2) [000083] -c---------- t83 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8
/--* t84 int
N003 ( 2, 3) [000085] ------------ t85 = * CAST long <- int
/--* t83 long
+--* t85 long
N004 ( 6, 6) [000086] ------------ t86 = * ADD long
/--* t86 long
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59
N001 ( 3, 2) [000064] -c---------- t64 = LCL_VAR int V02 arg2
N002 ( 1, 1) [000065] -c---------- t65 = CNS_INT int 0
/--* t64 int
+--* t65 int
N003 ( 5, 4) [000066] J------N---- * GT void
N004 ( 7, 6) [000067] ------------ * JTRUE void
------------ BB07 [05D..086) (return), preds={BB06} succs={}
( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8
/--* t92 int
N003 ( 2, 3) [000093] ------------ t93 = * CAST long <- int
/--* t91 long
+--* t93 long
N004 ( 6, 6) [000094] ------------ t94 = * SUB long
/--* t94 long
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61
N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1
N002 ( 1, 1) [000101] -c---------- t101 = CNS_INT int -1
/--* t100 int
+--* t101 int
N003 ( 5, 4) [000102] ------------ t102 = * ADD int
N006 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1
/--* t98 int
N007 ( 2, 3) [000099] ------------ t99 = * CAST long <- int
/--* t99 long
+--* t102 int
N008 ( 13, 10) [000105] ------------ t105 = * LSH long
N009 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0
/--* t106 long
N010 ( 6, 4) [000107] *c-XG------- t107 = * IND long
/--* t105 long
+--* t107 long
N011 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit
/--* t108 long
N012 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount
/--* t109 long
N013 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long
/--* t110 int
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78
N001 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0
N002 ( 3, 2) [000115] -c---------- t115 = LCL_VAR long V00 arg0
/--* t114 long
+--* t115 long
N003 ( 7, 5) [000116] ------------ t116 = * SUB long
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8
/--* t117 int
N005 ( 2, 3) [000118] ------------ t118 = * CAST long <- int
/--* t116 long
+--* t118 long
N006 ( 29, 11) [000119] ---X-------- t119 = * DIV long
/--* t119 long
N007 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long
N008 ( 1, 1) [000120] -c---------- t120 = CNS_INT int 64
/--* t134 int
+--* t120 int
N010 ( 35, 17) [000122] ---X-------- t122 = * MUL int
N011 ( 3, 2) [000124] -c---------- t124 = LCL_VAR int V05 loc2
/--* t122 int
+--* t124 int
N012 ( 39, 20) [000125] ---X-------- t125 = * ADD int
/--* t125 int
N013 ( 40, 21) [000126] ---X-------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** Exiting StackLevelSetter
Trees after StackLevelSetter
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0
N001 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0
/--* t1 long
N003 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB02 [004..03B), preds={BB03} succs={BB03}
( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4
N001 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0
/--* t13 long
N002 ( 6, 4) [000014] *c-XG------- t14 = * IND long
/--* t14 long
N003 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount
/--* t15 long
N004 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long
N005 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0
N006 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8
/--* t17 int
N007 ( 2, 3) [000018] ------------ t18 = * CAST long <- int
/--* t16 long
+--* t18 long
[000136] -c---------- t136 = * LEA(b+(i*1)+0) long
/--* t136 long
N009 ( 8, 7) [000020] *c-XG------- t20 = * IND long
/--* t20 long
N010 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount
/--* t21 long
N011 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long
/--* t132 int
+--* t133 int
N012 ( 19, 18) [000022] ---XG------- t22 = * ADD int
N013 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0
N014 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2
/--* t24 int
N015 ( 2, 3) [000025] ------------ t25 = * CAST long <- int
N016 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8
/--* t26 int
N017 ( 2, 3) [000027] ------------ t27 = * CAST long <- int
/--* t25 long
+--* t27 long
N018 ( 8, 9) [000028] ------------ t28 = * MUL long
/--* t23 long
+--* t28 long
[000137] -c---------- t137 = * LEA(b+(i*1)+0) long
/--* t137 long
N020 ( 14, 13) [000030] *c-XG------- t30 = * IND long
/--* t30 long
N021 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount
/--* t31 long
N022 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long
/--* t22 int
+--* t131 int
N023 ( 36, 35) [000032] ---XG------- t32 = * ADD int
N024 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0
N025 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3
/--* t34 int
N026 ( 2, 3) [000035] ------------ t35 = * CAST long <- int
N027 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8
/--* t36 int
N028 ( 2, 3) [000037] ------------ t37 = * CAST long <- int
/--* t35 long
+--* t37 long
N029 ( 8, 9) [000038] ------------ t38 = * MUL long
/--* t33 long
+--* t38 long
[000138] -c---------- t138 = * LEA(b+(i*1)+0) long
/--* t138 long
N031 ( 14, 13) [000040] *c-XG------- t40 = * IND long
/--* t40 long
N032 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount
/--* t41 long
N033 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long
/--* t32 int
+--* t129 int
N034 ( 53, 52) [000042] ---XG------- t42 = * ADD int
N035 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2
/--* t12 int
+--* t42 int
N036 ( 57, 55) [000044] ---XG------- t44 = * SUB int
/--* t44 int
N038 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34
N001 ( 3, 2) [000048] -c---------- t48 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4
/--* t49 int
N003 ( 2, 3) [000050] ------------ t50 = * CAST long <- int
N004 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8
/--* t51 int
N005 ( 2, 3) [000052] ------------ t52 = * CAST long <- int
/--* t50 long
+--* t52 long
N006 ( 8, 9) [000053] ------------ t53 = * MUL long
/--* t48 long
+--* t53 long
N007 ( 12, 12) [000054] ------------ t54 = * ADD long
/--* t54 long
N009 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b
N001 ( 3, 2) [000006] -c---------- t6 = LCL_VAR int V02 arg2
N002 ( 1, 4) [000007] -c---------- t7 = CNS_INT int 256
/--* t6 int
+--* t7 int
N003 ( 5, 7) [000008] J------N---- * GE void
N004 ( 7, 9) [000009] ------------ * JTRUE void
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43
N001 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2
/--* t59 int
N003 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1
------------ BB05 [047..059), preds={BB06} succs={BB06}
( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47
N001 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2
/--* t70 int
N003 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1
( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49
N001 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2
N002 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0
/--* t75 long
N003 ( 6, 4) [000076] *c-XG------- t76 = * IND long
/--* t76 long
N004 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount
/--* t77 long
N005 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long
/--* t74 int
+--* t78 int
N006 ( 12, 10) [000079] ---XG------- t79 = * SUB int
/--* t79 int
N008 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2
( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55
N001 ( 3, 2) [000083] -c---------- t83 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8
/--* t84 int
N003 ( 2, 3) [000085] ------------ t85 = * CAST long <- int
/--* t83 long
+--* t85 long
N004 ( 6, 6) [000086] ------------ t86 = * ADD long
/--* t86 long
N006 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59
N001 ( 3, 2) [000064] -c---------- t64 = LCL_VAR int V02 arg2
N002 ( 1, 1) [000065] -c---------- t65 = CNS_INT int 0
/--* t64 int
+--* t65 int
N003 ( 5, 4) [000066] J------N---- * GT void
N004 ( 7, 6) [000067] ------------ * JTRUE void
------------ BB07 [05D..086) (return), preds={BB06} succs={}
( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d
N001 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0
N002 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8
/--* t92 int
N003 ( 2, 3) [000093] ------------ t93 = * CAST long <- int
/--* t91 long
+--* t93 long
N004 ( 6, 6) [000094] ------------ t94 = * SUB long
/--* t94 long
N006 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0
( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61
N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1
N002 ( 1, 1) [000101] -c---------- t101 = CNS_INT int -1
/--* t100 int
+--* t101 int
N003 ( 5, 4) [000102] ------------ t102 = * ADD int
N006 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1
/--* t98 int
N007 ( 2, 3) [000099] ------------ t99 = * CAST long <- int
/--* t99 long
+--* t102 int
N008 ( 13, 10) [000105] ------------ t105 = * LSH long
N009 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0
/--* t106 long
N010 ( 6, 4) [000107] *c-XG------- t107 = * IND long
/--* t105 long
+--* t107 long
N011 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit
/--* t108 long
N012 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount
/--* t109 long
N013 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long
/--* t110 int
N015 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2
( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78
N001 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0
N002 ( 3, 2) [000115] -c---------- t115 = LCL_VAR long V00 arg0
/--* t114 long
+--* t115 long
N003 ( 7, 5) [000116] ------------ t116 = * SUB long
N004 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8
/--* t117 int
N005 ( 2, 3) [000118] ------------ t118 = * CAST long <- int
/--* t116 long
+--* t118 long
N006 ( 29, 11) [000119] ---X-------- t119 = * DIV long
/--* t119 long
N007 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long
N008 ( 1, 1) [000120] -c---------- t120 = CNS_INT int 64
/--* t134 int
+--* t120 int
N010 ( 35, 17) [000122] ---X-------- t122 = * MUL int
N011 ( 3, 2) [000124] -c---------- t124 = LCL_VAR int V05 loc2
/--* t122 int
+--* t124 int
N012 ( 39, 20) [000125] ---X-------- t125 = * ADD int
/--* t125 int
N013 ( 40, 21) [000126] ---X-------- * RETURN int
-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Clearing modified regs.
buildIntervals ========
-----------------
LIVENESS:
-----------------
BB01 use def in out
{}
{}
{}
{}
BB02 use def in out
{}
{}
{}
{}
BB03 use def in out
{}
{}
{}
{}
BB04 use def in out
{}
{}
{}
{}
BB05 use def in out
{}
{}
{}
{}
BB06 use def in out
{}
{}
{}
{}
BB07 use def in out
{}
{}
{}
{}
FP callee save candidate vars: None
floatVarCount = 0; hasLoops = 0, singleExit = 1
; Decided to create an EBP based frame for ETW stackwalking (Debug Code)
TUPLE STYLE DUMP BEFORE LSRA
LSRA Block Sequence: BB01( 1 ) BB03( 1 ) BB02( 1 ) BB04( 1 ) BB06( 1 ) BB05( 1 ) BB07( 1 )
BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
=====
N000. IL_OFFSET IL offset: 0x0
N001. t1 = V00 MEM
N003. V03 MEM; t1
BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
=====
N000. IL_OFFSET IL offset: 0x3b
N001. V02 MEM
N002. CNS_INT 256
N003. GE
N004. JTRUE
BB02 [004..03B), preds={BB03} succs={BB03}
=====
N000. IL_OFFSET IL offset: 0x4
N001. t13 = V03 MEM
N002. t14 = IND ; t13
N003. t15 = HWIntrinsic; t14
N004. t132 = CAST ; t15
N005. t16 = V03 MEM
N006. t17 = CNS_INT 8
N007. t18 = CAST ; t17
N000. t136 = LEA(b+(i*1)+0); t16,t18
N009. t20 = IND ; t136
N010. t21 = HWIntrinsic; t20
N011. t133 = CAST ; t21
N012. t22 = ADD ; t132,t133
N013. t23 = V03 MEM
N014. t24 = CNS_INT 2
N015. t25 = CAST ; t24
N016. t26 = CNS_INT 8
N017. t27 = CAST ; t26
N018. t28 = MUL ; t25,t27
N000. t137 = LEA(b+(i*1)+0); t23,t28
N020. t30 = IND ; t137
N021. t31 = HWIntrinsic; t30
N022. t131 = CAST ; t31
N023. t32 = ADD ; t22,t131
N024. t33 = V03 MEM
N025. t34 = CNS_INT 3
N026. t35 = CAST ; t34
N027. t36 = CNS_INT 8
N028. t37 = CAST ; t36
N029. t38 = MUL ; t35,t37
N000. t138 = LEA(b+(i*1)+0); t33,t38
N031. t40 = IND ; t138
N032. t41 = HWIntrinsic; t40
N033. t129 = CAST ; t41
N034. t42 = ADD ; t32,t129
N035. t12 = V02 MEM
N036. t44 = SUB ; t12,t42
N038. V02 MEM; t44
N000. IL_OFFSET IL offset: 0x34
N001. V03 MEM
N002. t49 = CNS_INT 4
N003. t50 = CAST ; t49
N004. t51 = CNS_INT 8
N005. t52 = CAST ; t51
N006. t53 = MUL ; t50,t52
N007. t54 = ADD ; t53
N009. V03 MEM; t54
BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
=====
N000. IL_OFFSET IL offset: 0x43
N001. t59 = V02 MEM
N003. V04 MEM; t59
BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
=====
N000. IL_OFFSET IL offset: 0x59
N001. V02 MEM
N002. CNS_INT 0
N003. GT
N004. JTRUE
BB05 [047..059), preds={BB06} succs={BB06}
=====
N000. IL_OFFSET IL offset: 0x47
N001. t70 = V02 MEM
N003. V04 MEM; t70
N000. IL_OFFSET IL offset: 0x49
N001. t74 = V02 MEM
N002. t75 = V03 MEM
N003. t76 = IND ; t75
N004. t77 = HWIntrinsic; t76
N005. t78 = CAST ; t77
N006. t79 = SUB ; t74,t78
N008. V02 MEM; t79
N000. IL_OFFSET IL offset: 0x55
N001. V03 MEM
N002. t84 = CNS_INT 8
N003. t85 = CAST ; t84
N004. t86 = ADD ; t85
N006. V03 MEM; t86
BB07 [05D..086) (return), preds={BB06} succs={}
=====
N000. IL_OFFSET IL offset: 0x5d
N001. t91 = V03 MEM
N002. t92 = CNS_INT 8
N003. t93 = CAST ; t92
N004. t94 = SUB ; t91,t93
N006. V03 MEM; t94
N000. IL_OFFSET IL offset: 0x61
N001. t100 = V04 MEM
N002. CNS_INT -1
N003. t102 = ADD ; t100
N006. t98 = CNS_INT 1
N007. t99 = CAST ; t98
N008. t105 = LSH ; t99,t102
N009. t106 = V03 MEM
N010. t107 = IND ; t106
N011. t108 = HWIntrinsic; t105,t107
N012. t109 = HWIntrinsic; t108
N013. t110 = CAST ; t109
N015. V05 MEM; t110
N000. IL_OFFSET IL offset: 0x78
N001. t114 = V03 MEM
N002. V00 MEM
N003. t116 = SUB ; t114
N004. t117 = CNS_INT 8
N005. t118 = CAST ; t117
N006. t119 = DIV ; t116,t118
N007. t134 = CAST ; t119
N008. CNS_INT 64
N010. t122 = MUL ; t134
N011. V05 MEM
N012. t125 = ADD ; t122
N013. RETURN ; t125
buildIntervals second part ========
Int arg V00 in reg rdi
Int arg V01 in reg rsi
Int arg V02 in reg rdx
NEW BLOCK BB01
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
DefList: { }
N002 ( 7, 5) [000004] ------------ * IL_OFFSET void IL offset: 0x0 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N004 ( 3, 2) [000001] ------------ * LCL_VAR long V00 arg0 NA REG NA
Interval 0: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #1 @5 RefTypeDef <Ivl:0> LCL_VAR BB01 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N004.t1. LCL_VAR }
N006 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
NEW BLOCK BB03
Setting BB03 as the predecessor for determining incoming variable registers of BB01
<RefPosition #3 @8 RefTypeBB BB03 regmask=[] minReg=1>
DefList: { }
N010 ( 7, 9) [000010] ------------ * IL_OFFSET void IL offset: 0x3b REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N012 ( 3, 2) [000006] -c---------- * LCL_VAR int V02 arg2 NA REG NA
Contained
DefList: { }
N014 ( 1, 4) [000007] -c---------- * CNS_INT int 256 REG NA
Contained
DefList: { }
N016 ( 5, 7) [000008] J------N---- * GE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N018 ( 7, 9) [000009] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
NEW BLOCK BB02
Setting BB02 as the predecessor for determining incoming variable registers of BB03
<RefPosition #4 @20 RefTypeBB BB02 regmask=[] minReg=1>
DefList: { }
N022 ( 61, 58) [000047] ------------ * IL_OFFSET void IL offset: 0x4 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N024 ( 3, 2) [000013] ------------ * LCL_VAR long V03 loc0 NA REG NA
Interval 1: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #5 @25 RefTypeDef <Ivl:1> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N024.t13. LCL_VAR }
N026 ( 6, 4) [000014] *c-XG------- * IND long REG NA
Contained
DefList: { N024.t13. LCL_VAR }
N028 ( 7, 5) [000015] ---XG------- * HWIntrinsic long PopCount REG NA
<RefPosition #6 @28 RefTypeUse <Ivl:1> BB02 regmask=[allInt] minReg=1 last>
Interval 2: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #7 @29 RefTypeDef <Ivl:2> HWIntrinsic BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 1 produce=1
DefList: { N028.t15. HWIntrinsic }
N030 ( 8, 7) [000132] ---XG------- * CAST int <- long REG NA
<RefPosition #8 @30 RefTypeUse <Ivl:2> BB02 regmask=[allInt] minReg=1 last>
Interval 3: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #9 @31 RefTypeDef <Ivl:3> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N030.t132. CAST }
N032 ( 3, 2) [000016] ------------ * LCL_VAR long V03 loc0 NA REG NA
Interval 4: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #10 @33 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N030.t132. CAST; N032.t16. LCL_VAR }
N034 ( 1, 1) [000017] ------------ * CNS_INT int 8 REG NA
Interval 5: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #11 @35 RefTypeDef <Ivl:5> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N030.t132. CAST; N032.t16. LCL_VAR; N034.t17. CNS_INT }
N036 ( 2, 3) [000018] ------------ * CAST long <- int REG NA
<RefPosition #12 @36 RefTypeUse <Ivl:5> BB02 regmask=[allInt] minReg=1 last>
Interval 6: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #13 @37 RefTypeDef <Ivl:6> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N030.t132. CAST; N032.t16. LCL_VAR; N036.t18. CAST }
N038 (???,???) [000136] -c---------- * LEA(b+(i*1)+0) long REG NA
Contained
DefList: { N030.t132. CAST; N032.t16. LCL_VAR; N036.t18. CAST }
N040 ( 8, 7) [000020] *c-XG------- * IND long REG NA
Contained
DefList: { N030.t132. CAST; N032.t16. LCL_VAR; N036.t18. CAST }
N042 ( 9, 8) [000021] ---XG------- * HWIntrinsic long PopCount REG NA
<RefPosition #14 @42 RefTypeUse <Ivl:4> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #15 @42 RefTypeUse <Ivl:6> BB02 regmask=[allInt] minReg=1 last>
Interval 7: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #16 @43 RefTypeDef <Ivl:7> HWIntrinsic BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N030.t132. CAST; N042.t21. HWIntrinsic }
N044 ( 10, 10) [000133] ---XG------- * CAST int <- long REG NA
<RefPosition #17 @44 RefTypeUse <Ivl:7> BB02 regmask=[allInt] minReg=1 last>
Interval 8: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #18 @45 RefTypeDef <Ivl:8> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N030.t132. CAST; N044.t133. CAST }
N046 ( 19, 18) [000022] ---XG------- * ADD int REG NA
<RefPosition #19 @46 RefTypeUse <Ivl:3> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #20 @46 RefTypeUse <Ivl:8> BB02 regmask=[allInt] minReg=1 last>
Interval 9: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #21 @47 RefTypeDef <Ivl:9> ADD BB02 regmask=[allInt] minReg=1>
Assigning related <I3> to <I9>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 2 produce=1
DefList: { N046.t22. ADD }
N048 ( 3, 2) [000023] ------------ * LCL_VAR long V03 loc0 NA REG NA
Interval 10: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #22 @49 RefTypeDef <Ivl:10> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N046.t22. ADD; N048.t23. LCL_VAR }
N050 ( 1, 1) [000024] ------------ * CNS_INT int 2 REG NA
Interval 11: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #23 @51 RefTypeDef <Ivl:11> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N046.t22. ADD; N048.t23. LCL_VAR; N050.t24. CNS_INT }
N052 ( 2, 3) [000025] ------------ * CAST long <- int REG NA
<RefPosition #24 @52 RefTypeUse <Ivl:11> BB02 regmask=[allInt] minReg=1 last>
Interval 12: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #25 @53 RefTypeDef <Ivl:12> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N046.t22. ADD; N048.t23. LCL_VAR; N052.t25. CAST }
N054 ( 1, 1) [000026] ------------ * CNS_INT int 8 REG NA
Interval 13: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #26 @55 RefTypeDef <Ivl:13> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N046.t22. ADD; N048.t23. LCL_VAR; N052.t25. CAST; N054.t26. CNS_INT }
N056 ( 2, 3) [000027] ------------ * CAST long <- int REG NA
<RefPosition #27 @56 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
Interval 14: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #28 @57 RefTypeDef <Ivl:14> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N046.t22. ADD; N048.t23. LCL_VAR; N052.t25. CAST; N056.t27. CAST }
N058 ( 8, 9) [000028] ------------ * MUL long REG NA
<RefPosition #29 @58 RefTypeUse <Ivl:12> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #30 @58 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
Interval 15: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #31 @59 RefTypeDef <Ivl:15> MUL BB02 regmask=[allInt] minReg=1>
Assigning related <I12> to <I15>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N046.t22. ADD; N048.t23. LCL_VAR; N058.t28. MUL }
N060 (???,???) [000137] -c---------- * LEA(b+(i*1)+0) long REG NA
Contained
DefList: { N046.t22. ADD; N048.t23. LCL_VAR; N058.t28. MUL }
N062 ( 14, 13) [000030] *c-XG------- * IND long REG NA
Contained
DefList: { N046.t22. ADD; N048.t23. LCL_VAR; N058.t28. MUL }
N064 ( 15, 14) [000031] ---XG------- * HWIntrinsic long PopCount REG NA
<RefPosition #32 @64 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #33 @64 RefTypeUse <Ivl:15> BB02 regmask=[allInt] minReg=1 last>
Interval 16: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #34 @65 RefTypeDef <Ivl:16> HWIntrinsic BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N046.t22. ADD; N064.t31. HWIntrinsic }
N066 ( 16, 16) [000131] ---XG------- * CAST int <- long REG NA
<RefPosition #35 @66 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
Interval 17: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #36 @67 RefTypeDef <Ivl:17> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N046.t22. ADD; N066.t131. CAST }
N068 ( 36, 35) [000032] ---XG------- * ADD int REG NA
<RefPosition #37 @68 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #38 @68 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
Interval 18: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #39 @69 RefTypeDef <Ivl:18> ADD BB02 regmask=[allInt] minReg=1>
Assigning related <I9> to <I18>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 2 produce=1
DefList: { N068.t32. ADD }
N070 ( 3, 2) [000033] ------------ * LCL_VAR long V03 loc0 NA REG NA
Interval 19: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #40 @71 RefTypeDef <Ivl:19> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N068.t32. ADD; N070.t33. LCL_VAR }
N072 ( 1, 1) [000034] ------------ * CNS_INT int 3 REG NA
Interval 20: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #41 @73 RefTypeDef <Ivl:20> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N068.t32. ADD; N070.t33. LCL_VAR; N072.t34. CNS_INT }
N074 ( 2, 3) [000035] ------------ * CAST long <- int REG NA
<RefPosition #42 @74 RefTypeUse <Ivl:20> BB02 regmask=[allInt] minReg=1 last>
Interval 21: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #43 @75 RefTypeDef <Ivl:21> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N068.t32. ADD; N070.t33. LCL_VAR; N074.t35. CAST }
N076 ( 1, 1) [000036] ------------ * CNS_INT int 8 REG NA
Interval 22: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #44 @77 RefTypeDef <Ivl:22> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N068.t32. ADD; N070.t33. LCL_VAR; N074.t35. CAST; N076.t36. CNS_INT }
N078 ( 2, 3) [000037] ------------ * CAST long <- int REG NA
<RefPosition #45 @78 RefTypeUse <Ivl:22> BB02 regmask=[allInt] minReg=1 last>
Interval 23: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #46 @79 RefTypeDef <Ivl:23> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N068.t32. ADD; N070.t33. LCL_VAR; N074.t35. CAST; N078.t37. CAST }
N080 ( 8, 9) [000038] ------------ * MUL long REG NA
<RefPosition #47 @80 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #48 @80 RefTypeUse <Ivl:23> BB02 regmask=[allInt] minReg=1 last>
Interval 24: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #49 @81 RefTypeDef <Ivl:24> MUL BB02 regmask=[allInt] minReg=1>
Assigning related <I21> to <I24>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N068.t32. ADD; N070.t33. LCL_VAR; N080.t38. MUL }
N082 (???,???) [000138] -c---------- * LEA(b+(i*1)+0) long REG NA
Contained
DefList: { N068.t32. ADD; N070.t33. LCL_VAR; N080.t38. MUL }
N084 ( 14, 13) [000040] *c-XG------- * IND long REG NA
Contained
DefList: { N068.t32. ADD; N070.t33. LCL_VAR; N080.t38. MUL }
N086 ( 15, 14) [000041] ---XG------- * HWIntrinsic long PopCount REG NA
<RefPosition #50 @86 RefTypeUse <Ivl:19> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #51 @86 RefTypeUse <Ivl:24> BB02 regmask=[allInt] minReg=1 last>
Interval 25: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #52 @87 RefTypeDef <Ivl:25> HWIntrinsic BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N068.t32. ADD; N086.t41. HWIntrinsic }
N088 ( 16, 16) [000129] ---XG------- * CAST int <- long REG NA
<RefPosition #53 @88 RefTypeUse <Ivl:25> BB02 regmask=[allInt] minReg=1 last>
Interval 26: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #54 @89 RefTypeDef <Ivl:26> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N068.t32. ADD; N088.t129. CAST }
N090 ( 53, 52) [000042] ---XG------- * ADD int REG NA
<RefPosition #55 @90 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #56 @90 RefTypeUse <Ivl:26> BB02 regmask=[allInt] minReg=1 last>
Interval 27: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #57 @91 RefTypeDef <Ivl:27> ADD BB02 regmask=[allInt] minReg=1>
Assigning related <I18> to <I27>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 2 produce=1
DefList: { N090.t42. ADD }
N092 ( 3, 2) [000012] ------------ * LCL_VAR int V02 arg2 NA REG NA
Interval 28: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #58 @93 RefTypeDef <Ivl:28> LCL_VAR BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N090.t42. ADD; N092.t12. LCL_VAR }
N094 ( 57, 55) [000044] ---XG------- * SUB int REG NA
<RefPosition #59 @94 RefTypeUse <Ivl:28> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #60 @94 RefTypeUse <Ivl:27> BB02 regmask=[allInt] minReg=1 last>
Interval 29: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #61 @95 RefTypeDef <Ivl:29> SUB BB02 regmask=[allInt] minReg=1>
Assigning related <I28> to <I29>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N094.t44. SUB }
N096 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2 NA REG NA
<RefPosition #62 @96 RefTypeUse <Ivl:29> BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N098 ( 16, 15) [000057] ------------ * IL_OFFSET void IL offset: 0x34 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N100 ( 3, 2) [000048] -c---------- * LCL_VAR long V03 loc0 NA REG NA
Contained
DefList: { }
N102 ( 1, 1) [000049] ------------ * CNS_INT int 4 REG NA
Interval 30: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #63 @103 RefTypeDef <Ivl:30> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N102.t49. CNS_INT }
N104 ( 2, 3) [000050] ------------ * CAST long <- int REG NA
<RefPosition #64 @104 RefTypeUse <Ivl:30> BB02 regmask=[allInt] minReg=1 last>
Interval 31: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #65 @105 RefTypeDef <Ivl:31> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N104.t50. CAST }
N106 ( 1, 1) [000051] ------------ * CNS_INT int 8 REG NA
Interval 32: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #66 @107 RefTypeDef <Ivl:32> CNS_INT BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N104.t50. CAST; N106.t51. CNS_INT }
N108 ( 2, 3) [000052] ------------ * CAST long <- int REG NA
<RefPosition #67 @108 RefTypeUse <Ivl:32> BB02 regmask=[allInt] minReg=1 last>
Interval 33: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #68 @109 RefTypeDef <Ivl:33> CAST BB02 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N104.t50. CAST; N108.t52. CAST }
N110 ( 8, 9) [000053] ------------ * MUL long REG NA
<RefPosition #69 @110 RefTypeUse <Ivl:31> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #70 @110 RefTypeUse <Ivl:33> BB02 regmask=[allInt] minReg=1 last>
Interval 34: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #71 @111 RefTypeDef <Ivl:34> MUL BB02 regmask=[allInt] minReg=1>
Assigning related <I31> to <I34>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 2 produce=1
DefList: { N110.t53. MUL }
N112 ( 12, 12) [000054] ------------ * ADD long REG NA
<RefPosition #72 @112 RefTypeUse <Ivl:34> BB02 regmask=[allInt] minReg=1 last>
Interval 35: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #73 @113 RefTypeDef <Ivl:35> ADD BB02 regmask=[allInt] minReg=1>
Assigning related <I34> to <I35>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N112.t54. ADD }
N114 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
<RefPosition #74 @114 RefTypeUse <Ivl:35> BB02 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
NEW BLOCK BB04
Setting BB04 as the predecessor for determining incoming variable registers of BB03
<RefPosition #75 @116 RefTypeBB BB04 regmask=[] minReg=1>
DefList: { }
N118 ( 7, 5) [000062] ------------ * IL_OFFSET void IL offset: 0x43 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N120 ( 3, 2) [000059] ------------ * LCL_VAR int V02 arg2 NA REG NA
Interval 36: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #76 @121 RefTypeDef <Ivl:36> LCL_VAR BB04 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N120.t59. LCL_VAR }
N122 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1 NA REG NA
<RefPosition #77 @122 RefTypeUse <Ivl:36> BB04 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
NEW BLOCK BB06
Setting BB06 as the predecessor for determining incoming variable registers of BB04
<RefPosition #78 @124 RefTypeBB BB06 regmask=[] minReg=1>
DefList: { }
N126 ( 7, 6) [000068] ------------ * IL_OFFSET void IL offset: 0x59 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N128 ( 3, 2) [000064] -c---------- * LCL_VAR int V02 arg2 NA REG NA
Contained
DefList: { }
N130 ( 1, 1) [000065] -c---------- * CNS_INT int 0 REG NA
Contained
DefList: { }
N132 ( 5, 4) [000066] J------N---- * GT void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N134 ( 7, 6) [000067] ------------ * JTRUE void REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
NEW BLOCK BB05
Setting BB05 as the predecessor for determining incoming variable registers of BB06
<RefPosition #79 @136 RefTypeBB BB05 regmask=[] minReg=1>
DefList: { }
N138 ( 7, 5) [000073] ------------ * IL_OFFSET void IL offset: 0x47 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N140 ( 3, 2) [000070] ------------ * LCL_VAR int V02 arg2 NA REG NA
Interval 37: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #80 @141 RefTypeDef <Ivl:37> LCL_VAR BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N140.t70. LCL_VAR }
N142 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1 NA REG NA
<RefPosition #81 @142 RefTypeUse <Ivl:37> BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N144 ( 16, 13) [000082] ------------ * IL_OFFSET void IL offset: 0x49 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N146 ( 3, 2) [000074] ------------ * LCL_VAR int V02 arg2 NA REG NA
Interval 38: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #82 @147 RefTypeDef <Ivl:38> LCL_VAR BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N146.t74. LCL_VAR }
N148 ( 3, 2) [000075] ------------ * LCL_VAR long V03 loc0 NA REG NA
Interval 39: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #83 @149 RefTypeDef <Ivl:39> LCL_VAR BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N146.t74. LCL_VAR; N148.t75. LCL_VAR }
N150 ( 6, 4) [000076] *c-XG------- * IND long REG NA
Contained
DefList: { N146.t74. LCL_VAR; N148.t75. LCL_VAR }
N152 ( 7, 5) [000077] ---XG------- * HWIntrinsic long PopCount REG NA
<RefPosition #84 @152 RefTypeUse <Ivl:39> BB05 regmask=[allInt] minReg=1 last>
Interval 40: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #85 @153 RefTypeDef <Ivl:40> HWIntrinsic BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 1 produce=1
DefList: { N146.t74. LCL_VAR; N152.t77. HWIntrinsic }
N154 ( 8, 7) [000078] ---XG------- * CAST int <- long REG NA
<RefPosition #86 @154 RefTypeUse <Ivl:40> BB05 regmask=[allInt] minReg=1 last>
Interval 41: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #87 @155 RefTypeDef <Ivl:41> CAST BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N146.t74. LCL_VAR; N154.t78. CAST }
N156 ( 12, 10) [000079] ---XG------- * SUB int REG NA
<RefPosition #88 @156 RefTypeUse <Ivl:38> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #89 @156 RefTypeUse <Ivl:41> BB05 regmask=[allInt] minReg=1 last>
Interval 42: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #90 @157 RefTypeDef <Ivl:42> SUB BB05 regmask=[allInt] minReg=1>
Assigning related <I38> to <I42>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N156.t79. SUB }
N158 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2 NA REG NA
<RefPosition #91 @158 RefTypeUse <Ivl:42> BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N160 ( 10, 9) [000089] ------------ * IL_OFFSET void IL offset: 0x55 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N162 ( 3, 2) [000083] -c---------- * LCL_VAR long V03 loc0 NA REG NA
Contained
DefList: { }
N164 ( 1, 1) [000084] ------------ * CNS_INT int 8 REG NA
Interval 43: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #92 @165 RefTypeDef <Ivl:43> CNS_INT BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N164.t84. CNS_INT }
N166 ( 2, 3) [000085] ------------ * CAST long <- int REG NA
<RefPosition #93 @166 RefTypeUse <Ivl:43> BB05 regmask=[allInt] minReg=1 last>
Interval 44: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #94 @167 RefTypeDef <Ivl:44> CAST BB05 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N166.t85. CAST }
N168 ( 6, 6) [000086] ------------ * ADD long REG NA
<RefPosition #95 @168 RefTypeUse <Ivl:44> BB05 regmask=[allInt] minReg=1 last>
Interval 45: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #96 @169 RefTypeDef <Ivl:45> ADD BB05 regmask=[allInt] minReg=1>
Assigning related <I44> to <I45>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N168.t86. ADD }
N170 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
<RefPosition #97 @170 RefTypeUse <Ivl:45> BB05 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
NEW BLOCK BB07
Setting BB07 as the predecessor for determining incoming variable registers of BB06
<RefPosition #98 @172 RefTypeBB BB07 regmask=[] minReg=1>
DefList: { }
N174 ( 10, 9) [000097] ------------ * IL_OFFSET void IL offset: 0x5d REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N176 ( 3, 2) [000091] ------------ * LCL_VAR long V03 loc0 NA REG NA
Interval 46: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #99 @177 RefTypeDef <Ivl:46> LCL_VAR BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N176.t91. LCL_VAR }
N178 ( 1, 1) [000092] ------------ * CNS_INT int 8 REG NA
Interval 47: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #100 @179 RefTypeDef <Ivl:47> CNS_INT BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N176.t91. LCL_VAR; N178.t92. CNS_INT }
N180 ( 2, 3) [000093] ------------ * CAST long <- int REG NA
<RefPosition #101 @180 RefTypeUse <Ivl:47> BB07 regmask=[allInt] minReg=1 last>
Interval 48: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #102 @181 RefTypeDef <Ivl:48> CAST BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N176.t91. LCL_VAR; N180.t93. CAST }
N182 ( 6, 6) [000094] ------------ * SUB long REG NA
<RefPosition #103 @182 RefTypeUse <Ivl:46> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #104 @182 RefTypeUse <Ivl:48> BB07 regmask=[allInt] minReg=1 last>
Interval 49: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #105 @183 RefTypeDef <Ivl:49> SUB BB07 regmask=[allInt] minReg=1>
Assigning related <I46> to <I49>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N182.t94. SUB }
N184 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
<RefPosition #106 @184 RefTypeUse <Ivl:49> BB07 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N186 ( 26, 21) [000113] ------------ * IL_OFFSET void IL offset: 0x61 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N188 ( 3, 2) [000100] ------------ * LCL_VAR int V04 loc1 NA REG NA
Interval 50: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #107 @189 RefTypeDef <Ivl:50> LCL_VAR BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N188.t100. LCL_VAR }
N190 ( 1, 1) [000101] -c---------- * CNS_INT int -1 REG NA
Contained
DefList: { N188.t100. LCL_VAR }
N192 ( 5, 4) [000102] ------------ * ADD int REG NA
<RefPosition #108 @192 RefTypeUse <Ivl:50> BB07 regmask=[allInt] minReg=1 last>
Interval 51: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #109 @193 RefTypeDef <Ivl:51> ADD BB07 regmask=[allInt] minReg=1>
Assigning related <I50> to <I51>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N192.t102. ADD }
N194 ( 1, 1) [000098] ------------ * CNS_INT int 1 REG NA
Interval 52: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #110 @195 RefTypeDef <Ivl:52> CNS_INT BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N192.t102. ADD; N194.t98. CNS_INT }
N196 ( 2, 3) [000099] ------------ * CAST long <- int REG NA
<RefPosition #111 @196 RefTypeUse <Ivl:52> BB07 regmask=[allInt] minReg=1 last>
Interval 53: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #112 @197 RefTypeDef <Ivl:53> CAST BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N192.t102. ADD; N196.t99. CAST }
N198 ( 13, 10) [000105] ------------ * LSH long REG NA
<RefPosition #113 @198 RefTypeUse <Ivl:53> BB07 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #114 @198 RefTypeFixedReg <Reg:rcx> BB07 regmask=[rcx] minReg=1>
<RefPosition #115 @198 RefTypeUse <Ivl:51> BB07 regmask=[rcx] minReg=1 last fixed>
<RefPosition #116 @199 RefTypeKill <Reg:rcx> BB07 regmask=[rcx] minReg=1>
Interval 54: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #117 @199 RefTypeDef <Ivl:54> LSH BB07 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
Assigning related <I53> to <I54>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N198.t105. LSH }
N200 ( 3, 2) [000106] ------------ * LCL_VAR long V03 loc0 NA REG NA
Interval 55: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #118 @201 RefTypeDef <Ivl:55> LCL_VAR BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N198.t105. LSH; N200.t106. LCL_VAR }
N202 ( 6, 4) [000107] *c-XG------- * IND long REG NA
Contained
DefList: { N198.t105. LSH; N200.t106. LCL_VAR }
N204 ( 20, 15) [000108] ---XG------- * HWIntrinsic long ParallelBitDeposit REG NA
<RefPosition #119 @204 RefTypeUse <Ivl:54> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #120 @204 RefTypeUse <Ivl:55> BB07 regmask=[allInt] minReg=1 last>
Interval 56: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #121 @205 RefTypeDef <Ivl:56> HWIntrinsic BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 2 produce=1
DefList: { N204.t108. HWIntrinsic }
N206 ( 21, 16) [000109] ---XG------- * HWIntrinsic long TrailingZeroCount REG NA
<RefPosition #122 @206 RefTypeUse <Ivl:56> BB07 regmask=[allInt] minReg=1 last>
Interval 57: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #123 @207 RefTypeDef <Ivl:57> HWIntrinsic BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 1 produce=1
DefList: { N206.t109. HWIntrinsic }
N208 ( 22, 18) [000110] ---XG------- * CAST int <- long REG NA
<RefPosition #124 @208 RefTypeUse <Ivl:57> BB07 regmask=[allInt] minReg=1 last>
Interval 58: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #125 @209 RefTypeDef <Ivl:58> CAST BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N208.t110. CAST }
N210 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2 NA REG NA
<RefPosition #126 @210 RefTypeUse <Ivl:58> BB07 regmask=[allInt] minReg=1 last>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
DefList: { }
N212 ( 40, 21) [000127] ------------ * IL_OFFSET void IL offset: 0x78 REG NA
+<TreeNodeInfo 0=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=0
DefList: { }
N214 ( 3, 2) [000114] ------------ * LCL_VAR long V03 loc0 NA REG NA
Interval 59: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #127 @215 RefTypeDef <Ivl:59> LCL_VAR BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N214.t114. LCL_VAR }
N216 ( 3, 2) [000115] -c---------- * LCL_VAR long V00 arg0 NA REG NA
Contained
DefList: { N214.t114. LCL_VAR }
N218 ( 7, 5) [000116] ------------ * SUB long REG NA
<RefPosition #128 @218 RefTypeUse <Ivl:59> BB07 regmask=[allInt] minReg=1 last>
Interval 60: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #129 @219 RefTypeDef <Ivl:60> SUB BB07 regmask=[allInt] minReg=1>
Assigning related <I59> to <I60>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N218.t116. SUB }
N220 ( 1, 1) [000117] ------------ * CNS_INT int 8 REG NA
Interval 61: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #130 @221 RefTypeDef <Ivl:61> CNS_INT BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=0 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 0 produce=1
DefList: { N218.t116. SUB; N220.t117. CNS_INT }
N222 ( 2, 3) [000118] ------------ * CAST long <- int REG NA
<RefPosition #131 @222 RefTypeUse <Ivl:61> BB07 regmask=[allInt] minReg=1 last>
Interval 62: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #132 @223 RefTypeDef <Ivl:62> CAST BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N218.t116. SUB; N222.t118. CAST }
N224 ( 29, 11) [000119] ---X-------- * DIV long REG NA
<RefPosition #133 @224 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #134 @224 RefTypeUse <Ivl:60> BB07 regmask=[rax] minReg=1 last fixed>
<RefPosition #135 @224 RefTypeUse <Ivl:62> BB07 regmask=[rcx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #136 @225 RefTypeKill <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #137 @225 RefTypeKill <Reg:rdx> BB07 regmask=[rdx] minReg=1>
Interval 63: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #138 @225 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #139 @225 RefTypeDef <Ivl:63> DIV BB07 regmask=[rax] minReg=1 fixed>
Assigning related <I60> to <I63>
+<TreeNodeInfo 1=2 0i 0f src=[allInt] int=[allInt] dst=[allInt] I D>[--]
consume= 2 produce=1
DefList: { N224.t119. DIV }
N226 ( 30, 13) [000134] ---X-------- * CAST int <- long REG NA
<RefPosition #140 @226 RefTypeUse <Ivl:63> BB07 regmask=[allInt] minReg=1 last>
Interval 64: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #141 @227 RefTypeDef <Ivl:64> CAST BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[-O]
consume= 1 produce=1
DefList: { N226.t134. CAST }
N228 ( 1, 1) [000120] -c---------- * CNS_INT int 64 REG NA
Contained
DefList: { N226.t134. CAST }
N230 ( 35, 17) [000122] ---X-------- * MUL int REG NA
<RefPosition #142 @230 RefTypeUse <Ivl:64> BB07 regmask=[allInt] minReg=1 last>
Interval 65: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #143 @231 RefTypeDef <Ivl:65> MUL BB07 regmask=[allInt] minReg=1>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N230.t122. MUL }
N232 ( 3, 2) [000124] -c---------- * LCL_VAR int V05 loc2 NA REG NA
Contained
DefList: { N230.t122. MUL }
N234 ( 39, 20) [000125] ---X-------- * ADD int REG NA
<RefPosition #144 @234 RefTypeUse <Ivl:65> BB07 regmask=[allInt] minReg=1 last>
Interval 66: RefPositions {} physReg:NA Preferences=[allInt]
<RefPosition #145 @235 RefTypeDef <Ivl:66> ADD BB07 regmask=[allInt] minReg=1>
Assigning related <I65> to <I66>
+<TreeNodeInfo 1=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=1
DefList: { N234.t125. ADD }
N236 ( 40, 21) [000126] ---X-------- * RETURN int REG NA
<RefPosition #146 @236 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #147 @236 RefTypeUse <Ivl:66> BB07 regmask=[rax] minReg=1 last fixed>
+<TreeNodeInfo 0=1 0i 0f src=[allInt] int=[allInt] dst=[allInt] I>[--]
consume= 1 produce=0
Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval 0: RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#5@25 #6@28} physReg:NA Preferences=[allInt]
Interval 2: (interfering uses) RefPositions {#7@29 #8@30} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#9@31 #19@46} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {#10@33 #14@42} physReg:NA Preferences=[allInt]
Interval 5: (constant) RefPositions {#11@35 #12@36} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {#13@37 #15@42} physReg:NA Preferences=[allInt]
Interval 7: (interfering uses) RefPositions {#16@43 #17@44} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {#18@45 #20@46} physReg:NA Preferences=[allInt]
Interval 9: RefPositions {#21@47 #37@68} physReg:NA Preferences=[allInt] RelatedInterval <I3>[0000000001408C18]
Interval 10: RefPositions {#22@49 #32@64} physReg:NA Preferences=[allInt]
Interval 11: (constant) RefPositions {#23@51 #24@52} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#25@53 #29@58} physReg:NA Preferences=[allInt]
Interval 13: (constant) RefPositions {#26@55 #27@56} physReg:NA Preferences=[allInt]
Interval 14: RefPositions {#28@57 #30@58} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#31@59 #33@64} physReg:NA Preferences=[allInt] RelatedInterval <I12>[00000000014095A8]
Interval 16: (interfering uses) RefPositions {#34@65 #35@66} physReg:NA Preferences=[allInt]
Interval 17: RefPositions {#36@67 #38@68} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#39@69 #55@90} physReg:NA Preferences=[allInt] RelatedInterval <I9>[00000000014092F8]
Interval 19: RefPositions {#40@71 #50@86} physReg:NA Preferences=[allInt]
Interval 20: (constant) RefPositions {#41@73 #42@74} physReg:NA Preferences=[allInt]
Interval 21: RefPositions {#43@75 #47@80} physReg:NA Preferences=[allInt]
Interval 22: (constant) RefPositions {#44@77 #45@78} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#46@79 #48@80} physReg:NA Preferences=[allInt]
Interval 24: RefPositions {#49@81 #51@86} physReg:NA Preferences=[allInt] RelatedInterval <I21>[0000000001409FB8]
Interval 25: (interfering uses) RefPositions {#52@87 #53@88} physReg:NA Preferences=[allInt]
Interval 26: RefPositions {#54@89 #56@90} physReg:NA Preferences=[allInt]
Interval 27: RefPositions {#57@91 #60@94} physReg:NA Preferences=[allInt] RelatedInterval <I18>[0000000001409D08]
Interval 28: RefPositions {#58@93 #59@94} physReg:NA Preferences=[allInt]
Interval 29: (interfering uses) RefPositions {#61@95 #62@96} physReg:NA Preferences=[allInt] RelatedInterval <I28>[000000000140A7E8]
Interval 30: (constant) RefPositions {#63@103 #64@104} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#65@105 #69@110} physReg:NA Preferences=[allInt]
Interval 32: (constant) RefPositions {#66@107 #67@108} physReg:NA Preferences=[allInt]
Interval 33: RefPositions {#68@109 #70@110} physReg:NA Preferences=[allInt]
Interval 34: RefPositions {#71@111 #72@112} physReg:NA Preferences=[allInt] RelatedInterval <I31>[000000000140AC18]
Interval 35: RefPositions {#73@113 #74@114} physReg:NA Preferences=[allInt] RelatedInterval <I34>[000000000140AF48]
Interval 36: RefPositions {#76@121 #77@122} physReg:NA Preferences=[allInt]
Interval 37: RefPositions {#80@141 #81@142} physReg:NA Preferences=[allInt]
Interval 38: RefPositions {#82@147 #88@156} physReg:NA Preferences=[allInt]
Interval 39: RefPositions {#83@149 #84@152} physReg:NA Preferences=[allInt]
Interval 40: (interfering uses) RefPositions {#85@153 #86@154} physReg:NA Preferences=[allInt]
Interval 41: RefPositions {#87@155 #89@156} physReg:NA Preferences=[allInt]
Interval 42: (interfering uses) RefPositions {#90@157 #91@158} physReg:NA Preferences=[allInt] RelatedInterval <I38>[000000000140B708]
Interval 43: (constant) RefPositions {#92@165 #93@166} physReg:NA Preferences=[allInt]
Interval 44: RefPositions {#94@167 #95@168} physReg:NA Preferences=[allInt]
Interval 45: RefPositions {#96@169 #97@170} physReg:NA Preferences=[allInt] RelatedInterval <I44>[000000000140BE68]
Interval 46: RefPositions {#99@177 #103@182} physReg:NA Preferences=[allInt]
Interval 47: (constant) RefPositions {#100@179 #101@180} physReg:NA Preferences=[allInt]
Interval 48: RefPositions {#102@181 #104@182} physReg:NA Preferences=[allInt]
Interval 49: (interfering uses) RefPositions {#105@183 #106@184} physReg:NA Preferences=[allInt] RelatedInterval <I46>[000000000140C148]
Interval 50: RefPositions {#107@189 #108@192} physReg:NA Preferences=[allInt]
Interval 51: RefPositions {#109@193 #115@198} physReg:NA Preferences=[rcx] RelatedInterval <I50>[000000000140C608]
Interval 52: (constant) RefPositions {#110@195 #111@196} physReg:NA Preferences=[allInt]
Interval 53: RefPositions {#112@197 #113@198} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 54: (interfering uses) RefPositions {#117@199 #119@204} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15] RelatedInterval <I53>[000000000140C938]
Interval 55: RefPositions {#118@201 #120@204} physReg:NA Preferences=[allInt]
Interval 56: RefPositions {#121@205 #122@206} physReg:NA Preferences=[allInt]
Interval 57: (interfering uses) RefPositions {#123@207 #124@208} physReg:NA Preferences=[allInt]
Interval 58: RefPositions {#125@209 #126@210} physReg:NA Preferences=[allInt]
Interval 59: RefPositions {#127@215 #128@218} physReg:NA Preferences=[allInt]
Interval 60: RefPositions {#129@219 #134@224} physReg:NA Preferences=[rax] RelatedInterval <I59>[000000000140D118]
Interval 61: (constant) RefPositions {#130@221 #131@222} physReg:NA Preferences=[allInt]
Interval 62: RefPositions {#132@223 #135@224} physReg:NA Preferences=[rcx rbx rsi rdi r8-r15]
Interval 63: (interfering uses) RefPositions {#139@225 #140@226} physReg:NA Preferences=[rax] RelatedInterval <I60>[000000000140D268]
Interval 64: RefPositions {#141@227 #142@230} physReg:NA Preferences=[allInt]
Interval 65: RefPositions {#143@231 #144@234} physReg:NA Preferences=[allInt]
Interval 66: RefPositions {#145@235 #147@236} physReg:NA Preferences=[rax] RelatedInterval <I65>[000000000140D8F8]
------------
REFPOSITIONS BEFORE VALIDATING INTERVALS:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @8 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #4 @20 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #5 @25 RefTypeDef <Ivl:1> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #6 @28 RefTypeUse <Ivl:1> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #7 @29 RefTypeDef <Ivl:2> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #8 @30 RefTypeUse <Ivl:2> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #9 @31 RefTypeDef <Ivl:3> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #10 @33 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #11 @35 RefTypeDef <Ivl:5> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #12 @36 RefTypeUse <Ivl:5> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #13 @37 RefTypeDef <Ivl:6> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #14 @42 RefTypeUse <Ivl:4> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #15 @42 RefTypeUse <Ivl:6> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #16 @43 RefTypeDef <Ivl:7> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #17 @44 RefTypeUse <Ivl:7> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #18 @45 RefTypeDef <Ivl:8> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @46 RefTypeUse <Ivl:3> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #20 @46 RefTypeUse <Ivl:8> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @47 RefTypeDef <Ivl:9> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @49 RefTypeDef <Ivl:10> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #23 @51 RefTypeDef <Ivl:11> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @52 RefTypeUse <Ivl:11> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #25 @53 RefTypeDef <Ivl:12> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #26 @55 RefTypeDef <Ivl:13> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @56 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #28 @57 RefTypeDef <Ivl:14> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #29 @58 RefTypeUse <Ivl:12> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #30 @58 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #31 @59 RefTypeDef <Ivl:15> MUL BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @64 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #33 @64 RefTypeUse <Ivl:15> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #34 @65 RefTypeDef <Ivl:16> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #35 @66 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #36 @67 RefTypeDef <Ivl:17> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #37 @68 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #38 @68 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #39 @69 RefTypeDef <Ivl:18> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #40 @71 RefTypeDef <Ivl:19> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #41 @73 RefTypeDef <Ivl:20> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #42 @74 RefTypeUse <Ivl:20> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #43 @75 RefTypeDef <Ivl:21> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #44 @77 RefTypeDef <Ivl:22> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #45 @78 RefTypeUse <Ivl:22> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #46 @79 RefTypeDef <Ivl:23> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #47 @80 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #48 @80 RefTypeUse <Ivl:23> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #49 @81 RefTypeDef <Ivl:24> MUL BB02 regmask=[allInt] minReg=1>
<RefPosition #50 @86 RefTypeUse <Ivl:19> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #51 @86 RefTypeUse <Ivl:24> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #52 @87 RefTypeDef <Ivl:25> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #53 @88 RefTypeUse <Ivl:25> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #54 @89 RefTypeDef <Ivl:26> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #55 @90 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #56 @90 RefTypeUse <Ivl:26> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #57 @91 RefTypeDef <Ivl:27> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #58 @93 RefTypeDef <Ivl:28> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #59 @94 RefTypeUse <Ivl:28> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #60 @94 RefTypeUse <Ivl:27> BB02 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #61 @95 RefTypeDef <Ivl:29> SUB BB02 regmask=[allInt] minReg=1>
<RefPosition #62 @96 RefTypeUse <Ivl:29> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #63 @103 RefTypeDef <Ivl:30> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #64 @104 RefTypeUse <Ivl:30> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #65 @105 RefTypeDef <Ivl:31> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #66 @107 RefTypeDef <Ivl:32> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #67 @108 RefTypeUse <Ivl:32> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #68 @109 RefTypeDef <Ivl:33> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #69 @110 RefTypeUse <Ivl:31> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #70 @110 RefTypeUse <Ivl:33> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #71 @111 RefTypeDef <Ivl:34> MUL BB02 regmask=[allInt] minReg=1>
<RefPosition #72 @112 RefTypeUse <Ivl:34> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #73 @113 RefTypeDef <Ivl:35> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #74 @114 RefTypeUse <Ivl:35> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #75 @116 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #76 @121 RefTypeDef <Ivl:36> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #77 @122 RefTypeUse <Ivl:36> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #78 @124 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #79 @136 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #80 @141 RefTypeDef <Ivl:37> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #81 @142 RefTypeUse <Ivl:37> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #82 @147 RefTypeDef <Ivl:38> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #83 @149 RefTypeDef <Ivl:39> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #84 @152 RefTypeUse <Ivl:39> BB05 regmask=[allInt] minReg=1 last delay>
<RefPosition #85 @153 RefTypeDef <Ivl:40> HWIntrinsic BB05 regmask=[allInt] minReg=1>
<RefPosition #86 @154 RefTypeUse <Ivl:40> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #87 @155 RefTypeDef <Ivl:41> CAST BB05 regmask=[allInt] minReg=1>
<RefPosition #88 @156 RefTypeUse <Ivl:38> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #89 @156 RefTypeUse <Ivl:41> BB05 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #90 @157 RefTypeDef <Ivl:42> SUB BB05 regmask=[allInt] minReg=1>
<RefPosition #91 @158 RefTypeUse <Ivl:42> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #92 @165 RefTypeDef <Ivl:43> CNS_INT BB05 regmask=[allInt] minReg=1>
<RefPosition #93 @166 RefTypeUse <Ivl:43> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #94 @167 RefTypeDef <Ivl:44> CAST BB05 regmask=[allInt] minReg=1>
<RefPosition #95 @168 RefTypeUse <Ivl:44> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #96 @169 RefTypeDef <Ivl:45> ADD BB05 regmask=[allInt] minReg=1>
<RefPosition #97 @170 RefTypeUse <Ivl:45> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #98 @172 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #99 @177 RefTypeDef <Ivl:46> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #100 @179 RefTypeDef <Ivl:47> CNS_INT BB07 regmask=[allInt] minReg=1>
<RefPosition #101 @180 RefTypeUse <Ivl:47> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #102 @181 RefTypeDef <Ivl:48> CAST BB07 regmask=[allInt] minReg=1>
<RefPosition #103 @182 RefTypeUse <Ivl:46> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #104 @182 RefTypeUse <Ivl:48> BB07 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #105 @183 RefTypeDef <Ivl:49> SUB BB07 regmask=[allInt] minReg=1>
<RefPosition #106 @184 RefTypeUse <Ivl:49> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #107 @189 RefTypeDef <Ivl:50> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #108 @192 RefTypeUse <Ivl:50> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #109 @193 RefTypeDef <Ivl:51> ADD BB07 regmask=[rcx] minReg=1>
<RefPosition #110 @195 RefTypeDef <Ivl:52> CNS_INT BB07 regmask=[allInt] minReg=1>
<RefPosition #111 @196 RefTypeUse <Ivl:52> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #112 @197 RefTypeDef <Ivl:53> CAST BB07 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #113 @198 RefTypeUse <Ivl:53> BB07 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #114 @198 RefTypeFixedReg <Reg:rcx> BB07 regmask=[rcx] minReg=1>
<RefPosition #115 @198 RefTypeUse <Ivl:51> BB07 regmask=[rcx] minReg=1 last fixed delay>
<RefPosition #116 @199 RefTypeKill <Reg:rcx> BB07 regmask=[rcx] minReg=1 last>
<RefPosition #117 @199 RefTypeDef <Ivl:54> LSH BB07 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #118 @201 RefTypeDef <Ivl:55> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #119 @204 RefTypeUse <Ivl:54> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #120 @204 RefTypeUse <Ivl:55> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #121 @205 RefTypeDef <Ivl:56> HWIntrinsic BB07 regmask=[allInt] minReg=1>
<RefPosition #122 @206 RefTypeUse <Ivl:56> BB07 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #123 @207 RefTypeDef <Ivl:57> HWIntrinsic BB07 regmask=[allInt] minReg=1>
<RefPosition #124 @208 RefTypeUse <Ivl:57> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #125 @209 RefTypeDef <Ivl:58> CAST BB07 regmask=[allInt] minReg=1>
<RefPosition #126 @210 RefTypeUse <Ivl:58> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #127 @215 RefTypeDef <Ivl:59> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #128 @218 RefTypeUse <Ivl:59> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #129 @219 RefTypeDef <Ivl:60> SUB BB07 regmask=[rax] minReg=1>
<RefPosition #130 @221 RefTypeDef <Ivl:61> CNS_INT BB07 regmask=[allInt] minReg=1>
<RefPosition #131 @222 RefTypeUse <Ivl:61> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #132 @223 RefTypeDef <Ivl:62> CAST BB07 regmask=[rcx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #133 @224 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #134 @224 RefTypeUse <Ivl:60> BB07 regmask=[rax] minReg=1 last fixed>
<RefPosition #135 @224 RefTypeUse <Ivl:62> BB07 regmask=[rcx rbx rsi rdi r8-r15] minReg=1 last delay regOptional>
<RefPosition #136 @225 RefTypeKill <Reg:rax> BB07 regmask=[rax] minReg=1 last>
<RefPosition #137 @225 RefTypeKill <Reg:rdx> BB07 regmask=[rdx] minReg=1 last>
<RefPosition #138 @225 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #139 @225 RefTypeDef <Ivl:63> DIV BB07 regmask=[rax] minReg=1 fixed>
<RefPosition #140 @226 RefTypeUse <Ivl:63> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #141 @227 RefTypeDef <Ivl:64> CAST BB07 regmask=[allInt] minReg=1>
<RefPosition #142 @230 RefTypeUse <Ivl:64> BB07 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #143 @231 RefTypeDef <Ivl:65> MUL BB07 regmask=[allInt] minReg=1>
<RefPosition #144 @234 RefTypeUse <Ivl:65> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #145 @235 RefTypeDef <Ivl:66> ADD BB07 regmask=[rax] minReg=1>
<RefPosition #146 @236 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #147 @236 RefTypeUse <Ivl:66> BB07 regmask=[rax] minReg=1 last fixed>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters:
BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. V00 MEM
Def:<I0>(#1)
N006. V03 MEM
Use:<I0>(#2) *
BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
=====
N010. IL_OFFSET IL offset: 0x3b REG NA
N012. V02 MEM
N014. CNS_INT 256 REG NA
N016. GE
N018. JTRUE
BB02 [004..03B), preds={BB03} succs={BB03}
=====
N022. IL_OFFSET IL offset: 0x4 REG NA
N024. V03 MEM
Def:<I1>(#5)
N026. IND
N028. HWIntrinsic
Use:<I1>(#6) *
Def:<I2>(#7)
N030. CAST
Use:<I2>(#8) *
Def:<I3>(#9)
N032. V03 MEM
Def:<I4>(#10)
N034. CNS_INT 8 REG NA
Def:<I5>(#11)
N036. CAST
Use:<I5>(#12) *
Def:<I6>(#13)
N038. LEA(b+(i*1)+0)
N040. IND
N042. HWIntrinsic
Use:<I4>(#14) *
Use:<I6>(#15) *
Def:<I7>(#16)
N044. CAST
Use:<I7>(#17) *
Def:<I8>(#18)
N046. ADD
Use:<I3>(#19) *
Use:<I8>(#20) *
Def:<I9>(#21) Pref:<I3>
N048. V03 MEM
Def:<I10>(#22)
N050. CNS_INT 2 REG NA
Def:<I11>(#23)
N052. CAST
Use:<I11>(#24) *
Def:<I12>(#25)
N054. CNS_INT 8 REG NA
Def:<I13>(#26)
N056. CAST
Use:<I13>(#27) *
Def:<I14>(#28)
N058. MUL
Use:<I12>(#29) *
Use:<I14>(#30) *
Def:<I15>(#31) Pref:<I12>
N060. LEA(b+(i*1)+0)
N062. IND
N064. HWIntrinsic
Use:<I10>(#32) *
Use:<I15>(#33) *
Def:<I16>(#34)
N066. CAST
Use:<I16>(#35) *
Def:<I17>(#36)
N068. ADD
Use:<I9>(#37) *
Use:<I17>(#38) *
Def:<I18>(#39) Pref:<I9>
N070. V03 MEM
Def:<I19>(#40)
N072. CNS_INT 3 REG NA
Def:<I20>(#41)
N074. CAST
Use:<I20>(#42) *
Def:<I21>(#43)
N076. CNS_INT 8 REG NA
Def:<I22>(#44)
N078. CAST
Use:<I22>(#45) *
Def:<I23>(#46)
N080. MUL
Use:<I21>(#47) *
Use:<I23>(#48) *
Def:<I24>(#49) Pref:<I21>
N082. LEA(b+(i*1)+0)
N084. IND
N086. HWIntrinsic
Use:<I19>(#50) *
Use:<I24>(#51) *
Def:<I25>(#52)
N088. CAST
Use:<I25>(#53) *
Def:<I26>(#54)
N090. ADD
Use:<I18>(#55) *
Use:<I26>(#56) *
Def:<I27>(#57) Pref:<I18>
N092. V02 MEM
Def:<I28>(#58)
N094. SUB
Use:<I28>(#59) *
Use:<I27>(#60) *
Def:<I29>(#61) Pref:<I28>
N096. V02 MEM
Use:<I29>(#62) *
N098. IL_OFFSET IL offset: 0x34 REG NA
N100. V03 MEM
N102. CNS_INT 4 REG NA
Def:<I30>(#63)
N104. CAST
Use:<I30>(#64) *
Def:<I31>(#65)
N106. CNS_INT 8 REG NA
Def:<I32>(#66)
N108. CAST
Use:<I32>(#67) *
Def:<I33>(#68)
N110. MUL
Use:<I31>(#69) *
Use:<I33>(#70) *
Def:<I34>(#71) Pref:<I31>
N112. ADD
Use:<I34>(#72) *
Def:<I35>(#73) Pref:<I34>
N114. V03 MEM
Use:<I35>(#74) *
BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
=====
N118. IL_OFFSET IL offset: 0x43 REG NA
N120. V02 MEM
Def:<I36>(#76)
N122. V04 MEM
Use:<I36>(#77) *
BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
=====
N126. IL_OFFSET IL offset: 0x59 REG NA
N128. V02 MEM
N130. CNS_INT 0 REG NA
N132. GT
N134. JTRUE
BB05 [047..059), preds={BB06} succs={BB06}
=====
N138. IL_OFFSET IL offset: 0x47 REG NA
N140. V02 MEM
Def:<I37>(#80)
N142. V04 MEM
Use:<I37>(#81) *
N144. IL_OFFSET IL offset: 0x49 REG NA
N146. V02 MEM
Def:<I38>(#82)
N148. V03 MEM
Def:<I39>(#83)
N150. IND
N152. HWIntrinsic
Use:<I39>(#84) *
Def:<I40>(#85)
N154. CAST
Use:<I40>(#86) *
Def:<I41>(#87)
N156. SUB
Use:<I38>(#88) *
Use:<I41>(#89) *
Def:<I42>(#90) Pref:<I38>
N158. V02 MEM
Use:<I42>(#91) *
N160. IL_OFFSET IL offset: 0x55 REG NA
N162. V03 MEM
N164. CNS_INT 8 REG NA
Def:<I43>(#92)
N166. CAST
Use:<I43>(#93) *
Def:<I44>(#94)
N168. ADD
Use:<I44>(#95) *
Def:<I45>(#96) Pref:<I44>
N170. V03 MEM
Use:<I45>(#97) *
BB07 [05D..086) (return), preds={BB06} succs={}
=====
N174. IL_OFFSET IL offset: 0x5d REG NA
N176. V03 MEM
Def:<I46>(#99)
N178. CNS_INT 8 REG NA
Def:<I47>(#100)
N180. CAST
Use:<I47>(#101) *
Def:<I48>(#102)
N182. SUB
Use:<I46>(#103) *
Use:<I48>(#104) *
Def:<I49>(#105) Pref:<I46>
N184. V03 MEM
Use:<I49>(#106) *
N186. IL_OFFSET IL offset: 0x61 REG NA
N188. V04 MEM
Def:<I50>(#107)
N190. CNS_INT -1 REG NA
N192. ADD
Use:<I50>(#108) *
Def:<I51>(#109) Pref:<I50>
N194. CNS_INT 1 REG NA
Def:<I52>(#110)
N196. CAST
Use:<I52>(#111) *
Def:<I53>(#112)
N198. LSH
Use:<I53>(#113) *
Use:<I51>(#115) Fixed:rcx(#114) *
Kill: rcx
Def:<I54>(#117) Pref:<I53>
N200. V03 MEM
Def:<I55>(#118)
N202. IND
N204. HWIntrinsic
Use:<I54>(#119) *
Use:<I55>(#120) *
Def:<I56>(#121)
N206. HWIntrinsic
Use:<I56>(#122) *
Def:<I57>(#123)
N208. CAST
Use:<I57>(#124) *
Def:<I58>(#125)
N210. V05 MEM
Use:<I58>(#126) *
N212. IL_OFFSET IL offset: 0x78 REG NA
N214. V03 MEM
Def:<I59>(#127)
N216. V00 MEM
N218. SUB
Use:<I59>(#128) *
Def:<I60>(#129) Pref:<I59>
N220. CNS_INT 8 REG NA
Def:<I61>(#130)
N222. CAST
Use:<I61>(#131) *
Def:<I62>(#132)
N224. DIV
Use:<I60>(#134) Fixed:rax(#133) *
Use:<I62>(#135) *
Kill: rax rdx
Def:<I63>(#139) rax Pref:<I60>
N226. CAST
Use:<I63>(#140) *
Def:<I64>(#141)
N228. CNS_INT 64 REG NA
N230. MUL
Use:<I64>(#142) *
Def:<I65>(#143)
N232. V05 MEM
N234. ADD
Use:<I65>(#144) *
Def:<I66>(#145) Pref:<I65>
N236. RETURN
Use:<I66>(#147) Fixed:rax(#146) *
Linear scan intervals after buildIntervals:
Interval 0: RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#5@25 #6@28} physReg:NA Preferences=[allInt]
Interval 2: (interfering uses) RefPositions {#7@29 #8@30} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#9@31 #19@46} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {#10@33 #14@42} physReg:NA Preferences=[allInt]
Interval 5: (constant) RefPositions {#11@35 #12@36} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {#13@37 #15@42} physReg:NA Preferences=[allInt]
Interval 7: (interfering uses) RefPositions {#16@43 #17@44} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {#18@45 #20@46} physReg:NA Preferences=[allInt]
Interval 9: RefPositions {#21@47 #37@68} physReg:NA Preferences=[allInt] RelatedInterval <I3>[0000000001408C18]
Interval 10: RefPositions {#22@49 #32@64} physReg:NA Preferences=[allInt]
Interval 11: (constant) RefPositions {#23@51 #24@52} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#25@53 #29@58} physReg:NA Preferences=[allInt]
Interval 13: (constant) RefPositions {#26@55 #27@56} physReg:NA Preferences=[allInt]
Interval 14: RefPositions {#28@57 #30@58} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#31@59 #33@64} physReg:NA Preferences=[allInt] RelatedInterval <I12>[00000000014095A8]
Interval 16: (interfering uses) RefPositions {#34@65 #35@66} physReg:NA Preferences=[allInt]
Interval 17: RefPositions {#36@67 #38@68} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#39@69 #55@90} physReg:NA Preferences=[allInt] RelatedInterval <I9>[00000000014092F8]
Interval 19: RefPositions {#40@71 #50@86} physReg:NA Preferences=[allInt]
Interval 20: (constant) RefPositions {#41@73 #42@74} physReg:NA Preferences=[allInt]
Interval 21: RefPositions {#43@75 #47@80} physReg:NA Preferences=[allInt]
Interval 22: (constant) RefPositions {#44@77 #45@78} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#46@79 #48@80} physReg:NA Preferences=[allInt]
Interval 24: RefPositions {#49@81 #51@86} physReg:NA Preferences=[allInt] RelatedInterval <I21>[0000000001409FB8]
Interval 25: (interfering uses) RefPositions {#52@87 #53@88} physReg:NA Preferences=[allInt]
Interval 26: RefPositions {#54@89 #56@90} physReg:NA Preferences=[allInt]
Interval 27: RefPositions {#57@91 #60@94} physReg:NA Preferences=[allInt] RelatedInterval <I18>[0000000001409D08]
Interval 28: RefPositions {#58@93 #59@94} physReg:NA Preferences=[allInt]
Interval 29: (interfering uses) RefPositions {#61@95 #62@96} physReg:NA Preferences=[allInt] RelatedInterval <I28>[000000000140A7E8]
Interval 30: (constant) RefPositions {#63@103 #64@104} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#65@105 #69@110} physReg:NA Preferences=[allInt]
Interval 32: (constant) RefPositions {#66@107 #67@108} physReg:NA Preferences=[allInt]
Interval 33: RefPositions {#68@109 #70@110} physReg:NA Preferences=[allInt]
Interval 34: RefPositions {#71@111 #72@112} physReg:NA Preferences=[allInt] RelatedInterval <I31>[000000000140AC18]
Interval 35: RefPositions {#73@113 #74@114} physReg:NA Preferences=[allInt] RelatedInterval <I34>[000000000140AF48]
Interval 36: RefPositions {#76@121 #77@122} physReg:NA Preferences=[allInt]
Interval 37: RefPositions {#80@141 #81@142} physReg:NA Preferences=[allInt]
Interval 38: RefPositions {#82@147 #88@156} physReg:NA Preferences=[allInt]
Interval 39: RefPositions {#83@149 #84@152} physReg:NA Preferences=[allInt]
Interval 40: (interfering uses) RefPositions {#85@153 #86@154} physReg:NA Preferences=[allInt]
Interval 41: RefPositions {#87@155 #89@156} physReg:NA Preferences=[allInt]
Interval 42: (interfering uses) RefPositions {#90@157 #91@158} physReg:NA Preferences=[allInt] RelatedInterval <I38>[000000000140B708]
Interval 43: (constant) RefPositions {#92@165 #93@166} physReg:NA Preferences=[allInt]
Interval 44: RefPositions {#94@167 #95@168} physReg:NA Preferences=[allInt]
Interval 45: RefPositions {#96@169 #97@170} physReg:NA Preferences=[allInt] RelatedInterval <I44>[000000000140BE68]
Interval 46: RefPositions {#99@177 #103@182} physReg:NA Preferences=[allInt]
Interval 47: (constant) RefPositions {#100@179 #101@180} physReg:NA Preferences=[allInt]
Interval 48: RefPositions {#102@181 #104@182} physReg:NA Preferences=[allInt]
Interval 49: (interfering uses) RefPositions {#105@183 #106@184} physReg:NA Preferences=[allInt] RelatedInterval <I46>[000000000140C148]
Interval 50: RefPositions {#107@189 #108@192} physReg:NA Preferences=[allInt]
Interval 51: RefPositions {#109@193 #115@198} physReg:NA Preferences=[rcx] RelatedInterval <I50>[000000000140C608]
Interval 52: (constant) RefPositions {#110@195 #111@196} physReg:NA Preferences=[allInt]
Interval 53: RefPositions {#112@197 #113@198} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 54: (interfering uses) RefPositions {#117@199 #119@204} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15] RelatedInterval <I53>[000000000140C938]
Interval 55: RefPositions {#118@201 #120@204} physReg:NA Preferences=[allInt]
Interval 56: RefPositions {#121@205 #122@206} physReg:NA Preferences=[allInt]
Interval 57: (interfering uses) RefPositions {#123@207 #124@208} physReg:NA Preferences=[allInt]
Interval 58: RefPositions {#125@209 #126@210} physReg:NA Preferences=[allInt]
Interval 59: RefPositions {#127@215 #128@218} physReg:NA Preferences=[allInt]
Interval 60: RefPositions {#129@219 #134@224} physReg:NA Preferences=[rax] RelatedInterval <I59>[000000000140D118]
Interval 61: (constant) RefPositions {#130@221 #131@222} physReg:NA Preferences=[allInt]
Interval 62: RefPositions {#132@223 #135@224} physReg:NA Preferences=[rcx rbx rsi rdi r8-r15]
Interval 63: (interfering uses) RefPositions {#139@225 #140@226} physReg:NA Preferences=[rax] RelatedInterval <I60>[000000000140D268]
Interval 64: RefPositions {#141@227 #142@230} physReg:NA Preferences=[allInt]
Interval 65: RefPositions {#143@231 #144@234} physReg:NA Preferences=[allInt]
Interval 66: RefPositions {#145@235 #147@236} physReg:NA Preferences=[rax] RelatedInterval <I65>[000000000140D8F8]
*************** In LinearScan::allocateRegisters()
Linear scan intervals before allocateRegisters:
Interval 0: RefPositions {#1@5 #2@6} physReg:NA Preferences=[allInt]
Interval 1: RefPositions {#5@25 #6@28} physReg:NA Preferences=[allInt]
Interval 2: (interfering uses) RefPositions {#7@29 #8@30} physReg:NA Preferences=[allInt]
Interval 3: RefPositions {#9@31 #19@46} physReg:NA Preferences=[allInt]
Interval 4: RefPositions {#10@33 #14@42} physReg:NA Preferences=[allInt]
Interval 5: (constant) RefPositions {#11@35 #12@36} physReg:NA Preferences=[allInt]
Interval 6: RefPositions {#13@37 #15@42} physReg:NA Preferences=[allInt]
Interval 7: (interfering uses) RefPositions {#16@43 #17@44} physReg:NA Preferences=[allInt]
Interval 8: RefPositions {#18@45 #20@46} physReg:NA Preferences=[allInt]
Interval 9: RefPositions {#21@47 #37@68} physReg:NA Preferences=[allInt] RelatedInterval <I3>[0000000001408C18]
Interval 10: RefPositions {#22@49 #32@64} physReg:NA Preferences=[allInt]
Interval 11: (constant) RefPositions {#23@51 #24@52} physReg:NA Preferences=[allInt]
Interval 12: RefPositions {#25@53 #29@58} physReg:NA Preferences=[allInt]
Interval 13: (constant) RefPositions {#26@55 #27@56} physReg:NA Preferences=[allInt]
Interval 14: RefPositions {#28@57 #30@58} physReg:NA Preferences=[allInt]
Interval 15: RefPositions {#31@59 #33@64} physReg:NA Preferences=[allInt] RelatedInterval <I12>[00000000014095A8]
Interval 16: (interfering uses) RefPositions {#34@65 #35@66} physReg:NA Preferences=[allInt]
Interval 17: RefPositions {#36@67 #38@68} physReg:NA Preferences=[allInt]
Interval 18: RefPositions {#39@69 #55@90} physReg:NA Preferences=[allInt] RelatedInterval <I9>[00000000014092F8]
Interval 19: RefPositions {#40@71 #50@86} physReg:NA Preferences=[allInt]
Interval 20: (constant) RefPositions {#41@73 #42@74} physReg:NA Preferences=[allInt]
Interval 21: RefPositions {#43@75 #47@80} physReg:NA Preferences=[allInt]
Interval 22: (constant) RefPositions {#44@77 #45@78} physReg:NA Preferences=[allInt]
Interval 23: RefPositions {#46@79 #48@80} physReg:NA Preferences=[allInt]
Interval 24: RefPositions {#49@81 #51@86} physReg:NA Preferences=[allInt] RelatedInterval <I21>[0000000001409FB8]
Interval 25: (interfering uses) RefPositions {#52@87 #53@88} physReg:NA Preferences=[allInt]
Interval 26: RefPositions {#54@89 #56@90} physReg:NA Preferences=[allInt]
Interval 27: RefPositions {#57@91 #60@94} physReg:NA Preferences=[allInt] RelatedInterval <I18>[0000000001409D08]
Interval 28: RefPositions {#58@93 #59@94} physReg:NA Preferences=[allInt]
Interval 29: (interfering uses) RefPositions {#61@95 #62@96} physReg:NA Preferences=[allInt] RelatedInterval <I28>[000000000140A7E8]
Interval 30: (constant) RefPositions {#63@103 #64@104} physReg:NA Preferences=[allInt]
Interval 31: RefPositions {#65@105 #69@110} physReg:NA Preferences=[allInt]
Interval 32: (constant) RefPositions {#66@107 #67@108} physReg:NA Preferences=[allInt]
Interval 33: RefPositions {#68@109 #70@110} physReg:NA Preferences=[allInt]
Interval 34: RefPositions {#71@111 #72@112} physReg:NA Preferences=[allInt] RelatedInterval <I31>[000000000140AC18]
Interval 35: RefPositions {#73@113 #74@114} physReg:NA Preferences=[allInt] RelatedInterval <I34>[000000000140AF48]
Interval 36: RefPositions {#76@121 #77@122} physReg:NA Preferences=[allInt]
Interval 37: RefPositions {#80@141 #81@142} physReg:NA Preferences=[allInt]
Interval 38: RefPositions {#82@147 #88@156} physReg:NA Preferences=[allInt]
Interval 39: RefPositions {#83@149 #84@152} physReg:NA Preferences=[allInt]
Interval 40: (interfering uses) RefPositions {#85@153 #86@154} physReg:NA Preferences=[allInt]
Interval 41: RefPositions {#87@155 #89@156} physReg:NA Preferences=[allInt]
Interval 42: (interfering uses) RefPositions {#90@157 #91@158} physReg:NA Preferences=[allInt] RelatedInterval <I38>[000000000140B708]
Interval 43: (constant) RefPositions {#92@165 #93@166} physReg:NA Preferences=[allInt]
Interval 44: RefPositions {#94@167 #95@168} physReg:NA Preferences=[allInt]
Interval 45: RefPositions {#96@169 #97@170} physReg:NA Preferences=[allInt] RelatedInterval <I44>[000000000140BE68]
Interval 46: RefPositions {#99@177 #103@182} physReg:NA Preferences=[allInt]
Interval 47: (constant) RefPositions {#100@179 #101@180} physReg:NA Preferences=[allInt]
Interval 48: RefPositions {#102@181 #104@182} physReg:NA Preferences=[allInt]
Interval 49: (interfering uses) RefPositions {#105@183 #106@184} physReg:NA Preferences=[allInt] RelatedInterval <I46>[000000000140C148]
Interval 50: RefPositions {#107@189 #108@192} physReg:NA Preferences=[allInt]
Interval 51: RefPositions {#109@193 #115@198} physReg:NA Preferences=[rcx] RelatedInterval <I50>[000000000140C608]
Interval 52: (constant) RefPositions {#110@195 #111@196} physReg:NA Preferences=[allInt]
Interval 53: RefPositions {#112@197 #113@198} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15]
Interval 54: (interfering uses) RefPositions {#117@199 #119@204} physReg:NA Preferences=[rax rdx rbx rsi rdi r8-r15] RelatedInterval <I53>[000000000140C938]
Interval 55: RefPositions {#118@201 #120@204} physReg:NA Preferences=[allInt]
Interval 56: RefPositions {#121@205 #122@206} physReg:NA Preferences=[allInt]
Interval 57: (interfering uses) RefPositions {#123@207 #124@208} physReg:NA Preferences=[allInt]
Interval 58: RefPositions {#125@209 #126@210} physReg:NA Preferences=[allInt]
Interval 59: RefPositions {#127@215 #128@218} physReg:NA Preferences=[allInt]
Interval 60: RefPositions {#129@219 #134@224} physReg:NA Preferences=[rax] RelatedInterval <I59>[000000000140D118]
Interval 61: (constant) RefPositions {#130@221 #131@222} physReg:NA Preferences=[allInt]
Interval 62: RefPositions {#132@223 #135@224} physReg:NA Preferences=[rcx rbx rsi rdi r8-r15]
Interval 63: (interfering uses) RefPositions {#139@225 #140@226} physReg:NA Preferences=[rax] RelatedInterval <I60>[000000000140D268]
Interval 64: RefPositions {#141@227 #142@230} physReg:NA Preferences=[allInt]
Interval 65: RefPositions {#143@231 #144@234} physReg:NA Preferences=[allInt]
Interval 66: RefPositions {#145@235 #147@236} physReg:NA Preferences=[rax] RelatedInterval <I65>[000000000140D8F8]
------------
REFPOSITIONS BEFORE ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> LCL_VAR BB01 regmask=[allInt] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[allInt] minReg=1 last>
<RefPosition #3 @8 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #4 @20 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #5 @25 RefTypeDef <Ivl:1> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #6 @28 RefTypeUse <Ivl:1> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #7 @29 RefTypeDef <Ivl:2> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #8 @30 RefTypeUse <Ivl:2> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #9 @31 RefTypeDef <Ivl:3> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #10 @33 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #11 @35 RefTypeDef <Ivl:5> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #12 @36 RefTypeUse <Ivl:5> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #13 @37 RefTypeDef <Ivl:6> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #14 @42 RefTypeUse <Ivl:4> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #15 @42 RefTypeUse <Ivl:6> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #16 @43 RefTypeDef <Ivl:7> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #17 @44 RefTypeUse <Ivl:7> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #18 @45 RefTypeDef <Ivl:8> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #19 @46 RefTypeUse <Ivl:3> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #20 @46 RefTypeUse <Ivl:8> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #21 @47 RefTypeDef <Ivl:9> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #22 @49 RefTypeDef <Ivl:10> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #23 @51 RefTypeDef <Ivl:11> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #24 @52 RefTypeUse <Ivl:11> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #25 @53 RefTypeDef <Ivl:12> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #26 @55 RefTypeDef <Ivl:13> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #27 @56 RefTypeUse <Ivl:13> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #28 @57 RefTypeDef <Ivl:14> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #29 @58 RefTypeUse <Ivl:12> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #30 @58 RefTypeUse <Ivl:14> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #31 @59 RefTypeDef <Ivl:15> MUL BB02 regmask=[allInt] minReg=1>
<RefPosition #32 @64 RefTypeUse <Ivl:10> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #33 @64 RefTypeUse <Ivl:15> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #34 @65 RefTypeDef <Ivl:16> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #35 @66 RefTypeUse <Ivl:16> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #36 @67 RefTypeDef <Ivl:17> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #37 @68 RefTypeUse <Ivl:9> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #38 @68 RefTypeUse <Ivl:17> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #39 @69 RefTypeDef <Ivl:18> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #40 @71 RefTypeDef <Ivl:19> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #41 @73 RefTypeDef <Ivl:20> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #42 @74 RefTypeUse <Ivl:20> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #43 @75 RefTypeDef <Ivl:21> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #44 @77 RefTypeDef <Ivl:22> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #45 @78 RefTypeUse <Ivl:22> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #46 @79 RefTypeDef <Ivl:23> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #47 @80 RefTypeUse <Ivl:21> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #48 @80 RefTypeUse <Ivl:23> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #49 @81 RefTypeDef <Ivl:24> MUL BB02 regmask=[allInt] minReg=1>
<RefPosition #50 @86 RefTypeUse <Ivl:19> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #51 @86 RefTypeUse <Ivl:24> BB02 regmask=[allInt] minReg=1 last delay>
<RefPosition #52 @87 RefTypeDef <Ivl:25> HWIntrinsic BB02 regmask=[allInt] minReg=1>
<RefPosition #53 @88 RefTypeUse <Ivl:25> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #54 @89 RefTypeDef <Ivl:26> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #55 @90 RefTypeUse <Ivl:18> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #56 @90 RefTypeUse <Ivl:26> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #57 @91 RefTypeDef <Ivl:27> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #58 @93 RefTypeDef <Ivl:28> LCL_VAR BB02 regmask=[allInt] minReg=1>
<RefPosition #59 @94 RefTypeUse <Ivl:28> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #60 @94 RefTypeUse <Ivl:27> BB02 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #61 @95 RefTypeDef <Ivl:29> SUB BB02 regmask=[allInt] minReg=1>
<RefPosition #62 @96 RefTypeUse <Ivl:29> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #63 @103 RefTypeDef <Ivl:30> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #64 @104 RefTypeUse <Ivl:30> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #65 @105 RefTypeDef <Ivl:31> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #66 @107 RefTypeDef <Ivl:32> CNS_INT BB02 regmask=[allInt] minReg=1>
<RefPosition #67 @108 RefTypeUse <Ivl:32> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #68 @109 RefTypeDef <Ivl:33> CAST BB02 regmask=[allInt] minReg=1>
<RefPosition #69 @110 RefTypeUse <Ivl:31> BB02 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #70 @110 RefTypeUse <Ivl:33> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #71 @111 RefTypeDef <Ivl:34> MUL BB02 regmask=[allInt] minReg=1>
<RefPosition #72 @112 RefTypeUse <Ivl:34> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #73 @113 RefTypeDef <Ivl:35> ADD BB02 regmask=[allInt] minReg=1>
<RefPosition #74 @114 RefTypeUse <Ivl:35> BB02 regmask=[allInt] minReg=1 last>
<RefPosition #75 @116 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #76 @121 RefTypeDef <Ivl:36> LCL_VAR BB04 regmask=[allInt] minReg=1>
<RefPosition #77 @122 RefTypeUse <Ivl:36> BB04 regmask=[allInt] minReg=1 last>
<RefPosition #78 @124 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #79 @136 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #80 @141 RefTypeDef <Ivl:37> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #81 @142 RefTypeUse <Ivl:37> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #82 @147 RefTypeDef <Ivl:38> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #83 @149 RefTypeDef <Ivl:39> LCL_VAR BB05 regmask=[allInt] minReg=1>
<RefPosition #84 @152 RefTypeUse <Ivl:39> BB05 regmask=[allInt] minReg=1 last delay>
<RefPosition #85 @153 RefTypeDef <Ivl:40> HWIntrinsic BB05 regmask=[allInt] minReg=1>
<RefPosition #86 @154 RefTypeUse <Ivl:40> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #87 @155 RefTypeDef <Ivl:41> CAST BB05 regmask=[allInt] minReg=1>
<RefPosition #88 @156 RefTypeUse <Ivl:38> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #89 @156 RefTypeUse <Ivl:41> BB05 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #90 @157 RefTypeDef <Ivl:42> SUB BB05 regmask=[allInt] minReg=1>
<RefPosition #91 @158 RefTypeUse <Ivl:42> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #92 @165 RefTypeDef <Ivl:43> CNS_INT BB05 regmask=[allInt] minReg=1>
<RefPosition #93 @166 RefTypeUse <Ivl:43> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #94 @167 RefTypeDef <Ivl:44> CAST BB05 regmask=[allInt] minReg=1>
<RefPosition #95 @168 RefTypeUse <Ivl:44> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #96 @169 RefTypeDef <Ivl:45> ADD BB05 regmask=[allInt] minReg=1>
<RefPosition #97 @170 RefTypeUse <Ivl:45> BB05 regmask=[allInt] minReg=1 last>
<RefPosition #98 @172 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #99 @177 RefTypeDef <Ivl:46> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #100 @179 RefTypeDef <Ivl:47> CNS_INT BB07 regmask=[allInt] minReg=1>
<RefPosition #101 @180 RefTypeUse <Ivl:47> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #102 @181 RefTypeDef <Ivl:48> CAST BB07 regmask=[allInt] minReg=1>
<RefPosition #103 @182 RefTypeUse <Ivl:46> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #104 @182 RefTypeUse <Ivl:48> BB07 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #105 @183 RefTypeDef <Ivl:49> SUB BB07 regmask=[allInt] minReg=1>
<RefPosition #106 @184 RefTypeUse <Ivl:49> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #107 @189 RefTypeDef <Ivl:50> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #108 @192 RefTypeUse <Ivl:50> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #109 @193 RefTypeDef <Ivl:51> ADD BB07 regmask=[rcx] minReg=1>
<RefPosition #110 @195 RefTypeDef <Ivl:52> CNS_INT BB07 regmask=[allInt] minReg=1>
<RefPosition #111 @196 RefTypeUse <Ivl:52> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #112 @197 RefTypeDef <Ivl:53> CAST BB07 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #113 @198 RefTypeUse <Ivl:53> BB07 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1 last>
<RefPosition #114 @198 RefTypeFixedReg <Reg:rcx> BB07 regmask=[rcx] minReg=1>
<RefPosition #115 @198 RefTypeUse <Ivl:51> BB07 regmask=[rcx] minReg=1 last fixed delay>
<RefPosition #116 @199 RefTypeKill <Reg:rcx> BB07 regmask=[rcx] minReg=1 last>
<RefPosition #117 @199 RefTypeDef <Ivl:54> LSH BB07 regmask=[rax rdx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #118 @201 RefTypeDef <Ivl:55> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #119 @204 RefTypeUse <Ivl:54> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #120 @204 RefTypeUse <Ivl:55> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #121 @205 RefTypeDef <Ivl:56> HWIntrinsic BB07 regmask=[allInt] minReg=1>
<RefPosition #122 @206 RefTypeUse <Ivl:56> BB07 regmask=[allInt] minReg=1 last delay regOptional>
<RefPosition #123 @207 RefTypeDef <Ivl:57> HWIntrinsic BB07 regmask=[allInt] minReg=1>
<RefPosition #124 @208 RefTypeUse <Ivl:57> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #125 @209 RefTypeDef <Ivl:58> CAST BB07 regmask=[allInt] minReg=1>
<RefPosition #126 @210 RefTypeUse <Ivl:58> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #127 @215 RefTypeDef <Ivl:59> LCL_VAR BB07 regmask=[allInt] minReg=1>
<RefPosition #128 @218 RefTypeUse <Ivl:59> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #129 @219 RefTypeDef <Ivl:60> SUB BB07 regmask=[rax] minReg=1>
<RefPosition #130 @221 RefTypeDef <Ivl:61> CNS_INT BB07 regmask=[allInt] minReg=1>
<RefPosition #131 @222 RefTypeUse <Ivl:61> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #132 @223 RefTypeDef <Ivl:62> CAST BB07 regmask=[rcx rbx rsi rdi r8-r15] minReg=1>
<RefPosition #133 @224 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #134 @224 RefTypeUse <Ivl:60> BB07 regmask=[rax] minReg=1 last fixed>
<RefPosition #135 @224 RefTypeUse <Ivl:62> BB07 regmask=[rcx rbx rsi rdi r8-r15] minReg=1 last delay regOptional>
<RefPosition #136 @225 RefTypeKill <Reg:rax> BB07 regmask=[rax] minReg=1 last>
<RefPosition #137 @225 RefTypeKill <Reg:rdx> BB07 regmask=[rdx] minReg=1 last>
<RefPosition #138 @225 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #139 @225 RefTypeDef <Ivl:63> DIV BB07 regmask=[rax] minReg=1 fixed>
<RefPosition #140 @226 RefTypeUse <Ivl:63> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #141 @227 RefTypeDef <Ivl:64> CAST BB07 regmask=[allInt] minReg=1>
<RefPosition #142 @230 RefTypeUse <Ivl:64> BB07 regmask=[allInt] minReg=1 last regOptional>
<RefPosition #143 @231 RefTypeDef <Ivl:65> MUL BB07 regmask=[allInt] minReg=1>
<RefPosition #144 @234 RefTypeUse <Ivl:65> BB07 regmask=[allInt] minReg=1 last>
<RefPosition #145 @235 RefTypeDef <Ivl:66> ADD BB07 regmask=[rax] minReg=1>
<RefPosition #146 @236 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #147 @236 RefTypeUse <Ivl:66> BB07 regmask=[rax] minReg=1 last fixed>
Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The first column provides the basic information about the RefPosition, with its type (e.g. Def,
Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the
action taken during allocation (e.g. Alloc a new register, or Keep an existing one).
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which
may increase during allocation, in which case additional columns will appear. Registers which are
not marked modified have ---- in their column.
--------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |r12 |r13 |
--------------------------------+----+----+----+----+----+
| | | | | |
0.#0 BB1 PredBB0 | | | | | |
5.#1 I0 Def Alloc rcx | |I0 a| | | |
6.#2 I0 Use * Keep rcx | |I0 a| | | |
--------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |r12 |r13 |
--------------------------------+----+----+----+----+----+
8.#3 BB3 PredBB1 | | | | | |
--------------------------------+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rbx |r12 |r13 |
--------------------------------+----+----+----+----+----+
20.#4 BB2 PredBB3 | | | | | |
25.#5 I1 Def Alloc rcx | |I1 a| | | |
28.#6 I1 Use *D Keep rcx | |I1 a| | | |
29.#7 I2 Def Alloc rax |I2 a|I1 a| | | |
30.#8 I2 Use * Keep rax |I2 a| | | | |
31.#9 I3 Def Alloc rcx | |I3 a| | | |
33.#10 I4 Def Alloc rax |I4 a|I3 a| | | |
--------------------------------+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |r12 |r13 |
--------------------------------+----+----+----+----+----+----+
35.#11 C5 Def Alloc rdx |I4 a|I3 a|C5 a| | | |
36.#12 C5 Use * Keep rdx |I4 a|I3 a|C5 a| | | |
37.#13 I6 Def Alloc rdx |I4 a|I3 a|I6 a| | | |
42.#14 I4 Use *D Keep rax |I4 a|I3 a|I6 a| | | |
42.#15 I6 Use *D Keep rdx |I4 a|I3 a|I6 a| | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
43.#16 I7 Def Alloc rdi |I4 a|I3 a|I6 a| |I7 a| | |
44.#17 I7 Use * Keep rdi | |I3 a| | |I7 a| | |
45.#18 I8 Def Alloc rax |I8 a|I3 a| | | | | |
46.#19 I3 Use * Keep rcx |I8 a|I3 a| | | | | |
46.#20 I8 Use * Keep rax |I8 a|I3 a| | | | | |
47.#21 I9 Def Alloc rcx | |I9 a| | | | | |
49.#22 I10 Def Alloc rax |I10a|I9 a| | | | | |
51.#23 C11 Def Alloc rdx |I10a|I9 a|C11a| | | | |
52.#24 C11 Use * Keep rdx |I10a|I9 a|C11a| | | | |
53.#25 I12 Def Alloc rdx |I10a|I9 a|I12a| | | | |
55.#26 C13 Def Alloc rdi |I10a|I9 a|I12a| |C13a| | |
56.#27 C13 Use * Keep rdi |I10a|I9 a|I12a| |C13a| | |
57.#28 I14 Def Alloc rdi |I10a|I9 a|I12a| |I14a| | |
58.#29 I12 Use * Keep rdx |I10a|I9 a|I12a| |I14a| | |
58.#30 I14 Use * Keep rdi |I10a|I9 a|I12a| |I14a| | |
59.#31 I15 Def Alloc rdx |I10a|I9 a|I15a| | | | |
64.#32 I10 Use *D Keep rax |I10a|I9 a|I15a| | | | |
64.#33 I15 Use *D Keep rdx |I10a|I9 a|I15a| | | | |
65.#34 I16 Def Alloc rdi |I10a|I9 a|I15a| |I16a| | |
66.#35 I16 Use * Keep rdi | |I9 a| | |I16a| | |
67.#36 I17 Def Alloc rax |I17a|I9 a| | | | | |
68.#37 I9 Use * Keep rcx |I17a|I9 a| | | | | |
68.#38 I17 Use * Keep rax |I17a|I9 a| | | | | |
69.#39 I18 Def Alloc rcx | |I18a| | | | | |
71.#40 I19 Def Alloc rax |I19a|I18a| | | | | |
73.#41 C20 Def Alloc rdx |I19a|I18a|C20a| | | | |
74.#42 C20 Use * Keep rdx |I19a|I18a|C20a| | | | |
75.#43 I21 Def Alloc rdx |I19a|I18a|I21a| | | | |
77.#44 C22 Def Alloc rdi |I19a|I18a|I21a| |C22a| | |
78.#45 C22 Use * Keep rdi |I19a|I18a|I21a| |C22a| | |
79.#46 I23 Def Alloc rdi |I19a|I18a|I21a| |I23a| | |
80.#47 I21 Use * Keep rdx |I19a|I18a|I21a| |I23a| | |
80.#48 I23 Use * Keep rdi |I19a|I18a|I21a| |I23a| | |
81.#49 I24 Def Alloc rdx |I19a|I18a|I24a| | | | |
86.#50 I19 Use *D Keep rax |I19a|I18a|I24a| | | | |
86.#51 I24 Use *D Keep rdx |I19a|I18a|I24a| | | | |
87.#52 I25 Def Alloc rdi |I19a|I18a|I24a| |I25a| | |
88.#53 I25 Use * Keep rdi | |I18a| | |I25a| | |
89.#54 I26 Def Alloc rax |I26a|I18a| | | | | |
90.#55 I18 Use * Keep rcx |I26a|I18a| | | | | |
90.#56 I26 Use * Keep rax |I26a|I18a| | | | | |
91.#57 I27 Def Alloc rcx | |I27a| | | | | |
93.#58 I28 Def Alloc rax |I28a|I27a| | | | | |
94.#59 I28 Use * Keep rax |I28a|I27a| | | | | |
94.#60 I27 Use *D Keep rcx |I28a|I27a| | | | | |
95.#61 I29 Def Alloc rax |I29a|I27a| | | | | |
96.#62 I29 Use * Keep rax |I29a| | | | | | |
103.#63 C30 Def Alloc rcx | |C30a| | | | | |
104.#64 C30 Use * Keep rcx | |C30a| | | | | |
105.#65 I31 Def Alloc rcx | |I31a| | | | | |
107.#66 C32 Def Alloc rax |C32a|I31a| | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
108.#67 C32 Use * Keep rax |C32a|I31a| | | | | |
109.#68 I33 Def Alloc rax |I33a|I31a| | | | | |
110.#69 I31 Use * Keep rcx |I33a|I31a| | | | | |
110.#70 I33 Use * Keep rax |I33a|I31a| | | | | |
111.#71 I34 Def Alloc rcx | |I34a| | | | | |
112.#72 I34 Use * Keep rcx | |I34a| | | | | |
113.#73 I35 Def Alloc rcx | |I35a| | | | | |
114.#74 I35 Use * Keep rcx | |I35a| | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
116.#75 BB4 PredBB3 | | | | | | | |
121.#76 I36 Def Alloc rcx | |I36a| | | | | |
122.#77 I36 Use * Keep rcx | |I36a| | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
124.#78 BB6 PredBB4 | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
136.#79 BB5 PredBB6 | | | | | | | |
141.#80 I37 Def Alloc rcx | |I37a| | | | | |
142.#81 I37 Use * Keep rcx | |I37a| | | | | |
147.#82 I38 Def Alloc rcx | |I38a| | | | | |
149.#83 I39 Def Alloc rax |I39a|I38a| | | | | |
152.#84 I39 Use *D Keep rax |I39a|I38a| | | | | |
153.#85 I40 Def Alloc rdx |I39a|I38a|I40a| | | | |
154.#86 I40 Use * Keep rdx | |I38a|I40a| | | | |
155.#87 I41 Def Alloc rax |I41a|I38a| | | | | |
156.#88 I38 Use * Keep rcx |I41a|I38a| | | | | |
156.#89 I41 Use *D Keep rax |I41a|I38a| | | | | |
157.#90 I42 Def Alloc rcx |I41a|I42a| | | | | |
158.#91 I42 Use * Keep rcx | |I42a| | | | | |
165.#92 C43 Def Alloc rcx | |C43a| | | | | |
166.#93 C43 Use * Keep rcx | |C43a| | | | | |
167.#94 I44 Def Alloc rcx | |I44a| | | | | |
168.#95 I44 Use * Keep rcx | |I44a| | | | | |
169.#96 I45 Def Alloc rcx | |I45a| | | | | |
170.#97 I45 Use * Keep rcx | |I45a| | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
172.#98 BB7 PredBB6 | | | | | | | |
177.#99 I46 Def Alloc rcx | |I46a| | | | | |
179.#100 C47 Def Alloc rax |C47a|I46a| | | | | |
180.#101 C47 Use * Keep rax |C47a|I46a| | | | | |
181.#102 I48 Def Alloc rax |I48a|I46a| | | | | |
182.#103 I46 Use * Keep rcx |I48a|I46a| | | | | |
182.#104 I48 Use *D Keep rax |I48a|I46a| | | | | |
183.#105 I49 Def Alloc rcx |I48a|I49a| | | | | |
184.#106 I49 Use * Keep rcx | |I49a| | | | | |
189.#107 I50 Def Alloc rcx | |I50a| | | | | |
192.#108 I50 Use * Keep rcx | |I50a| | | | | |
193.#109 I51 Def Alloc rcx | |I51a| | | | | |
195.#110 C52 Def Alloc rax |C52a|I51a| | | | | |
196.#111 C52 Use * Keep rax |C52a|I51a| | | | | |
197.#112 I53 Def Alloc rax |I53a|I51a| | | | | |
198.#113 I53 Use * Keep rax |I53a|I51a| | | | | |
198.#114 rcx Fixd Keep rcx |I53a|I51a| | | | | |
198.#115 I51 Use *D Keep rcx |I53a|I51a| | | | | |
199.#116 rcx Kill Keep rcx | | | | | | | |
199.#117 I54 Def Alloc rax |I54a| | | | | | |
201.#118 I55 Def Alloc rdx |I54a| |I55a| | | | |
204.#119 I54 Use * Keep rax |I54a| |I55a| | | | |
204.#120 I55 Use * Keep rdx |I54a| |I55a| | | | |
205.#121 I56 Def Alloc rax |I56a| | | | | | |
206.#122 I56 Use *D Keep rax |I56a| | | | | | |
207.#123 I57 Def Alloc rdx |I56a| |I57a| | | | |
208.#124 I57 Use * Keep rdx | | |I57a| | | | |
209.#125 I58 Def Alloc rax |I58a| | | | | | |
210.#126 I58 Use * Keep rax |I58a| | | | | | |
215.#127 I59 Def Alloc rax |I59a| | | | | | |
218.#128 I59 Use * Keep rax |I59a| | | | | | |
219.#129 I60 Def Alloc rax |I60a| | | | | | |
221.#130 C61 Def Alloc rdx |I60a| |C61a| | | | |
222.#131 C61 Use * Keep rdx |I60a| |C61a| | | | |
223.#132 I62 Def Alloc rdi |I60a| |C61i| |I62a| | |
224.#133 rax Fixd Keep rax |I60a| |C61i| |I62a| | |
224.#134 I60 Use * Keep rax |I60a| |C61i| |I62a| | |
224.#135 I62 Use *D Keep rdi |I60a| |C61i| |I62a| | |
225.#136 rax Kill Keep rax | | |C61i| |I62a| | |
225.#137 rdx Kill Keep rdx | | | | |I62a| | |
225.#138 rax Fixd Keep rax | | | | |I62a| | |
225.#139 I63 Def Alloc rax |I63a| | | |I62a| | |
226.#140 I63 Use * Keep rax |I63a| | | | | | |
227.#141 I64 Def Alloc rax |I64a| | | | | | |
230.#142 I64 Use * Keep rax |I64a| | | | | | |
231.#143 I65 Def Alloc rax |I65a| | | | | | |
234.#144 I65 Use * Keep rax |I65a| | | | | | |
235.#145 I66 Def Alloc rax |I66a| | | | | | |
236.#146 rax Fixd Keep rax |I66a| | | | | | |
236.#147 I66 Use * Keep rax | | | | | | | |
------------
REFPOSITIONS AFTER ALLOCATION:
------------
<RefPosition #0 @0 RefTypeBB BB01 regmask=[] minReg=1>
<RefPosition #1 @5 RefTypeDef <Ivl:0> LCL_VAR BB01 regmask=[rcx] minReg=1>
<RefPosition #2 @6 RefTypeUse <Ivl:0> BB01 regmask=[rcx] minReg=1 last>
<RefPosition #3 @8 RefTypeBB BB03 regmask=[] minReg=1>
<RefPosition #4 @20 RefTypeBB BB02 regmask=[] minReg=1>
<RefPosition #5 @25 RefTypeDef <Ivl:1> LCL_VAR BB02 regmask=[rcx] minReg=1>
<RefPosition #6 @28 RefTypeUse <Ivl:1> BB02 regmask=[rcx] minReg=1 last delay>
<RefPosition #7 @29 RefTypeDef <Ivl:2> HWIntrinsic BB02 regmask=[rax] minReg=1>
<RefPosition #8 @30 RefTypeUse <Ivl:2> BB02 regmask=[rax] minReg=1 last>
<RefPosition #9 @31 RefTypeDef <Ivl:3> CAST BB02 regmask=[rcx] minReg=1>
<RefPosition #10 @33 RefTypeDef <Ivl:4> LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #11 @35 RefTypeDef <Ivl:5> CNS_INT BB02 regmask=[rdx] minReg=1>
<RefPosition #12 @36 RefTypeUse <Ivl:5> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #13 @37 RefTypeDef <Ivl:6> CAST BB02 regmask=[rdx] minReg=1>
<RefPosition #14 @42 RefTypeUse <Ivl:4> BB02 regmask=[rax] minReg=1 last delay>
<RefPosition #15 @42 RefTypeUse <Ivl:6> BB02 regmask=[rdx] minReg=1 last delay>
<RefPosition #16 @43 RefTypeDef <Ivl:7> HWIntrinsic BB02 regmask=[rdi] minReg=1>
<RefPosition #17 @44 RefTypeUse <Ivl:7> BB02 regmask=[rdi] minReg=1 last>
<RefPosition #18 @45 RefTypeDef <Ivl:8> CAST BB02 regmask=[rax] minReg=1>
<RefPosition #19 @46 RefTypeUse <Ivl:3> BB02 regmask=[rcx] minReg=1 last regOptional>
<RefPosition #20 @46 RefTypeUse <Ivl:8> BB02 regmask=[rax] minReg=1 last>
<RefPosition #21 @47 RefTypeDef <Ivl:9> ADD BB02 regmask=[rcx] minReg=1>
<RefPosition #22 @49 RefTypeDef <Ivl:10> LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #23 @51 RefTypeDef <Ivl:11> CNS_INT BB02 regmask=[rdx] minReg=1>
<RefPosition #24 @52 RefTypeUse <Ivl:11> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #25 @53 RefTypeDef <Ivl:12> CAST BB02 regmask=[rdx] minReg=1>
<RefPosition #26 @55 RefTypeDef <Ivl:13> CNS_INT BB02 regmask=[rdi] minReg=1>
<RefPosition #27 @56 RefTypeUse <Ivl:13> BB02 regmask=[rdi] minReg=1 last>
<RefPosition #28 @57 RefTypeDef <Ivl:14> CAST BB02 regmask=[rdi] minReg=1>
<RefPosition #29 @58 RefTypeUse <Ivl:12> BB02 regmask=[rdx] minReg=1 last regOptional>
<RefPosition #30 @58 RefTypeUse <Ivl:14> BB02 regmask=[rdi] minReg=1 last>
<RefPosition #31 @59 RefTypeDef <Ivl:15> MUL BB02 regmask=[rdx] minReg=1>
<RefPosition #32 @64 RefTypeUse <Ivl:10> BB02 regmask=[rax] minReg=1 last delay>
<RefPosition #33 @64 RefTypeUse <Ivl:15> BB02 regmask=[rdx] minReg=1 last delay>
<RefPosition #34 @65 RefTypeDef <Ivl:16> HWIntrinsic BB02 regmask=[rdi] minReg=1>
<RefPosition #35 @66 RefTypeUse <Ivl:16> BB02 regmask=[rdi] minReg=1 last>
<RefPosition #36 @67 RefTypeDef <Ivl:17> CAST BB02 regmask=[rax] minReg=1>
<RefPosition #37 @68 RefTypeUse <Ivl:9> BB02 regmask=[rcx] minReg=1 last regOptional>
<RefPosition #38 @68 RefTypeUse <Ivl:17> BB02 regmask=[rax] minReg=1 last>
<RefPosition #39 @69 RefTypeDef <Ivl:18> ADD BB02 regmask=[rcx] minReg=1>
<RefPosition #40 @71 RefTypeDef <Ivl:19> LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #41 @73 RefTypeDef <Ivl:20> CNS_INT BB02 regmask=[rdx] minReg=1>
<RefPosition #42 @74 RefTypeUse <Ivl:20> BB02 regmask=[rdx] minReg=1 last>
<RefPosition #43 @75 RefTypeDef <Ivl:21> CAST BB02 regmask=[rdx] minReg=1>
<RefPosition #44 @77 RefTypeDef <Ivl:22> CNS_INT BB02 regmask=[rdi] minReg=1>
<RefPosition #45 @78 RefTypeUse <Ivl:22> BB02 regmask=[rdi] minReg=1 last>
<RefPosition #46 @79 RefTypeDef <Ivl:23> CAST BB02 regmask=[rdi] minReg=1>
<RefPosition #47 @80 RefTypeUse <Ivl:21> BB02 regmask=[rdx] minReg=1 last regOptional>
<RefPosition #48 @80 RefTypeUse <Ivl:23> BB02 regmask=[rdi] minReg=1 last>
<RefPosition #49 @81 RefTypeDef <Ivl:24> MUL BB02 regmask=[rdx] minReg=1>
<RefPosition #50 @86 RefTypeUse <Ivl:19> BB02 regmask=[rax] minReg=1 last delay>
<RefPosition #51 @86 RefTypeUse <Ivl:24> BB02 regmask=[rdx] minReg=1 last delay>
<RefPosition #52 @87 RefTypeDef <Ivl:25> HWIntrinsic BB02 regmask=[rdi] minReg=1>
<RefPosition #53 @88 RefTypeUse <Ivl:25> BB02 regmask=[rdi] minReg=1 last>
<RefPosition #54 @89 RefTypeDef <Ivl:26> CAST BB02 regmask=[rax] minReg=1>
<RefPosition #55 @90 RefTypeUse <Ivl:18> BB02 regmask=[rcx] minReg=1 last regOptional>
<RefPosition #56 @90 RefTypeUse <Ivl:26> BB02 regmask=[rax] minReg=1 last>
<RefPosition #57 @91 RefTypeDef <Ivl:27> ADD BB02 regmask=[rcx] minReg=1>
<RefPosition #58 @93 RefTypeDef <Ivl:28> LCL_VAR BB02 regmask=[rax] minReg=1>
<RefPosition #59 @94 RefTypeUse <Ivl:28> BB02 regmask=[rax] minReg=1 last>
<RefPosition #60 @94 RefTypeUse <Ivl:27> BB02 regmask=[rcx] minReg=1 last delay regOptional>
<RefPosition #61 @95 RefTypeDef <Ivl:29> SUB BB02 regmask=[rax] minReg=1>
<RefPosition #62 @96 RefTypeUse <Ivl:29> BB02 regmask=[rax] minReg=1 last>
<RefPosition #63 @103 RefTypeDef <Ivl:30> CNS_INT BB02 regmask=[rcx] minReg=1>
<RefPosition #64 @104 RefTypeUse <Ivl:30> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #65 @105 RefTypeDef <Ivl:31> CAST BB02 regmask=[rcx] minReg=1>
<RefPosition #66 @107 RefTypeDef <Ivl:32> CNS_INT BB02 regmask=[rax] minReg=1>
<RefPosition #67 @108 RefTypeUse <Ivl:32> BB02 regmask=[rax] minReg=1 last>
<RefPosition #68 @109 RefTypeDef <Ivl:33> CAST BB02 regmask=[rax] minReg=1>
<RefPosition #69 @110 RefTypeUse <Ivl:31> BB02 regmask=[rcx] minReg=1 last regOptional>
<RefPosition #70 @110 RefTypeUse <Ivl:33> BB02 regmask=[rax] minReg=1 last>
<RefPosition #71 @111 RefTypeDef <Ivl:34> MUL BB02 regmask=[rcx] minReg=1>
<RefPosition #72 @112 RefTypeUse <Ivl:34> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #73 @113 RefTypeDef <Ivl:35> ADD BB02 regmask=[rcx] minReg=1>
<RefPosition #74 @114 RefTypeUse <Ivl:35> BB02 regmask=[rcx] minReg=1 last>
<RefPosition #75 @116 RefTypeBB BB04 regmask=[] minReg=1>
<RefPosition #76 @121 RefTypeDef <Ivl:36> LCL_VAR BB04 regmask=[rcx] minReg=1>
<RefPosition #77 @122 RefTypeUse <Ivl:36> BB04 regmask=[rcx] minReg=1 last>
<RefPosition #78 @124 RefTypeBB BB06 regmask=[] minReg=1>
<RefPosition #79 @136 RefTypeBB BB05 regmask=[] minReg=1>
<RefPosition #80 @141 RefTypeDef <Ivl:37> LCL_VAR BB05 regmask=[rcx] minReg=1>
<RefPosition #81 @142 RefTypeUse <Ivl:37> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #82 @147 RefTypeDef <Ivl:38> LCL_VAR BB05 regmask=[rcx] minReg=1>
<RefPosition #83 @149 RefTypeDef <Ivl:39> LCL_VAR BB05 regmask=[rax] minReg=1>
<RefPosition #84 @152 RefTypeUse <Ivl:39> BB05 regmask=[rax] minReg=1 last delay>
<RefPosition #85 @153 RefTypeDef <Ivl:40> HWIntrinsic BB05 regmask=[rdx] minReg=1>
<RefPosition #86 @154 RefTypeUse <Ivl:40> BB05 regmask=[rdx] minReg=1 last>
<RefPosition #87 @155 RefTypeDef <Ivl:41> CAST BB05 regmask=[rax] minReg=1>
<RefPosition #88 @156 RefTypeUse <Ivl:38> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #89 @156 RefTypeUse <Ivl:41> BB05 regmask=[rax] minReg=1 last delay regOptional>
<RefPosition #90 @157 RefTypeDef <Ivl:42> SUB BB05 regmask=[rcx] minReg=1>
<RefPosition #91 @158 RefTypeUse <Ivl:42> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #92 @165 RefTypeDef <Ivl:43> CNS_INT BB05 regmask=[rcx] minReg=1>
<RefPosition #93 @166 RefTypeUse <Ivl:43> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #94 @167 RefTypeDef <Ivl:44> CAST BB05 regmask=[rcx] minReg=1>
<RefPosition #95 @168 RefTypeUse <Ivl:44> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #96 @169 RefTypeDef <Ivl:45> ADD BB05 regmask=[rcx] minReg=1>
<RefPosition #97 @170 RefTypeUse <Ivl:45> BB05 regmask=[rcx] minReg=1 last>
<RefPosition #98 @172 RefTypeBB BB07 regmask=[] minReg=1>
<RefPosition #99 @177 RefTypeDef <Ivl:46> LCL_VAR BB07 regmask=[rcx] minReg=1>
<RefPosition #100 @179 RefTypeDef <Ivl:47> CNS_INT BB07 regmask=[rax] minReg=1>
<RefPosition #101 @180 RefTypeUse <Ivl:47> BB07 regmask=[rax] minReg=1 last>
<RefPosition #102 @181 RefTypeDef <Ivl:48> CAST BB07 regmask=[rax] minReg=1>
<RefPosition #103 @182 RefTypeUse <Ivl:46> BB07 regmask=[rcx] minReg=1 last>
<RefPosition #104 @182 RefTypeUse <Ivl:48> BB07 regmask=[rax] minReg=1 last delay regOptional>
<RefPosition #105 @183 RefTypeDef <Ivl:49> SUB BB07 regmask=[rcx] minReg=1>
<RefPosition #106 @184 RefTypeUse <Ivl:49> BB07 regmask=[rcx] minReg=1 last>
<RefPosition #107 @189 RefTypeDef <Ivl:50> LCL_VAR BB07 regmask=[rcx] minReg=1>
<RefPosition #108 @192 RefTypeUse <Ivl:50> BB07 regmask=[rcx] minReg=1 last>
<RefPosition #109 @193 RefTypeDef <Ivl:51> ADD BB07 regmask=[rcx] minReg=1>
<RefPosition #110 @195 RefTypeDef <Ivl:52> CNS_INT BB07 regmask=[rax] minReg=1>
<RefPosition #111 @196 RefTypeUse <Ivl:52> BB07 regmask=[rax] minReg=1 last>
<RefPosition #112 @197 RefTypeDef <Ivl:53> CAST BB07 regmask=[rax] minReg=1>
<RefPosition #113 @198 RefTypeUse <Ivl:53> BB07 regmask=[rax] minReg=1 last>
<RefPosition #114 @198 RefTypeFixedReg <Reg:rcx> BB07 regmask=[rcx] minReg=1>
<RefPosition #115 @198 RefTypeUse <Ivl:51> BB07 regmask=[rcx] minReg=1 last fixed delay>
<RefPosition #116 @199 RefTypeKill <Reg:rcx> BB07 regmask=[rcx] minReg=1 last>
<RefPosition #117 @199 RefTypeDef <Ivl:54> LSH BB07 regmask=[rax] minReg=1>
<RefPosition #118 @201 RefTypeDef <Ivl:55> LCL_VAR BB07 regmask=[rdx] minReg=1>
<RefPosition #119 @204 RefTypeUse <Ivl:54> BB07 regmask=[rax] minReg=1 last>
<RefPosition #120 @204 RefTypeUse <Ivl:55> BB07 regmask=[rdx] minReg=1 last>
<RefPosition #121 @205 RefTypeDef <Ivl:56> HWIntrinsic BB07 regmask=[rax] minReg=1>
<RefPosition #122 @206 RefTypeUse <Ivl:56> BB07 regmask=[rax] minReg=1 last delay regOptional>
<RefPosition #123 @207 RefTypeDef <Ivl:57> HWIntrinsic BB07 regmask=[rdx] minReg=1>
<RefPosition #124 @208 RefTypeUse <Ivl:57> BB07 regmask=[rdx] minReg=1 last>
<RefPosition #125 @209 RefTypeDef <Ivl:58> CAST BB07 regmask=[rax] minReg=1>
<RefPosition #126 @210 RefTypeUse <Ivl:58> BB07 regmask=[rax] minReg=1 last>
<RefPosition #127 @215 RefTypeDef <Ivl:59> LCL_VAR BB07 regmask=[rax] minReg=1>
<RefPosition #128 @218 RefTypeUse <Ivl:59> BB07 regmask=[rax] minReg=1 last>
<RefPosition #129 @219 RefTypeDef <Ivl:60> SUB BB07 regmask=[rax] minReg=1>
<RefPosition #130 @221 RefTypeDef <Ivl:61> CNS_INT BB07 regmask=[rdx] minReg=1>
<RefPosition #131 @222 RefTypeUse <Ivl:61> BB07 regmask=[rdx] minReg=1 last>
<RefPosition #132 @223 RefTypeDef <Ivl:62> CAST BB07 regmask=[rdi] minReg=1>
<RefPosition #133 @224 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #134 @224 RefTypeUse <Ivl:60> BB07 regmask=[rax] minReg=1 last fixed>
<RefPosition #135 @224 RefTypeUse <Ivl:62> BB07 regmask=[rdi] minReg=1 last delay regOptional>
<RefPosition #136 @225 RefTypeKill <Reg:rax> BB07 regmask=[rax] minReg=1 last>
<RefPosition #137 @225 RefTypeKill <Reg:rdx> BB07 regmask=[rdx] minReg=1 last>
<RefPosition #138 @225 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #139 @225 RefTypeDef <Ivl:63> DIV BB07 regmask=[rax] minReg=1 fixed>
<RefPosition #140 @226 RefTypeUse <Ivl:63> BB07 regmask=[rax] minReg=1 last>
<RefPosition #141 @227 RefTypeDef <Ivl:64> CAST BB07 regmask=[rax] minReg=1>
<RefPosition #142 @230 RefTypeUse <Ivl:64> BB07 regmask=[rax] minReg=1 last regOptional>
<RefPosition #143 @231 RefTypeDef <Ivl:65> MUL BB07 regmask=[rax] minReg=1>
<RefPosition #144 @234 RefTypeUse <Ivl:65> BB07 regmask=[rax] minReg=1 last>
<RefPosition #145 @235 RefTypeDef <Ivl:66> ADD BB07 regmask=[rax] minReg=1>
<RefPosition #146 @236 RefTypeFixedReg <Reg:rax> BB07 regmask=[rax] minReg=1>
<RefPosition #147 @236 RefTypeUse <Ivl:66> BB07 regmask=[rax] minReg=1 last fixed>
Active intervals at end of allocation:
Active Interval 51: RefPositions {#109@193 #115@198} physReg:NA Preferences=[rcx] RelatedInterval <I50>[000000000140C608]
Trees after linear scan register allocator (LSRA)
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
------------ BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
N002 ( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0 REG NA
N004 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0 rcx REG rcx
/--* t1 long
N006 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
------------ BB02 [004..03B), preds={BB03} succs={BB03}
N022 ( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4 REG NA
N024 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0 rcx REG rcx
/--* t13 long
N026 ( 6, 4) [000014] *c-XG------- t14 = * IND long REG NA
/--* t14 long
N028 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount REG rax
/--* t15 long
N030 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long REG rcx
N032 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0 rax REG rax
N034 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8 REG rdx
/--* t17 int
N036 ( 2, 3) [000018] ------------ t18 = * CAST long <- int REG rdx
/--* t16 long
+--* t18 long
N038 (???,???) [000136] -c---------- t136 = * LEA(b+(i*1)+0) long REG NA
/--* t136 long
N040 ( 8, 7) [000020] *c-XG------- t20 = * IND long REG NA
/--* t20 long
N042 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount REG rdi
/--* t21 long
N044 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long REG rax
/--* t132 int
+--* t133 int
N046 ( 19, 18) [000022] ---XG------- t22 = * ADD int REG rcx
N048 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0 rax REG rax
N050 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2 REG rdx
/--* t24 int
N052 ( 2, 3) [000025] ------------ t25 = * CAST long <- int REG rdx
N054 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8 REG rdi
/--* t26 int
N056 ( 2, 3) [000027] ------------ t27 = * CAST long <- int REG rdi
/--* t25 long
+--* t27 long
N058 ( 8, 9) [000028] ------------ t28 = * MUL long REG rdx
/--* t23 long
+--* t28 long
N060 (???,???) [000137] -c---------- t137 = * LEA(b+(i*1)+0) long REG NA
/--* t137 long
N062 ( 14, 13) [000030] *c-XG------- t30 = * IND long REG NA
/--* t30 long
N064 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount REG rdi
/--* t31 long
N066 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long REG rax
/--* t22 int
+--* t131 int
N068 ( 36, 35) [000032] ---XG------- t32 = * ADD int REG rcx
N070 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0 rax REG rax
N072 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3 REG rdx
/--* t34 int
N074 ( 2, 3) [000035] ------------ t35 = * CAST long <- int REG rdx
N076 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8 REG rdi
/--* t36 int
N078 ( 2, 3) [000037] ------------ t37 = * CAST long <- int REG rdi
/--* t35 long
+--* t37 long
N080 ( 8, 9) [000038] ------------ t38 = * MUL long REG rdx
/--* t33 long
+--* t38 long
N082 (???,???) [000138] -c---------- t138 = * LEA(b+(i*1)+0) long REG NA
/--* t138 long
N084 ( 14, 13) [000040] *c-XG------- t40 = * IND long REG NA
/--* t40 long
N086 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount REG rdi
/--* t41 long
N088 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long REG rax
/--* t32 int
+--* t129 int
N090 ( 53, 52) [000042] ---XG------- t42 = * ADD int REG rcx
N092 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2 rax REG rax
/--* t12 int
+--* t42 int
N094 ( 57, 55) [000044] ---XG------- t44 = * SUB int REG rax
/--* t44 int
N096 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2 NA REG NA
N098 ( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34 REG NA
N100 ( 3, 2) [000048] -c---------- t48 = LCL_VAR long V03 loc0 NA REG NA
N102 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4 REG rcx
/--* t49 int
N104 ( 2, 3) [000050] ------------ t50 = * CAST long <- int REG rcx
N106 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8 REG rax
/--* t51 int
N108 ( 2, 3) [000052] ------------ t52 = * CAST long <- int REG rax
/--* t50 long
+--* t52 long
N110 ( 8, 9) [000053] ------------ t53 = * MUL long REG rcx
/--* t48 long
+--* t53 long
N112 ( 12, 12) [000054] ------------ t54 = * ADD long REG rcx
/--* t54 long
N114 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
------------ BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
N010 ( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b REG NA
N012 ( 3, 2) [000006] -c---------- t6 = LCL_VAR int V02 arg2 NA REG NA
N014 ( 1, 4) [000007] -c---------- t7 = CNS_INT int 256 REG NA
/--* t6 int
+--* t7 int
N016 ( 5, 7) [000008] J------N---- * GE void REG NA
N018 ( 7, 9) [000009] ------------ * JTRUE void REG NA
------------ BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
N118 ( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43 REG NA
N120 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2 rcx REG rcx
/--* t59 int
N122 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1 NA REG NA
------------ BB05 [047..059), preds={BB06} succs={BB06}
N138 ( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47 REG NA
N140 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2 rcx REG rcx
/--* t70 int
N142 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1 NA REG NA
N144 ( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49 REG NA
N146 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2 rcx REG rcx
N148 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0 rax REG rax
/--* t75 long
N150 ( 6, 4) [000076] *c-XG------- t76 = * IND long REG NA
/--* t76 long
N152 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount REG rdx
/--* t77 long
N154 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long REG rax
/--* t74 int
+--* t78 int
N156 ( 12, 10) [000079] ---XG------- t79 = * SUB int REG rcx
/--* t79 int
N158 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2 NA REG NA
N160 ( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55 REG NA
N162 ( 3, 2) [000083] -c---------- t83 = LCL_VAR long V03 loc0 NA REG NA
N164 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8 REG rcx
/--* t84 int
N166 ( 2, 3) [000085] ------------ t85 = * CAST long <- int REG rcx
/--* t83 long
+--* t85 long
N168 ( 6, 6) [000086] ------------ t86 = * ADD long REG rcx
/--* t86 long
N170 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
------------ BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
N126 ( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59 REG NA
N128 ( 3, 2) [000064] -c---------- t64 = LCL_VAR int V02 arg2 NA REG NA
N130 ( 1, 1) [000065] -c---------- t65 = CNS_INT int 0 REG NA
/--* t64 int
+--* t65 int
N132 ( 5, 4) [000066] J------N---- * GT void REG NA
N134 ( 7, 6) [000067] ------------ * JTRUE void REG NA
------------ BB07 [05D..086) (return), preds={BB06} succs={}
N174 ( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d REG NA
N176 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0 rcx REG rcx
N178 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8 REG rax
/--* t92 int
N180 ( 2, 3) [000093] ------------ t93 = * CAST long <- int REG rax
/--* t91 long
+--* t93 long
N182 ( 6, 6) [000094] ------------ t94 = * SUB long REG rcx
/--* t94 long
N184 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
N186 ( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61 REG NA
N188 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1 rcx REG rcx
N190 ( 1, 1) [000101] -c---------- t101 = CNS_INT int -1 REG NA
/--* t100 int
+--* t101 int
N192 ( 5, 4) [000102] ------------ t102 = * ADD int REG rcx
N194 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1 REG rax
/--* t98 int
N196 ( 2, 3) [000099] ------------ t99 = * CAST long <- int REG rax
/--* t99 long
+--* t102 int
N198 ( 13, 10) [000105] ------------ t105 = * LSH long REG rax
N200 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0 rdx REG rdx
/--* t106 long
N202 ( 6, 4) [000107] *c-XG------- t107 = * IND long REG NA
/--* t105 long
+--* t107 long
N204 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit REG rax
/--* t108 long
N206 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount REG rdx
/--* t109 long
N208 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long REG rax
/--* t110 int
N210 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2 NA REG NA
N212 ( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78 REG NA
N214 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0 rax REG rax
N216 ( 3, 2) [000115] -c---------- t115 = LCL_VAR long V00 arg0 NA REG NA
/--* t114 long
+--* t115 long
N218 ( 7, 5) [000116] ------------ t116 = * SUB long REG rax
N220 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8 REG rdx
/--* t117 int
N222 ( 2, 3) [000118] ------------ t118 = * CAST long <- int REG rdi
/--* t116 long
+--* t118 long
N224 ( 29, 11) [000119] ---X-------- t119 = * DIV long REG rax
/--* t119 long
N226 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long REG rax
N228 ( 1, 1) [000120] -c---------- t120 = CNS_INT int 64 REG NA
/--* t134 int
+--* t120 int
N230 ( 35, 17) [000122] ---X-------- t122 = * MUL int REG rax
N232 ( 3, 2) [000124] -c---------- t124 = LCL_VAR int V05 loc2 NA REG NA
/--* t122 int
+--* t124 int
N234 ( 39, 20) [000125] ---X-------- t125 = * ADD int REG rax
/--* t125 int
N236 ( 40, 21) [000126] ---X-------- * RETURN int REG NA
-------------------------------------------------------------------------------------------------------------------
Final allocation
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
0.#0 BB1 PredBB0 | | | | | | | |
5.#1 I0 Def Alloc rcx | |I0 a| | | | | |
6.#2 I0 Use * Keep rcx | |I0 i| | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
8.#3 BB3 PredBB1 | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
20.#4 BB2 PredBB3 | | | | | | | |
25.#5 I1 Def Alloc rcx | |I1 a| | | | | |
28.#6 I1 Use *D Keep rcx | |I1 i| | | | | |
29.#7 I2 Def Alloc rax |I2 a| | | | | | |
30.#8 I2 Use * Keep rax |I2 i| | | | | | |
31.#9 I3 Def Alloc rcx | |I3 a| | | | | |
33.#10 I4 Def Alloc rax |I4 a|I3 a| | | | | |
35.#11 C5 Def Alloc rdx |I4 a|I3 a|C5 a| | | | |
36.#12 C5 Use * Keep rdx |I4 a|I3 a|C5 i| | | | |
37.#13 I6 Def Alloc rdx |I4 a|I3 a|I6 a| | | | |
42.#14 I4 Use *D Keep rax |I4 i|I3 a|I6 a| | | | |
42.#15 I6 Use *D Keep rdx | |I3 a|I6 i| | | | |
43.#16 I7 Def Alloc rdi | |I3 a| | |I7 a| | |
44.#17 I7 Use * Keep rdi | |I3 a| | |I7 i| | |
45.#18 I8 Def Alloc rax |I8 a|I3 a| | | | | |
46.#19 I3 Use * Keep rcx |I8 a|I3 i| | | | | |
46.#20 I8 Use * Keep rax |I8 i| | | | | | |
47.#21 I9 Def Alloc rcx | |I9 a| | | | | |
49.#22 I10 Def Alloc rax |I10a|I9 a| | | | | |
51.#23 C11 Def Alloc rdx |I10a|I9 a|C11a| | | | |
52.#24 C11 Use * Keep rdx |I10a|I9 a|C11i| | | | |
53.#25 I12 Def Alloc rdx |I10a|I9 a|I12a| | | | |
55.#26 C13 Def Alloc rdi |I10a|I9 a|I12a| |C13a| | |
56.#27 C13 Use * Keep rdi |I10a|I9 a|I12a| |C13i| | |
57.#28 I14 Def Alloc rdi |I10a|I9 a|I12a| |I14a| | |
58.#29 I12 Use * Keep rdx |I10a|I9 a|I12i| |I14a| | |
58.#30 I14 Use * Keep rdi |I10a|I9 a| | |I14i| | |
59.#31 I15 Def Alloc rdx |I10a|I9 a|I15a| | | | |
64.#32 I10 Use *D Keep rax |I10i|I9 a|I15a| | | | |
64.#33 I15 Use *D Keep rdx | |I9 a|I15i| | | | |
65.#34 I16 Def Alloc rdi | |I9 a| | |I16a| | |
66.#35 I16 Use * Keep rdi | |I9 a| | |I16i| | |
67.#36 I17 Def Alloc rax |I17a|I9 a| | | | | |
68.#37 I9 Use * Keep rcx |I17a|I9 i| | | | | |
68.#38 I17 Use * Keep rax |I17i| | | | | | |
69.#39 I18 Def Alloc rcx | |I18a| | | | | |
71.#40 I19 Def Alloc rax |I19a|I18a| | | | | |
73.#41 C20 Def Alloc rdx |I19a|I18a|C20a| | | | |
74.#42 C20 Use * Keep rdx |I19a|I18a|C20i| | | | |
75.#43 I21 Def Alloc rdx |I19a|I18a|I21a| | | | |
77.#44 C22 Def Alloc rdi |I19a|I18a|I21a| |C22a| | |
78.#45 C22 Use * Keep rdi |I19a|I18a|I21a| |C22i| | |
79.#46 I23 Def Alloc rdi |I19a|I18a|I21a| |I23a| | |
80.#47 I21 Use * Keep rdx |I19a|I18a|I21i| |I23a| | |
80.#48 I23 Use * Keep rdi |I19a|I18a| | |I23i| | |
81.#49 I24 Def Alloc rdx |I19a|I18a|I24a| | | | |
86.#50 I19 Use *D Keep rax |I19i|I18a|I24a| | | | |
86.#51 I24 Use *D Keep rdx | |I18a|I24i| | | | |
87.#52 I25 Def Alloc rdi | |I18a| | |I25a| | |
88.#53 I25 Use * Keep rdi | |I18a| | |I25i| | |
89.#54 I26 Def Alloc rax |I26a|I18a| | | | | |
90.#55 I18 Use * Keep rcx |I26a|I18i| | | | | |
90.#56 I26 Use * Keep rax |I26i| | | | | | |
91.#57 I27 Def Alloc rcx | |I27a| | | | | |
93.#58 I28 Def Alloc rax |I28a|I27a| | | | | |
94.#59 I28 Use * Keep rax |I28i|I27a| | | | | |
94.#60 I27 Use *D Keep rcx | |I27i| | | | | |
95.#61 I29 Def Alloc rax |I29a| | | | | | |
96.#62 I29 Use * Keep rax |I29i| | | | | | |
103.#63 C30 Def Alloc rcx | |C30a| | | | | |
104.#64 C30 Use * Keep rcx | |C30i| | | | | |
105.#65 I31 Def Alloc rcx | |I31a| | | | | |
107.#66 C32 Def Alloc rax |C32a|I31a| | | | | |
108.#67 C32 Use * Keep rax |C32i|I31a| | | | | |
109.#68 I33 Def Alloc rax |I33a|I31a| | | | | |
110.#69 I31 Use * Keep rcx |I33a|I31i| | | | | |
110.#70 I33 Use * Keep rax |I33i| | | | | | |
111.#71 I34 Def Alloc rcx | |I34a| | | | | |
112.#72 I34 Use * Keep rcx | |I34i| | | | | |
113.#73 I35 Def Alloc rcx | |I35a| | | | | |
114.#74 I35 Use * Keep rcx | |I35i| | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
116.#75 BB4 PredBB3 | | | | | | | |
121.#76 I36 Def Alloc rcx | |I36a| | | | | |
122.#77 I36 Use * Keep rcx | |I36i| | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
124.#78 BB6 PredBB4 | | | | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
136.#79 BB5 PredBB6 | | | | | | | |
141.#80 I37 Def Alloc rcx | |I37a| | | | | |
142.#81 I37 Use * Keep rcx | |I37i| | | | | |
147.#82 I38 Def Alloc rcx | |I38a| | | | | |
149.#83 I39 Def Alloc rax |I39a|I38a| | | | | |
152.#84 I39 Use *D Keep rax |I39i|I38a| | | | | |
153.#85 I40 Def Alloc rdx | |I38a|I40a| | | | |
154.#86 I40 Use * Keep rdx | |I38a|I40i| | | | |
155.#87 I41 Def Alloc rax |I41a|I38a| | | | | |
156.#88 I38 Use * Keep rcx |I41a|I38i| | | | | |
156.#89 I41 Use *D Keep rax |I41i| | | | | | |
157.#90 I42 Def Alloc rcx | |I42a| | | | | |
158.#91 I42 Use * Keep rcx | |I42i| | | | | |
165.#92 C43 Def Alloc rcx | |C43a| | | | | |
166.#93 C43 Use * Keep rcx | |C43i| | | | | |
167.#94 I44 Def Alloc rcx | |I44a| | | | | |
168.#95 I44 Use * Keep rcx | |I44i| | | | | |
169.#96 I45 Def Alloc rcx | |I45a| | | | | |
170.#97 I45 Use * Keep rcx | |I45i| | | | | |
--------------------------------+----+----+----+----+----+----+----+
Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rdi |r12 |r13 |
--------------------------------+----+----+----+----+----+----+----+
172.#98 BB7 PredBB6 | | | | | | | |
177.#99 I46 Def Alloc rcx | |I46a| | | | | |
179.#100 C47 Def Alloc rax |C47a|I46a| | | | | |
180.#101 C47 Use * Keep rax |C47i|I46a| | | | | |
181.#102 I48 Def Alloc rax |I48a|I46a| | | | | |
182.#103 I46 Use * Keep rcx |I48a|I46i| | | | | |
182.#104 I48 Use *D Keep rax |I48i| | | | | | |
183.#105 I49 Def Alloc rcx | |I49a| | | | | |
184.#106 I49 Use * Keep rcx | |I49i| | | | | |
189.#107 I50 Def Alloc rcx | |I50a| | | | | |
192.#108 I50 Use * Keep rcx | |I50i| | | | | |
193.#109 I51 Def Alloc rcx | |I51a| | | | | |
195.#110 C52 Def Alloc rax |C52a|I51a| | | | | |
196.#111 C52 Use * Keep rax |C52i|I51a| | | | | |
197.#112 I53 Def Alloc rax |I53a|I51a| | | | | |
198.#113 I53 Use * Keep rax |I53i|I51a| | | | | |
198.#114 rcx Fixd Keep rcx | |I51a| | | | | |
198.#115 I51 Use *D Keep rcx | |I51i| | | | | |
199.#116 rcx Kill Keep rcx | | | | | | | |
199.#117 I54 Def Alloc rax |I54a| | | | | | |
201.#118 I55 Def Alloc rdx |I54a| |I55a| | | | |
204.#119 I54 Use * Keep rax |I54i| |I55a| | | | |
204.#120 I55 Use * Keep rdx | | |I55i| | | | |
205.#121 I56 Def Alloc rax |I56a| | | | | | |
206.#122 I56 Use *D Keep rax |I56i| | | | | | |
207.#123 I57 Def Alloc rdx | | |I57a| | | | |
208.#124 I57 Use * Keep rdx | | |I57i| | | | |
209.#125 I58 Def Alloc rax |I58a| | | | | | |
210.#126 I58 Use * Keep rax |I58i| | | | | | |
215.#127 I59 Def Alloc rax |I59a| | | | | | |
218.#128 I59 Use * Keep rax |I59i| | | | | | |
219.#129 I60 Def Alloc rax |I60a| | | | | | |
221.#130 C61 Def Alloc rdx |I60a| |C61a| | | | |
222.#131 C61 Use * Keep rdx |I60a| |C61i| | | | |
223.#132 I62 Def Alloc rdi |I60a| | | |I62a| | |
224.#133 rax Fixd Keep rax |I60a| | | |I62a| | |
224.#134 I60 Use * Keep rax |I60i| | | |I62a| | |
224.#135 I62 Use *D Keep rdi | | | | |I62i| | |
225.#136 rax Kill Keep rax | | | | | | | |
225.#137 rdx Kill Keep rdx | | | | | | | |
225.#138 rax Fixd Keep rax | | | | | | | |
225.#139 I63 Def Alloc rax |I63a| | | | | | |
226.#140 I63 Use * Keep rax |I63i| | | | | | |
227.#141 I64 Def Alloc rax |I64a| | | | | | |
230.#142 I64 Use * Keep rax |I64i| | | | | | |
231.#143 I65 Def Alloc rax |I65a| | | | | | |
234.#144 I65 Use * Keep rax |I65i| | | | | | |
235.#145 I66 Def Alloc rax |I66a| | | | | | |
236.#146 rax Fixd Keep rax |I66a| | | | | | |
236.#147 I66 Use * Keep rax |I66i| | | | | | |
Recording the maximum number of concurrent spills:
----------
LSRA Stats
----------
Total Tracked Vars: 0
Total Reg Cand Vars: 0
Total number of Intervals: 66
Total number of RefPositions: 147
Total Spill Count: 0 Weighted: 0
Total CopyReg Count: 0 Weighted: 0
Total ResolutionMov Count: 0 Weighted: 0
Total number of split edges: 0
Total Number of spill temps created: 0
TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters:
BB01 [000..004) -> BB03 (always), preds={} succs={BB03}
=====
N002. IL_OFFSET IL offset: 0x0 REG NA
N004. rcx = V00 MEM
N006. V03 MEM; rcx
BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02}
=====
N010. IL_OFFSET IL offset: 0x3b REG NA
N012. V02 MEM
N014. CNS_INT 256 REG NA
N016. GE
N018. JTRUE
BB02 [004..03B), preds={BB03} succs={BB03}
=====
N022. IL_OFFSET IL offset: 0x4 REG NA
N024. rcx = V03 MEM
N026. STK = IND ; rcx
N028. rax = HWIntrinsic; STK
N030. rcx = CAST ; rax
N032. rax = V03 MEM
N034. rdx = CNS_INT 8 REG rdx
N036. rdx = CAST ; rdx
N038. STK = LEA(b+(i*1)+0); rax,rdx
N040. STK = IND ; STK
N042. rdi = HWIntrinsic; STK
N044. rax = CAST ; rdi
N046. rcx = ADD ; rcx,rax
N048. rax = V03 MEM
N050. rdx = CNS_INT 2 REG rdx
N052. rdx = CAST ; rdx
N054. rdi = CNS_INT 8 REG rdi
N056. rdi = CAST ; rdi
N058. rdx = MUL ; rdx,rdi
N060. STK = LEA(b+(i*1)+0); rax,rdx
N062. STK = IND ; STK
N064. rdi = HWIntrinsic; STK
N066. rax = CAST ; rdi
N068. rcx = ADD ; rcx,rax
N070. rax = V03 MEM
N072. rdx = CNS_INT 3 REG rdx
N074. rdx = CAST ; rdx
N076. rdi = CNS_INT 8 REG rdi
N078. rdi = CAST ; rdi
N080. rdx = MUL ; rdx,rdi
N082. STK = LEA(b+(i*1)+0); rax,rdx
N084. STK = IND ; STK
N086. rdi = HWIntrinsic; STK
N088. rax = CAST ; rdi
N090. rcx = ADD ; rcx,rax
N092. rax = V02 MEM
N094. rax = SUB ; rax,rcx
N096. V02 MEM; rax
N098. IL_OFFSET IL offset: 0x34 REG NA
N100. V03 MEM
N102. rcx = CNS_INT 4 REG rcx
N104. rcx = CAST ; rcx
N106. rax = CNS_INT 8 REG rax
N108. rax = CAST ; rax
N110. rcx = MUL ; rcx,rax
N112. rcx = ADD ; rcx
N114. V03 MEM; rcx
BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06}
=====
N118. IL_OFFSET IL offset: 0x43 REG NA
N120. rcx = V02 MEM
N122. V04 MEM; rcx
BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05}
=====
N126. IL_OFFSET IL offset: 0x59 REG NA
N128. V02 MEM
N130. CNS_INT 0 REG NA
N132. GT
N134. JTRUE
BB05 [047..059), preds={BB06} succs={BB06}
=====
N138. IL_OFFSET IL offset: 0x47 REG NA
N140. rcx = V02 MEM
N142. V04 MEM; rcx
N144. IL_OFFSET IL offset: 0x49 REG NA
N146. rcx = V02 MEM
N148. rax = V03 MEM
N150. STK = IND ; rax
N152. rdx = HWIntrinsic; STK
N154. rax = CAST ; rdx
N156. rcx = SUB ; rcx,rax
N158. V02 MEM; rcx
N160. IL_OFFSET IL offset: 0x55 REG NA
N162. V03 MEM
N164. rcx = CNS_INT 8 REG rcx
N166. rcx = CAST ; rcx
N168. rcx = ADD ; rcx
N170. V03 MEM; rcx
BB07 [05D..086) (return), preds={BB06} succs={}
=====
N174. IL_OFFSET IL offset: 0x5d REG NA
N176. rcx = V03 MEM
N178. rax = CNS_INT 8 REG rax
N180. rax = CAST ; rax
N182. rcx = SUB ; rcx,rax
N184. V03 MEM; rcx
N186. IL_OFFSET IL offset: 0x61 REG NA
N188. rcx = V04 MEM
N190. CNS_INT -1 REG NA
N192. rcx = ADD ; rcx
N194. rax = CNS_INT 1 REG rax
N196. rax = CAST ; rax
N198. rax = LSH ; rax,rcx
N200. rdx = V03 MEM
N202. STK = IND ; rdx
N204. rax = HWIntrinsic; rax,STK
N206. rdx = HWIntrinsic; rax
N208. rax = CAST ; rdx
N210. V05 MEM; rax
N212. IL_OFFSET IL offset: 0x78 REG NA
N214. rax = V03 MEM
N216. V00 MEM
N218. rax = SUB ; rax
N220. rdx = CNS_INT 8 REG rdx
N222. rdi = CAST ; rdx
N224. rax = DIV ; rax,rdi
N226. rax = CAST ; rax
N228. CNS_INT 64 REG NA
N230. rax = MUL ; rax
N232. V05 MEM
N234. rax = ADD ; rax
N236. RETURN ; rax
*************** In genGenerateCode()
--------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags]
--------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000] 1 1 [000..004)-> BB03 (always) i label target LIR
BB02 [0001] 1 BB03 1 [004..03B) i label target bwd LIR
BB03 [0002] 2 BB01,BB02 1 [03B..043)-> BB02 ( cond ) i label target bwd LIR
BB04 [0003] 1 BB03 1 [043..047)-> BB06 (always) i LIR
BB05 [0004] 1 BB06 1 [047..059) i label target bwd LIR
BB06 [0005] 2 BB04,BB05 1 [059..05D)-> BB05 ( cond ) i label target bwd LIR
BB07 [0006] 1 BB06 1 [05D..086) (return) i LIR
--------------------------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
Finalizing stack frame
Marking regs modified: [r13] ([rax rcx rdx rdi] => [rax rcx rdx rdi r13])
Modified regs: [rax rcx rdx rdi r13]
Callee-saved registers pushed: 1 [r13]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Assign V00 arg0, size=8, stkOffs=-0x20
Assign V01 arg1, size=4, stkOffs=-0x24
Assign V02 arg2, size=4, stkOffs=-0x28
Assign V03 loc0, size=8, stkOffs=-0x30
Assign V04 loc1, size=4, stkOffs=-0x34
Assign V05 loc2, size=4, stkOffs=-0x38
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) long -> [rbp-0x10]
; V01 arg1 [V01 ] ( 1, 1 ) int -> [rbp-0x14]
; V02 arg2 [V02 ] ( 1, 1 ) int -> [rbp-0x18]
; V03 loc0 [V03 ] ( 1, 1 ) long -> [rbp-0x20] must-init
; V04 loc1 [V04 ] ( 1, 1 ) int -> [rbp-0x24] must-init
; V05 loc2 [V05 ] ( 1, 1 ) int -> [rbp-0x28] must-init
;# V06 OutArgs [V06 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
;
; Lcl frame size = 40
=============== Generating BB01 [000..004) -> BB03 (always), preds={} succs={BB03} flags=0x00000000.40030020: i label target LIR
BB01 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M42618_BB01:
Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Setting stack level from -572662307 to 0
Scope info: begin block BB01, IL range [000..004)
Scope info: open scopes =
<none>
Added IP mapping: 0x0000 STACK_EMPTY (G_M42618_IG02,ins#0,ofs#0) label
Generating: N002 ( 7, 5) [000004] ------------ IL_OFFSET void IL offset: 0x0 REG NA
Generating: N004 ( 3, 2) [000001] ------------ t1 = LCL_VAR long V00 arg0 rcx REG rcx
IN0001: mov rcx, qword ptr [V00 rbp-10H]
/--* t1 long
Generating: N006 ( 7, 5) [000003] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
IN0002: mov qword ptr [V03 rbp-20H], rcx
Scope info: end block BB01, IL range [000..004)
Scope info: open scopes =
<none>
IN0003: jmp L_M42618_BB03
=============== Generating BB02 [004..03B), preds={BB03} succs={BB03} flags=0x00000000.42030020: i label target bwd LIR
BB02 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M42618_BB02:
G_M42618_IG02: ; offs=000000H, funclet=00
Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB02, IL range [004..03B)
Scope info: open scopes =
<none>
Added IP mapping: 0x0004 STACK_EMPTY (G_M42618_IG03,ins#0,ofs#0) label
Generating: N022 ( 61, 58) [000047] ------------ IL_OFFSET void IL offset: 0x4 REG NA
Generating: N024 ( 3, 2) [000013] ------------ t13 = LCL_VAR long V03 loc0 rcx REG rcx
IN0004: mov rcx, qword ptr [V03 rbp-20H]
/--* t13 long
Generating: N026 ( 6, 4) [000014] *c-XG------- t14 = * IND long REG NA
/--* t14 long
Generating: N028 ( 7, 5) [000015] ---XG------- t15 = * HWIntrinsic long PopCount REG rax
IN0005: xor eax, eax
IN0006: popcnt rax, qword ptr [rcx]
/--* t15 long
Generating: N030 ( 8, 7) [000132] ---XG------- t132 = * CAST int <- long REG rcx
IN0007: mov ecx, eax
Generating: N032 ( 3, 2) [000016] ------------ t16 = LCL_VAR long V03 loc0 rax REG rax
IN0008: mov rax, qword ptr [V03 rbp-20H]
Generating: N034 ( 1, 1) [000017] ------------ t17 = CNS_INT int 8 REG rdx
IN0009: mov edx, 8
/--* t17 int
Generating: N036 ( 2, 3) [000018] ------------ t18 = * CAST long <- int REG rdx
IN000a: movsxd rdx, edx
/--* t16 long
+--* t18 long
Generating: N038 (???,???) [000136] -c---------- t136 = * LEA(b+(i*1)+0) long REG NA
/--* t136 long
Generating: N040 ( 8, 7) [000020] *c-XG------- t20 = * IND long REG NA
/--* t20 long
Generating: N042 ( 9, 8) [000021] ---XG------- t21 = * HWIntrinsic long PopCount REG rdi
IN000b: xor edi, edi
IN000c: popcnt rdi, qword ptr [rax+rdx]
/--* t21 long
Generating: N044 ( 10, 10) [000133] ---XG------- t133 = * CAST int <- long REG rax
IN000d: mov eax, edi
/--* t132 int
+--* t133 int
Generating: N046 ( 19, 18) [000022] ---XG------- t22 = * ADD int REG rcx
IN000e: add ecx, eax
Generating: N048 ( 3, 2) [000023] ------------ t23 = LCL_VAR long V03 loc0 rax REG rax
IN000f: mov rax, qword ptr [V03 rbp-20H]
Generating: N050 ( 1, 1) [000024] ------------ t24 = CNS_INT int 2 REG rdx
IN0010: mov edx, 2
/--* t24 int
Generating: N052 ( 2, 3) [000025] ------------ t25 = * CAST long <- int REG rdx
IN0011: movsxd rdx, edx
Generating: N054 ( 1, 1) [000026] ------------ t26 = CNS_INT int 8 REG rdi
IN0012: mov edi, 8
/--* t26 int
Generating: N056 ( 2, 3) [000027] ------------ t27 = * CAST long <- int REG rdi
IN0013: movsxd rdi, edi
/--* t25 long
+--* t27 long
Generating: N058 ( 8, 9) [000028] ------------ t28 = * MUL long REG rdx
IN0014: imul rdx, rdi
/--* t23 long
+--* t28 long
Generating: N060 (???,???) [000137] -c---------- t137 = * LEA(b+(i*1)+0) long REG NA
/--* t137 long
Generating: N062 ( 14, 13) [000030] *c-XG------- t30 = * IND long REG NA
/--* t30 long
Generating: N064 ( 15, 14) [000031] ---XG------- t31 = * HWIntrinsic long PopCount REG rdi
IN0015: xor edi, edi
IN0016: popcnt rdi, qword ptr [rax+rdx]
/--* t31 long
Generating: N066 ( 16, 16) [000131] ---XG------- t131 = * CAST int <- long REG rax
IN0017: mov eax, edi
/--* t22 int
+--* t131 int
Generating: N068 ( 36, 35) [000032] ---XG------- t32 = * ADD int REG rcx
IN0018: add ecx, eax
Generating: N070 ( 3, 2) [000033] ------------ t33 = LCL_VAR long V03 loc0 rax REG rax
IN0019: mov rax, qword ptr [V03 rbp-20H]
Generating: N072 ( 1, 1) [000034] ------------ t34 = CNS_INT int 3 REG rdx
IN001a: mov edx, 3
/--* t34 int
Generating: N074 ( 2, 3) [000035] ------------ t35 = * CAST long <- int REG rdx
IN001b: movsxd rdx, edx
Generating: N076 ( 1, 1) [000036] ------------ t36 = CNS_INT int 8 REG rdi
IN001c: mov edi, 8
/--* t36 int
Generating: N078 ( 2, 3) [000037] ------------ t37 = * CAST long <- int REG rdi
IN001d: movsxd rdi, edi
/--* t35 long
+--* t37 long
Generating: N080 ( 8, 9) [000038] ------------ t38 = * MUL long REG rdx
IN001e: imul rdx, rdi
/--* t33 long
+--* t38 long
Generating: N082 (???,???) [000138] -c---------- t138 = * LEA(b+(i*1)+0) long REG NA
/--* t138 long
Generating: N084 ( 14, 13) [000040] *c-XG------- t40 = * IND long REG NA
/--* t40 long
Generating: N086 ( 15, 14) [000041] ---XG------- t41 = * HWIntrinsic long PopCount REG rdi
IN001f: xor edi, edi
IN0020: popcnt rdi, qword ptr [rax+rdx]
/--* t41 long
Generating: N088 ( 16, 16) [000129] ---XG------- t129 = * CAST int <- long REG rax
IN0021: mov eax, edi
/--* t32 int
+--* t129 int
Generating: N090 ( 53, 52) [000042] ---XG------- t42 = * ADD int REG rcx
IN0022: add ecx, eax
Generating: N092 ( 3, 2) [000012] ------------ t12 = LCL_VAR int V02 arg2 rax REG rax
IN0023: mov eax, dword ptr [V02 rbp-18H]
/--* t12 int
+--* t42 int
Generating: N094 ( 57, 55) [000044] ---XG------- t44 = * SUB int REG rax
IN0024: sub eax, ecx
/--* t44 int
Generating: N096 ( 61, 58) [000046] DA-XG------- * STORE_LCL_VAR int V02 arg2 NA REG NA
IN0025: mov dword ptr [V02 rbp-18H], eax
Added IP mapping: 0x0034 STACK_EMPTY (G_M42618_IG03,ins#34,ofs#117)
Generating: N098 ( 16, 15) [000057] ------------ IL_OFFSET void IL offset: 0x34 REG NA
Generating: N100 ( 3, 2) [000048] -c---------- t48 = LCL_VAR long V03 loc0 NA REG NA
Generating: N102 ( 1, 1) [000049] ------------ t49 = CNS_INT int 4 REG rcx
IN0026: mov ecx, 4
/--* t49 int
Generating: N104 ( 2, 3) [000050] ------------ t50 = * CAST long <- int REG rcx
IN0027: movsxd rcx, ecx
Generating: N106 ( 1, 1) [000051] ------------ t51 = CNS_INT int 8 REG rax
IN0028: mov eax, 8
/--* t51 int
Generating: N108 ( 2, 3) [000052] ------------ t52 = * CAST long <- int REG rax
IN0029: movsxd rax, eax
/--* t50 long
+--* t52 long
Generating: N110 ( 8, 9) [000053] ------------ t53 = * MUL long REG rcx
IN002a: imul rcx, rax
/--* t48 long
+--* t53 long
Generating: N112 ( 12, 12) [000054] ------------ t54 = * ADD long REG rcx
IN002b: add rcx, qword ptr [V03 rbp-20H]
/--* t54 long
Generating: N114 ( 16, 15) [000056] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
IN002c: mov qword ptr [V03 rbp-20H], rcx
Scope info: end block BB02, IL range [004..03B)
Scope info: open scopes =
<none>
=============== Generating BB03 [03B..043) -> BB02 (cond), preds={BB01,BB02} succs={BB04,BB02} flags=0x00000000.42030020: i label target bwd LIR
BB03 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M42618_BB03:
G_M42618_IG03: ; offs=00000DH, funclet=00
Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB03, IL range [03B..043)
Scope info: open scopes =
<none>
Added IP mapping: 0x003B STACK_EMPTY (G_M42618_IG04,ins#0,ofs#0) label
Generating: N010 ( 7, 9) [000010] ------------ IL_OFFSET void IL offset: 0x3b REG NA
Generating: N012 ( 3, 2) [000006] -c---------- t6 = LCL_VAR int V02 arg2 NA REG NA
Generating: N014 ( 1, 4) [000007] -c---------- t7 = CNS_INT int 256 REG NA
/--* t6 int
+--* t7 int
Generating: N016 ( 5, 7) [000008] J------N---- * GE void REG NA
IN002d: cmp dword ptr [V02 rbp-18H], 256
Generating: N018 ( 7, 9) [000009] ------------ * JTRUE void REG NA
IN002e: jge L_M42618_BB02
Scope info: end block BB03, IL range [03B..043)
Scope info: open scopes =
<none>
=============== Generating BB04 [043..047) -> BB06 (always), preds={BB03} succs={BB06} flags=0x00000000.40000020: i LIR
BB04 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M42618_BB04:
Scope info: begin block BB04, IL range [043..047)
Scope info: open scopes =
<none>
Added IP mapping: 0x0043 STACK_EMPTY (G_M42618_IG04,ins#2,ofs#13) label
Generating: N118 ( 7, 5) [000062] ------------ IL_OFFSET void IL offset: 0x43 REG NA
Generating: N120 ( 3, 2) [000059] ------------ t59 = LCL_VAR int V02 arg2 rcx REG rcx
IN002f: mov ecx, dword ptr [V02 rbp-18H]
/--* t59 int
Generating: N122 ( 7, 5) [000061] DA---------- * STORE_LCL_VAR int V04 loc1 NA REG NA
IN0030: mov dword ptr [V04 rbp-24H], ecx
Scope info: end block BB04, IL range [043..047)
Scope info: open scopes =
<none>
IN0031: jmp L_M42618_BB06
=============== Generating BB05 [047..059), preds={BB06} succs={BB06} flags=0x00000000.42030020: i label target bwd LIR
BB05 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M42618_BB05:
G_M42618_IG04: ; offs=00009EH, funclet=00
Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB05, IL range [047..059)
Scope info: open scopes =
<none>
Added IP mapping: 0x0047 STACK_EMPTY (G_M42618_IG05,ins#0,ofs#0) label
Generating: N138 ( 7, 5) [000073] ------------ IL_OFFSET void IL offset: 0x47 REG NA
Generating: N140 ( 3, 2) [000070] ------------ t70 = LCL_VAR int V02 arg2 rcx REG rcx
IN0032: mov ecx, dword ptr [V02 rbp-18H]
/--* t70 int
Generating: N142 ( 7, 5) [000072] DA---------- * STORE_LCL_VAR int V04 loc1 NA REG NA
IN0033: mov dword ptr [V04 rbp-24H], ecx
Added IP mapping: 0x0049 STACK_EMPTY (G_M42618_IG05,ins#2,ofs#6)
Generating: N144 ( 16, 13) [000082] ------------ IL_OFFSET void IL offset: 0x49 REG NA
Generating: N146 ( 3, 2) [000074] ------------ t74 = LCL_VAR int V02 arg2 rcx REG rcx
IN0034: mov ecx, dword ptr [V02 rbp-18H]
Generating: N148 ( 3, 2) [000075] ------------ t75 = LCL_VAR long V03 loc0 rax REG rax
IN0035: mov rax, qword ptr [V03 rbp-20H]
/--* t75 long
Generating: N150 ( 6, 4) [000076] *c-XG------- t76 = * IND long REG NA
/--* t76 long
Generating: N152 ( 7, 5) [000077] ---XG------- t77 = * HWIntrinsic long PopCount REG rdx
IN0036: xor edx, edx
IN0037: popcnt rdx, qword ptr [rax]
/--* t77 long
Generating: N154 ( 8, 7) [000078] ---XG------- t78 = * CAST int <- long REG rax
IN0038: mov eax, edx
/--* t74 int
+--* t78 int
Generating: N156 ( 12, 10) [000079] ---XG------- t79 = * SUB int REG rcx
IN0039: sub ecx, eax
/--* t79 int
Generating: N158 ( 16, 13) [000081] DA-XG------- * STORE_LCL_VAR int V02 arg2 NA REG NA
IN003a: mov dword ptr [V02 rbp-18H], ecx
Added IP mapping: 0x0055 STACK_EMPTY (G_M42618_IG05,ins#9,ofs#27)
Generating: N160 ( 10, 9) [000089] ------------ IL_OFFSET void IL offset: 0x55 REG NA
Generating: N162 ( 3, 2) [000083] -c---------- t83 = LCL_VAR long V03 loc0 NA REG NA
Generating: N164 ( 1, 1) [000084] ------------ t84 = CNS_INT int 8 REG rcx
IN003b: mov ecx, 8
/--* t84 int
Generating: N166 ( 2, 3) [000085] ------------ t85 = * CAST long <- int REG rcx
IN003c: movsxd rcx, ecx
/--* t83 long
+--* t85 long
Generating: N168 ( 6, 6) [000086] ------------ t86 = * ADD long REG rcx
IN003d: add rcx, qword ptr [V03 rbp-20H]
/--* t86 long
Generating: N170 ( 10, 9) [000088] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
IN003e: mov qword ptr [V03 rbp-20H], rcx
Scope info: end block BB05, IL range [047..059)
Scope info: open scopes =
<none>
=============== Generating BB06 [059..05D) -> BB05 (cond), preds={BB04,BB05} succs={BB07,BB05} flags=0x00000000.42030020: i label target bwd LIR
BB06 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M42618_BB06:
G_M42618_IG05: ; offs=0000B6H, funclet=00
Label: IG06, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}
Scope info: begin block BB06, IL range [059..05D)
Scope info: open scopes =
<none>
Added IP mapping: 0x0059 STACK_EMPTY (G_M42618_IG06,ins#0,ofs#0) label
Generating: N126 ( 7, 6) [000068] ------------ IL_OFFSET void IL offset: 0x59 REG NA
Generating: N128 ( 3, 2) [000064] -c---------- t64 = LCL_VAR int V02 arg2 NA REG NA
Generating: N130 ( 1, 1) [000065] -c---------- t65 = CNS_INT int 0 REG NA
/--* t64 int
+--* t65 int
Generating: N132 ( 5, 4) [000066] J------N---- * GT void REG NA
IN003f: cmp dword ptr [V02 rbp-18H], 0
Generating: N134 ( 7, 6) [000067] ------------ * JTRUE void REG NA
IN0040: jg SHORT L_M42618_BB05
Scope info: end block BB06, IL range [059..05D)
Scope info: open scopes =
<none>
=============== Generating BB07 [05D..086) (return), preds={BB06} succs={} flags=0x00000000.40000020: i LIR
BB07 IN (0)={} + ByrefExposed + GcHeap
OUT(0)={} + ByrefExposed + GcHeap
Liveness not changing: 0000000000000000 {}
Live regs: (unchanged) 00000000 {}
GC regs: (unchanged) 00000000 {}
Byref regs: (unchanged) 00000000 {}
L_M42618_BB07:
Scope info: begin block BB07, IL range [05D..086)
Scope info: open scopes =
<none>
Added IP mapping: 0x005D STACK_EMPTY (G_M42618_IG06,ins#2,ofs#6) label
Generating: N174 ( 10, 9) [000097] ------------ IL_OFFSET void IL offset: 0x5d REG NA
Generating: N176 ( 3, 2) [000091] ------------ t91 = LCL_VAR long V03 loc0 rcx REG rcx
IN0041: mov rcx, qword ptr [V03 rbp-20H]
Generating: N178 ( 1, 1) [000092] ------------ t92 = CNS_INT int 8 REG rax
IN0042: mov eax, 8
/--* t92 int
Generating: N180 ( 2, 3) [000093] ------------ t93 = * CAST long <- int REG rax
IN0043: movsxd rax, eax
/--* t91 long
+--* t93 long
Generating: N182 ( 6, 6) [000094] ------------ t94 = * SUB long REG rcx
IN0044: sub rcx, rax
/--* t94 long
Generating: N184 ( 10, 9) [000096] DA---------- * STORE_LCL_VAR long V03 loc0 NA REG NA
IN0045: mov qword ptr [V03 rbp-20H], rcx
Added IP mapping: 0x0061 STACK_EMPTY (G_M42618_IG06,ins#7,ofs#25)
Generating: N186 ( 26, 21) [000113] ------------ IL_OFFSET void IL offset: 0x61 REG NA
Generating: N188 ( 3, 2) [000100] ------------ t100 = LCL_VAR int V04 loc1 rcx REG rcx
IN0046: mov ecx, dword ptr [V04 rbp-24H]
Generating: N190 ( 1, 1) [000101] -c---------- t101 = CNS_INT int -1 REG NA
/--* t100 int
+--* t101 int
Generating: N192 ( 5, 4) [000102] ------------ t102 = * ADD int REG rcx
IN0047: dec ecx
Generating: N194 ( 1, 1) [000098] ------------ t98 = CNS_INT int 1 REG rax
IN0048: mov eax, 1
/--* t98 int
Generating: N196 ( 2, 3) [000099] ------------ t99 = * CAST long <- int REG rax
IN0049: movsxd rax, eax
/--* t99 long
+--* t102 int
Generating: N198 ( 13, 10) [000105] ------------ t105 = * LSH long REG rax
IN004a: shl rax, cl
Generating: N200 ( 3, 2) [000106] ------------ t106 = LCL_VAR long V03 loc0 rdx REG rdx
IN004b: mov rdx, qword ptr [V03 rbp-20H]
/--* t106 long
Generating: N202 ( 6, 4) [000107] *c-XG------- t107 = * IND long REG NA
/--* t105 long
+--* t107 long
Generating: N204 ( 20, 15) [000108] ---XG------- t108 = * HWIntrinsic long ParallelBitDeposit REG rax
IN004c: vpdep rax, rax, qword ptr [rdx]
/--* t108 long
Generating: N206 ( 21, 16) [000109] ---XG------- t109 = * HWIntrinsic long TrailingZeroCount REG rdx
IN004d: xor edx, edx
IN004e: tzcnt rdx, rax
/--* t109 long
Generating: N208 ( 22, 18) [000110] ---XG------- t110 = * CAST int <- long REG rax
IN004f: mov eax, edx
/--* t110 int
Generating: N210 ( 26, 21) [000112] DA-XG------- * STORE_LCL_VAR int V05 loc2 NA REG NA
IN0050: mov dword ptr [V05 rbp-28H], eax
Added IP mapping: 0x0078 STACK_EMPTY (G_M42618_IG06,ins#18,ofs#62)
Generating: N212 ( 40, 21) [000127] ------------ IL_OFFSET void IL offset: 0x78 REG NA
Generating: N214 ( 3, 2) [000114] ------------ t114 = LCL_VAR long V03 loc0 rax REG rax
IN0051: mov rax, qword ptr [V03 rbp-20H]
Generating: N216 ( 3, 2) [000115] -c---------- t115 = LCL_VAR long V00 arg0 NA REG NA
/--* t114 long
+--* t115 long
Generating: N218 ( 7, 5) [000116] ------------ t116 = * SUB long REG rax
IN0052: sub rax, qword ptr [V00 rbp-10H]
Generating: N220 ( 1, 1) [000117] ------------ t117 = CNS_INT int 8 REG rdx
IN0053: mov edx, 8
/--* t117 int
Generating: N222 ( 2, 3) [000118] ------------ t118 = * CAST long <- int REG rdi
IN0054: movsxd rdi, edx
/--* t116 long
+--* t118 long
Generating: N224 ( 29, 11) [000119] ---X-------- t119 = * DIV long REG rax
IN0055: cdq
IN0056: idiv rdx:rax, rdi
/--* t119 long
Generating: N226 ( 30, 13) [000134] ---X-------- t134 = * CAST int <- long REG rax
Generating: N228 ( 1, 1) [000120] -c---------- t120 = CNS_INT int 64 REG NA
/--* t134 int
+--* t120 int
Generating: N230 ( 35, 17) [000122] ---X-------- t122 = * MUL int REG rax
IN0057: shl eax, 6
Generating: N232 ( 3, 2) [000124] -c---------- t124 = LCL_VAR int V05 loc2 NA REG NA
/--* t122 int
+--* t124 int
Generating: N234 ( 39, 20) [000125] ---X-------- t125 = * ADD int REG rax
IN0058: add eax, dword ptr [V05 rbp-28H]
/--* t125 int
Generating: N236 ( 40, 21) [000126] ---X-------- * RETURN int REG NA
Scope info: end block BB07, IL range [05D..086)
Scope info: ending scope, LVnum=0 [000..086)
Scope info: ending scope, LVnum=1 [000..086)
Scope info: ending scope, LVnum=2 [000..086)
Scope info: ending scope, LVnum=3 [000..086)
Scope info: ending scope, LVnum=4 [000..086)
Scope info: ending scope, LVnum=5 [000..086)
Scope info: open scopes =
<none>
Added IP mapping: EPILOG STACK_EMPTY (G_M42618_IG06,ins#26,ofs#89) label
Reserving epilog IG for block BB07
G_M42618_IG06: ; offs=0000E1H, funclet=00
*************** After placeholder IG creation
G_M42618_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M42618_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG03: ; offs=00000DH, size=0091H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG04: ; offs=00009EH, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG05: ; offs=0000B6H, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG06: ; offs=0000E1H, size=0059H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG07: ; epilog placeholder, next placeholder=<END>, BB07 [0006], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
Liveness not changing: 0000000000000000 {}
# compCycleEstimate = 214, compSizeEstimate = 176 GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
; Final local variable assignments
;
; V00 arg0 [V00 ] ( 1, 1 ) long -> [rbp-0x10]
; V01 arg1 [V01 ] ( 1, 1 ) int -> [rbp-0x14]
; V02 arg2 [V02 ] ( 1, 1 ) int -> [rbp-0x18]
; V03 loc0 [V03 ] ( 1, 1 ) long -> [rbp-0x20] must-init
; V04 loc1 [V04 ] ( 1, 1 ) int -> [rbp-0x24] must-init
; V05 loc2 [V05 ] ( 1, 1 ) int -> [rbp-0x28] must-init
;# V06 OutArgs [V06 ] ( 1, 1 ) lclBlk ( 0) [rsp+0x00]
;
; Lcl frame size = 40
*************** Before prolog / epilog generation
G_M42618_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG
G_M42618_IG02: ; offs=000000H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG03: ; offs=00000DH, size=0091H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG04: ; offs=00009EH, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG05: ; offs=0000B6H, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG06: ; offs=0000E1H, size=0059H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG07: ; epilog placeholder, next placeholder=<END>, BB07 [0006], epilog, emitadd <-- First placeholder <-- Last placeholder
; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {}
; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG STACK_EMPTY (G_M42618_IG01,ins#0,ofs#0) label
__prolog:
Found 6 lvMustInit stk vars, frame offsets 40 through 24
IN0059: push rbp
IN005a: push r13
IN005b: sub rsp, 40
IN005c: lea rbp, [rsp+30H]
IN005d: mov r13, rdi
IN005e: lea rdi, [rbp-28H]
IN005f: mov ecx, 4
IN0060: xor rax, rax
IN0061: rep stosd
IN0062: mov rdi, r13
*************** In genClearStackVec3ArgUpperBits()
*************** In genFnPrologCalleeRegArgs() for int regs
IN0063: mov qword ptr [V00 rbp-10H], rdi
IN0064: mov dword ptr [V01 rbp-14H], esi
IN0065: mov dword ptr [V02 rbp-18H], edx
*************** In genEnregisterIncomingStackArgs()
G_M42618_IG01: ; offs=000000H, funclet=00
*************** In genFnEpilog()
__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {}
IN0066: lea rsp, [rbp-08H]
IN0067: pop r13
IN0068: pop rbp
IN0069: ret
G_M42618_IG07: ; offs=00013AH, funclet=00
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M42618_IG01: ; func=00, offs=000000H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
G_M42618_IG02: ; offs=000029H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG03: ; offs=000036H, size=0091H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG04: ; offs=0000C7H, size=0018H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG05: ; offs=0000DFH, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG06: ; offs=00010AH, size=0059H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
G_M42618_IG07: ; offs=000163H, size=0008H, epilog, nogc, emitadd
*************** In emitJumpDistBind()
Binding: IN0003: 000000 jmp L_M42618_BB03
Binding L_M42618_BB03to G_M42618_IG04
Estimate of fwd jump [0140E31C/003]: 0031 -> 00C7 = 0094
Adjusted offset of BB03 from 0036 to 0036
Adjusted offset of BB04 from 00C7 to 00C7
Binding: IN002e: 000000 jge L_M42618_BB02
Binding L_M42618_BB02to G_M42618_IG03
Estimate of bwd jump [0140F0BC/046]: 00CE -> 0036 = 009A
Binding: IN0031: 000000 jmp L_M42618_BB06
Binding L_M42618_BB06to G_M42618_IG06
Estimate of fwd jump [0140F124/049]: 00DA -> 010A = 002E
Shrinking jump [0140F124/049]
Adjusted offset of BB05 from 00DF to 00DC
Adjusted offset of BB06 from 010A to 0107
Binding: IN0040: 000000 jg SHORT L_M42618_BB05
Binding L_M42618_BB05to G_M42618_IG05
Estimate of bwd jump [0140FBF4/064]: 010B -> 00DC = 0031
Shrinking jump [0140FBF4/064]
Adjusted offset of BB07 from 0163 to 0160
Total shrinkage = 3, min extra jump size = 21
Hot code size = 0x168 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0xa)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)
***************************************************************************
Instructions as they come out of the scheduler
G_M42618_IG01: ; func=00, offs=000000H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0059: 000000 55 push rbp
IN005a: 000001 4155 push r13
IN005b: 000003 4883EC28 sub rsp, 40
IN005c: 000007 488D6C2430 lea rbp, [rsp+30H]
IN005d: 00000C 4C8BEF mov r13, rdi
IN005e: 00000F 488D7DD8 lea rdi, [rbp-28H]
IN005f: 000013 B904000000 mov ecx, 4
IN0060: 000018 33C0 xor rax, rax
IN0061: 00001A F3AB rep stosd
IN0062: 00001C 498BFD mov rdi, r13
IN0063: 00001F 48897DF0 mov qword ptr [rbp-10H], rdi
IN0064: 000023 8975EC mov dword ptr [rbp-14H], esi
IN0065: 000026 8955E8 mov dword ptr [rbp-18H], edx
G_M42618_IG02: ; func=00, offs=000029H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 000029 488B4DF0 mov rcx, qword ptr [rbp-10H]
IN0002: 00002D 48894DE0 mov qword ptr [rbp-20H], rcx
IN0003: 000031 E991000000 jmp G_M42618_IG04
G_M42618_IG03: ; func=00, offs=000036H, size=0091H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0004: 000036 488B4DE0 mov rcx, qword ptr [rbp-20H]
IN0005: 00003A 33C0 xor eax, eax
IN0006: 00003C F3480FB801 popcnt rax, qword ptr [rcx]
IN0007: 000041 8BC8 mov ecx, eax
IN0008: 000043 488B45E0 mov rax, qword ptr [rbp-20H]
IN0009: 000047 BA08000000 mov edx, 8
IN000a: 00004C 4863D2 movsxd rdx, edx
IN000b: 00004F 33FF xor edi, edi
IN000c: 000051 F3480FB83C10 popcnt rdi, qword ptr [rax+rdx]
IN000d: 000057 8BC7 mov eax, edi
IN000e: 000059 03C8 add ecx, eax
IN000f: 00005B 488B45E0 mov rax, qword ptr [rbp-20H]
IN0010: 00005F BA02000000 mov edx, 2
IN0011: 000064 4863D2 movsxd rdx, edx
IN0012: 000067 BF08000000 mov edi, 8
IN0013: 00006C 4863FF movsxd rdi, edi
IN0014: 00006F 480FAFD7 imul rdx, rdi
IN0015: 000073 33FF xor edi, edi
IN0016: 000075 F3480FB83C10 popcnt rdi, qword ptr [rax+rdx]
IN0017: 00007B 8BC7 mov eax, edi
IN0018: 00007D 03C8 add ecx, eax
IN0019: 00007F 488B45E0 mov rax, qword ptr [rbp-20H]
IN001a: 000083 BA03000000 mov edx, 3
IN001b: 000088 4863D2 movsxd rdx, edx
IN001c: 00008B BF08000000 mov edi, 8
IN001d: 000090 4863FF movsxd rdi, edi
IN001e: 000093 480FAFD7 imul rdx, rdi
IN001f: 000097 33FF xor edi, edi
IN0020: 000099 F3480FB83C10 popcnt rdi, qword ptr [rax+rdx]
IN0021: 00009F 8BC7 mov eax, edi
IN0022: 0000A1 03C8 add ecx, eax
IN0023: 0000A3 8B45E8 mov eax, dword ptr [rbp-18H]
IN0024: 0000A6 2BC1 sub eax, ecx
IN0025: 0000A8 8945E8 mov dword ptr [rbp-18H], eax
IN0026: 0000AB B904000000 mov ecx, 4
IN0027: 0000B0 4863C9 movsxd rcx, ecx
IN0028: 0000B3 B808000000 mov eax, 8
IN0029: 0000B8 4863C0 movsxd rax, eax
IN002a: 0000BB 480FAFC8 imul rcx, rax
IN002b: 0000BF 48034DE0 add rcx, qword ptr [rbp-20H]
IN002c: 0000C3 48894DE0 mov qword ptr [rbp-20H], rcx
G_M42618_IG04: ; func=00, offs=0000C7H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN002d: 0000C7 817DE800010000 cmp dword ptr [rbp-18H], 256
IN002e: 0000CE 0F8D62FFFFFF jge G_M42618_IG03
IN002f: 0000D4 8B4DE8 mov ecx, dword ptr [rbp-18H]
IN0030: 0000D7 894DDC mov dword ptr [rbp-24H], ecx
IN0031: 0000DA EB2B jmp SHORT G_M42618_IG06
G_M42618_IG05: ; func=00, offs=0000DCH, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0032: 0000DC 8B4DE8 mov ecx, dword ptr [rbp-18H]
IN0033: 0000DF 894DDC mov dword ptr [rbp-24H], ecx
IN0034: 0000E2 8B4DE8 mov ecx, dword ptr [rbp-18H]
IN0035: 0000E5 488B45E0 mov rax, qword ptr [rbp-20H]
IN0036: 0000E9 33D2 xor edx, edx
IN0037: 0000EB F3480FB810 popcnt rdx, qword ptr [rax]
IN0038: 0000F0 8BC2 mov eax, edx
IN0039: 0000F2 2BC8 sub ecx, eax
IN003a: 0000F4 894DE8 mov dword ptr [rbp-18H], ecx
IN003b: 0000F7 B908000000 mov ecx, 8
IN003c: 0000FC 4863C9 movsxd rcx, ecx
IN003d: 0000FF 48034DE0 add rcx, qword ptr [rbp-20H]
IN003e: 000103 48894DE0 mov qword ptr [rbp-20H], rcx
G_M42618_IG06: ; func=00, offs=000107H, size=0059H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN003f: 000107 837DE800 cmp dword ptr [rbp-18H], 0
IN0040: 00010B 7FCF jg SHORT G_M42618_IG05
IN0041: 00010D 488B4DE0 mov rcx, qword ptr [rbp-20H]
IN0042: 000111 B808000000 mov eax, 8
IN0043: 000116 4863C0 movsxd rax, eax
IN0044: 000119 482BC8 sub rcx, rax
IN0045: 00011C 48894DE0 mov qword ptr [rbp-20H], rcx
IN0046: 000120 8B4DDC mov ecx, dword ptr [rbp-24H]
IN0047: 000123 FFC9 dec ecx
IN0048: 000125 B801000000 mov eax, 1
IN0049: 00012A 4863C0 movsxd rax, eax
IN004a: 00012D 48D3E0 shl rax, cl
IN004b: 000130 488B55E0 mov rdx, qword ptr [rbp-20H]
IN004c: 000134 C4E2FBF502 vpdep rax, rax, qword ptr [rdx]
IN004d: 000139 33D2 xor edx, edx
IN004e: 00013B F3480FBCD0 tzcnt rdx, rax
IN004f: 000140 8BC2 mov eax, edx
IN0050: 000142 8945D8 mov dword ptr [rbp-28H], eax
IN0051: 000145 488B45E0 mov rax, qword ptr [rbp-20H]
IN0052: 000149 482B45F0 sub rax, qword ptr [rbp-10H]
IN0053: 00014D BA08000000 mov edx, 8
IN0054: 000152 4863FA movsxd rdi, edx
IN0055: 000155 4899 cdq
IN0056: 000157 48F7FF idiv rdx:rax, rdi
IN0057: 00015A C1E006 shl eax, 6
IN0058: 00015D 0345D8 add eax, dword ptr [rbp-28H]
G_M42618_IG07: ; func=00, offs=000160H, size=0008H, epilog, nogc, emitadd
IN0066: 000160 488D65F8 lea rsp, [rbp-08H]
IN0067: 000164 415D pop r13
IN0068: 000166 5D pop rbp
IN0069: 000167 C3 ret
Allocated method code size = 360 , actual size = 360
*************** After end code gen, before unwindEmit()
G_M42618_IG01: ; func=00, offs=000000H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG
IN0059: 000000 push rbp
IN005a: 000001 push r13
IN005b: 000003 sub rsp, 40
IN005c: 000007 lea rbp, [rsp+30H]
IN005d: 00000C mov r13, rdi
IN005e: 00000F lea rdi, [rbp-28H]
IN005f: 000013 mov ecx, 4
IN0060: 000018 xor rax, rax
IN0061: 00001A rep stosd
IN0062: 00001C mov rdi, r13
IN0063: 00001F mov qword ptr [V00 rbp-10H], rdi
IN0064: 000023 mov dword ptr [V01 rbp-14H], esi
IN0065: 000026 mov dword ptr [V02 rbp-18H], edx
G_M42618_IG02: ; offs=000029H, size=000DH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0001: 000029 mov rcx, qword ptr [V00 rbp-10H]
IN0002: 00002D mov qword ptr [V03 rbp-20H], rcx
IN0003: 000031 jmp G_M42618_IG04
G_M42618_IG03: ; offs=000036H, size=0091H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0004: 000036 mov rcx, qword ptr [V03 rbp-20H]
IN0005: 00003A xor eax, eax
IN0006: 00003C popcnt rax, qword ptr [rcx]
IN0007: 000041 mov ecx, eax
IN0008: 000043 mov rax, qword ptr [V03 rbp-20H]
IN0009: 000047 mov edx, 8
IN000a: 00004C movsxd rdx, edx
IN000b: 00004F xor edi, edi
IN000c: 000051 popcnt rdi, qword ptr [rax+rdx]
IN000d: 000057 mov eax, edi
IN000e: 000059 add ecx, eax
IN000f: 00005B mov rax, qword ptr [V03 rbp-20H]
IN0010: 00005F mov edx, 2
IN0011: 000064 movsxd rdx, edx
IN0012: 000067 mov edi, 8
IN0013: 00006C movsxd rdi, edi
IN0014: 00006F imul rdx, rdi
IN0015: 000073 xor edi, edi
IN0016: 000075 popcnt rdi, qword ptr [rax+rdx]
IN0017: 00007B mov eax, edi
IN0018: 00007D add ecx, eax
IN0019: 00007F mov rax, qword ptr [V03 rbp-20H]
IN001a: 000083 mov edx, 3
IN001b: 000088 movsxd rdx, edx
IN001c: 00008B mov edi, 8
IN001d: 000090 movsxd rdi, edi
IN001e: 000093 imul rdx, rdi
IN001f: 000097 xor edi, edi
IN0020: 000099 popcnt rdi, qword ptr [rax+rdx]
IN0021: 00009F mov eax, edi
IN0022: 0000A1 add ecx, eax
IN0023: 0000A3 mov eax, dword ptr [V02 rbp-18H]
IN0024: 0000A6 sub eax, ecx
IN0025: 0000A8 mov dword ptr [V02 rbp-18H], eax
IN0026: 0000AB mov ecx, 4
IN0027: 0000B0 movsxd rcx, ecx
IN0028: 0000B3 mov eax, 8
IN0029: 0000B8 movsxd rax, eax
IN002a: 0000BB imul rcx, rax
IN002b: 0000BF add rcx, qword ptr [V03 rbp-20H]
IN002c: 0000C3 mov qword ptr [V03 rbp-20H], rcx
G_M42618_IG04: ; offs=0000C7H, size=0015H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN002d: 0000C7 cmp dword ptr [V02 rbp-18H], 256
IN002e: 0000CE jge G_M42618_IG03
IN002f: 0000D4 mov ecx, dword ptr [V02 rbp-18H]
IN0030: 0000D7 mov dword ptr [V04 rbp-24H], ecx
IN0031: 0000DA jmp SHORT G_M42618_IG06
G_M42618_IG05: ; offs=0000DCH, size=002BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
IN0032: 0000DC mov ecx, dword ptr [V02 rbp-18H]
IN0033: 0000DF mov dword ptr [V04 rbp-24H], ecx
IN0034: 0000E2 mov ecx, dword ptr [V02 rbp-18H]
IN0035: 0000E5 mov rax, qword ptr [V03 rbp-20H]
IN0036: 0000E9 xor edx, edx
IN0037: 0000EB popcnt rdx, qword ptr [rax]
IN0038: 0000F0 mov eax, edx
IN0039: 0000F2 sub ecx, eax
IN003a: 0000F4 mov dword ptr [V02 rbp-18H], ecx
IN003b: 0000F7 mov ecx, 8
IN003c: 0000FC movsxd rcx, ecx
IN003d: 0000FF add rcx, qword ptr [V03 rbp-20H]
IN003e: 000103 mov qword ptr [V03 rbp-20H], rcx
G_M42618_IG06: ; offs=000107H, size=0059H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
IN003f: 000107 cmp dword ptr [V02 rbp-18H], 0
IN0040: 00010B jg SHORT G_M42618_IG05
IN0041: 00010D mov rcx, qword ptr [V03 rbp-20H]
IN0042: 000111 mov eax, 8
IN0043: 000116 movsxd rax, eax
IN0044: 000119 sub rcx, rax
IN0045: 00011C mov qword ptr [V03 rbp-20H], rcx
IN0046: 000120 mov ecx, dword ptr [V04 rbp-24H]
IN0047: 000123 dec ecx
IN0048: 000125 mov eax, 1
IN0049: 00012A movsxd rax, eax
IN004a: 00012D shl rax, cl
IN004b: 000130 mov rdx, qword ptr [V03 rbp-20H]
IN004c: 000134 vpdep rax, rax, qword ptr [rdx]
IN004d: 000139 xor edx, edx
IN004e: 00013B tzcnt rdx, rax
IN004f: 000140 mov eax, edx
IN0050: 000142 mov dword ptr [V05 rbp-28H], eax
IN0051: 000145 mov rax, qword ptr [V03 rbp-20H]
IN0052: 000149 sub rax, qword ptr [V00 rbp-10H]
IN0053: 00014D mov edx, 8
IN0054: 000152 movsxd rdi, edx
IN0055: 000155 cdq
IN0056: 000157 idiv rdx:rax, rdi
IN0057: 00015A shl eax, 6
IN0058: 00015D add eax, dword ptr [V05 rbp-28H]
G_M42618_IG07: ; offs=000160H, size=0008H, epilog, nogc, emitadd
IN0066: 000160 lea rsp, [rbp-08H]
IN0067: 000164 pop r13
IN0068: 000166 pop rbp
IN0069: 000167 ret
Unwind Info:
>> Start offset : 0x000000 (not in unwind data)
>> End offset : 0x000168 (not in unwind data)
Version : 1
Flags : 0x00
SizeOfProlog : 0x07
CountOfUnwindCodes: 3
FrameRegister : none (0)
FrameOffset : N/A (no FrameRegister) (Value=0)
UnwindCodes :
CodeOffset: 0x07 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 4 * 8 + 8 = 40 = 0x28
CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r13 (13)
CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5)
allocUnwindInfo(pHotCode=0x00007FEC268639F0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x168, unwindSize=0xa, pUnwindBlock=0x000000000140626E, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 14
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x00000029 ( STACK_EMPTY )
IL offs 0x0004 : 0x00000036 ( STACK_EMPTY )
IL offs 0x0034 : 0x000000AB ( STACK_EMPTY )
IL offs 0x003B : 0x000000C7 ( STACK_EMPTY )
IL offs 0x0043 : 0x000000D4 ( STACK_EMPTY )
IL offs 0x0047 : 0x000000DC ( STACK_EMPTY )
IL offs 0x0049 : 0x000000E2 ( STACK_EMPTY )
IL offs 0x0055 : 0x000000F7 ( STACK_EMPTY )
IL offs 0x0059 : 0x00000107 ( STACK_EMPTY )
IL offs 0x005D : 0x0000010D ( STACK_EMPTY )
IL offs 0x0061 : 0x00000120 ( STACK_EMPTY )
IL offs 0x0078 : 0x00000145 ( STACK_EMPTY )
IL offs EPILOG : 0x00000160 ( STACK_EMPTY )
*************** In genSetScopeInfo()
VarLocInfo count is 3
*************** Variable debug info
3 vars
0( UNKNOWN) : From 00000000h to 00000029h, in rdi
1( UNKNOWN) : From 00000000h to 00000029h, in rsi
2( UNKNOWN) : From 00000000h to 00000029h, in rdx
*************** In gcInfoBlockHdrSave()
Set code length to 360.
Set ReturnKind to Scalar.
Set stack base register to rbp.
Set Outgoing stack arg area size to 0.
Defining interruptible range: [0x29, 0x160).
Method code size: 360
Allocations for GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int (MethodHash=cbde5985)
count: 819, size: 72142, max = 2600
allocateMemory: 131072, nraUsed: 74584
Alloc'd bytes by kind:
kind | size | pct
---------------------+------------+--------
AssertionProp | 0 | 0.00%
ASTNode | 19888 | 27.57%
InstDesc | 9128 | 12.65%
ImpStack | 384 | 0.53%
BasicBlock | 2592 | 3.59%
fgArgInfo | 0 | 0.00%
fgArgInfoPtrArr | 0 | 0.00%
FlowList | 256 | 0.35%
TreeStatementList | 0 | 0.00%
SiScope | 216 | 0.30%
FlatFPStateX87 | 0 | 0.00%
DominatorMemory | 0 | 0.00%
LSRA | 3272 | 4.54%
LSRA_Interval | 5360 | 7.43%
LSRA_RefPosition | 9472 | 13.13%
Reachability | 0 | 0.00%
SSA | 0 | 0.00%
ValueNumber | 0 | 0.00%
LvaTable | 1792 | 2.48%
UnwindInfo | 0 | 0.00%
hashBv | 368 | 0.51%
bitset | 288 | 0.40%
FixedBitVect | 24 | 0.03%
Generic | 674 | 0.93%
IndirAssignMap | 0 | 0.00%
FieldSeqStore | 0 | 0.00%
ZeroOffsetFieldMap | 0 | 0.00%
ArrayInfoMap | 0 | 0.00%
MemoryPhiArg | 0 | 0.00%
CSE | 0 | 0.00%
GC | 1328 | 1.84%
CorSig | 0 | 0.00%
Inlining | 128 | 0.18%
ArrayStack | 384 | 0.53%
DebugInfo | 848 | 1.18%
DebugOnly | 14502 | 20.10%
Codegen | 1144 | 1.59%
LoopOpt | 0 | 0.00%
LoopHoist | 0 | 0.00%
Unknown | 94 | 0.13%
RangeCheck | 0 | 0.00%
CopyProp | 0 | 0.00%
SideEffects | 0 | 0.00%
****** DONE compiling GetNthBitOffset:POPCNTAndBMI2Unrolled(long,int,int):int
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