Yosys SB_MAC16 multiply-add test

infer_mac_test.v

`default_nettype none

module infer_mac_test(
    input clk,

    input signed [15:0] pretranslate_x,
    input signed [15:0] pretranslate_y,

    input signed [15:0] translate_x,

    input signed [15:0] a,
    input signed [15:0] b,

    output reg [23:0] out
);
    reg signed [15:0] translate_x_r;

    always @(posedge clk) begin
        translate_x_r <= translate_x;
    end

    always @(posedge clk) begin
        // this seems to infer multiply-add with the extra parens
        // out <= pretranslate_x * a + (pretranslate_y * b + translate_x_r);

        // this doesn't seem to infer multiply-add. only multiply with extra cells spent
        out <= pretranslate_x * a + pretranslate_y * b + translate_x_r;
    end

endmodule