Created
December 1, 2020 06:57
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OpenSTA works (old open_pdks)
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OpenSTA 2.2.0 7662c12482 Copyright (c) 2019, Parallax Software, Inc. | |
License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html> | |
This is free software, and you are free to change and redistribute it | |
under certain conditions; type `show_copying' for details. | |
This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'. | |
Error: cannot open '/.sta'. | |
Warning: /Users/dan.rodrigues/hw/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib, line 31 default_operating_condition ff_n40C_1v95 not found. | |
Warning: /Users/dan.rodrigues/hw/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib, line 32 default_operating_condition ss_100C_1v60 not found. | |
Warning: /project/openlane/vdp_lite_user_proj/runs/01-12_06-53/results/synthesis/vdp_lite_user_proj.synthesis_optimized.v, line 83906 module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for PHY_792. | |
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) | |
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] | |
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)] | |
puts "\[INFO\]: Setting output delay to: $output_delay_value" | |
[INFO]: Setting output delay to: 7.800000000000001 | |
puts "\[INFO\]: Setting input delay to: $input_delay_value" | |
[INFO]: Setting input delay to: 7.800000000000001 | |
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] | |
#set rst_indx [lsearch [all_inputs] [get_port resetn]] | |
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] | |
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] | |
set all_inputs_wo_clk_rst $all_inputs_wo_clk | |
# correct resetn | |
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst | |
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} | |
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] | |
# TODO set this as parameter | |
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] | |
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] | |
puts "\[INFO\]: Setting load to: $cap_load" | |
[INFO]: Setting load to: 0.01765 | |
set_load $cap_load [all_outputs] | |
tns 0.00 | |
wns 0.00 |
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