OpenRAM 1024 x 8 error

gistfile1.txt

|==============================================================================|
|=========                       OpenRAM v1.1.6                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-user-group@ucsc.edu           =========|
|=========        Development help: openram-dev-group@ucsc.edu        =========|
|=========      Temp dir: /tmp/openram_dan.rodrigues_27828_temp/      =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 11/12/2020 18:55:54
Technology: scn4m_subm
Total size: 8192 bits
Word size: 8
Words: 1024
Banks: 1
Write size: None
RW ports: 1
R-only ports: 0
W-only ports: 0
Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing).
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
Only generating nominal corner timing.
Words per row: 16
Output files are: 
/Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.lvs
/Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.sp
/Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.v
/Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.lib
/Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.py
/Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.html
/Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.log
/Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.lef
/Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.gds
** Submodules: 5.8 seconds
** Placement: 0.0 seconds
** Routing: 0.1 seconds
** Verification: 0.0 seconds
** SRAM creation: 5.9 seconds
GDS: Writing to /Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.gds
** GDS: 5.2 seconds
LEF: Writing to /Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.lef
** LEF: 17.0 seconds
SP: Writing to /Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.sp
** Spice writing: 0.4 seconds
LVS: Writing to /Users/dan.rodrigues/hw/OpenRAM/temp/sram_8_1024_scn4m_subm.lvs.sp
** LVS writing: 0.0 seconds
LIB: Characterizing... 
Traceback (most recent call last):
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/openram.py", line 81, in <module>
    s.save()
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/sram/sram.py", line 147, in save
    lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/characterizer/lib.py", line 34, in __init__
    self.characterize_corners()
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/characterizer/lib.py", line 121, in characterize_corners
    self.characterize()
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/characterizer/lib.py", line 128, in characterize
    self.compute_delay()
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/characterizer/lib.py", line 587, in compute_delay
    char_results = self.d.analytical_delay(self.slews,self.loads)
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/characterizer/delay.py", line 1227, in analytical_delay
    power = self.analytical_power(slews, loads)
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/characterizer/delay.py", line 1270, in analytical_power
    power = self.sram.analytical_power(self.corner, load)
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/base/design.py", line 282, in analytical_power
    total_module_power += inst.mod.analytical_power(corner, load)
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/base/design.py", line 282, in analytical_power
    total_module_power += inst.mod.analytical_power(corner, load)
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/base/design.py", line 282, in analytical_power
    total_module_power += inst.mod.analytical_power(corner, load)
  [Previous line repeated 1 more time]
  File "/Users/dan.rodrigues/hw/OpenRAM/compiler/pgates/pnand4.py", line 335, in analytical_power
    power_leak = spice["nand4_leakage"]
KeyError: 'nand4_leakage'

ramdemo.py

# Data word size
word_size = 8
# Number of words in the memory
num_words = 1024

num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0

num_banks = 1

# Technology to use in $OPENRAM_TECH
tech_name = "scn4m_subm"

# You can use the technology nominal corner only
nominal_corner_only = True
# Or you can specify particular corners
# Process corners to characterize
# process_corners = ["SS", "TT", "FF"]
# Voltage corners to characterize
# supply_voltages = [ 3.0, 3.3, 3.5 ]
# Temperature corners to characterize
# temperatures = [ 0, 25 100]

# Output directory for the results
output_path = "temp"
# Output file base name
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

# Disable analytical models for full characterization (WARNING: slow!)
# analytical_delay = False