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EEsim Circuits 2023
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circuit-23.md

Analogue IC Design - Tutorial circuits for EEsim

Simple RC circuit

Basic RC circuit
.include modelcard.CMOS90

r in out 1k
c out 0 1n

vdd vdd 0 3.3

vin in 0 pulse (0 3.3 1u 1n 1n 1u 2u)

.tran  1n 5u

.end

Ids-Vds curve

Basic DC Sweep
.include modelcard.CMOS90

m1 d g 0 0 N90 W=100.0u L=0.09u

Vds d 0 DC 1.8
Vg g 0 DC [0:0.2:1.8]

.dc vds 0 1.8 0.01

.end

Ids-Vds curve (positive)

Basic DC Sweep
.include modelcard.CMOS90

m1 d g 0 0 N90 W=100.0u L=0.09u
v1 d1 d 0

Vds d1 0 DC 1.8
Vg g 0 DC [0:0.2:1.8]

.dc vds 0 1.8 0.01

.end

Ids-Vgs

Basic DC Sweep
.include modelcard.CMOS90

m1 d g 0 0 N90 W=100.0u L=0.09u

Vds d 0 DC [0:0.1:1.8]
Vg g 0 DC 1.8

.dc Vg 0 1.8 0.01

.end

Ids-Vgs sweep parametric

Basic DC Sweep
.include modelcard.CMOS90

m1 d g 0 0 N90 W=100.0u L=0.09u

Vds d 0 DC [0:0.1:1.8]
Vg g 0 DC 1.8

.dc Vg 0 1.8 0.01

.end

Single transistor amp - resistor

Basic amp
.include modelcard.CMOS90

R1 vdd d 1k
M1 d g 0 0 N90 W=1u L=90n


Vdd vdd 0 DC 1.8

Vin g 0 pulse (0.5 0.6 0 1n 1n 150n 300n)

.dc Vin 0 1.8 0.01

.end

Single transistor amp - sweep resistor

Basic amp
.include modelcard.CMOS90

R1 vdd d [1:2:50]k
M1 d g 0 0 N90 W=1u L=90n


Vdd vdd 0 DC 1.8

Vin g 0 pulse (0.5 0.6 0 1n 1n 150n 300n)


.dc Vin 0 1.8 0.01

.end

Single transistor amp - sweep W/L ratio

Basic amp
.include modelcard.CMOS90

R1 vdd d 10k
M1 d g 0 0 N90 W=[0.5:0.5:10]u L=90n


Vdd vdd 0 DC 1.8

Vin g 0 pulse (0.5 0.6 0 1n 1n 150n 300n)

.dc Vin 0 1.8 0.01

.end

Single transistor amp - transient

Basic amp
.include modelcard.CMOS90

R1 vdd d 10k
M1 d g 0 0 N90 W=1u L=90n


Vdd vdd 0 DC 1.8

Vin g 0 pulse (0.5 0.6 0 1n 1n 150n 300n)

*.dc Vin 0 1.8 0.01
.tran 1n 1u

.end

Single transistor amp - sweeping DC bias point

Basic amp
.include modelcard.CMOS90

R1 vdd d 10k
M1 d g 0 0 N90 W=1u L=90n


Vdd vdd 0 DC 1.8

.parameter vq = [0.1:0.1:1]

Vin g 0 pulse ({vq-0.1} {vq+0.1} 0 1n 1n 150n 300n)

*.dc Vin 0 1.8 0.01
.tran 1n 1u
.end

Single transistor amp - sweeping DC bias point

Basic amp
.include modelcard.CMOS90

R1 vdd d 10k
M1 d g 0 0 N90 W=1u L=90n


Vdd vdd 0 DC 1.8

.parameter vq = [0.1:0.1:1]

Vin g 0 pulse ({vq-0.1} {vq+0.1} 0 1n 1n 150n 300n)

*.dc Vin 0 1.8 0.01
.tran 1n 1u
.end

basic amp - CS load

Basic amp - CS
.include modelcard.CMOS90

M1 out in 0 0 N90 W=1u L=90n
M2 out bias vdd vdd P90 W=1u L=90n

Vdd vdd 0 DC 1.8

Vb vdd bias DC [0.6:0.1:1.8]

Vin in 0 1.0

.dc Vin 0 1.8 0.01

.end

basic amp - CS load tran

Basic amp - CS
.include modelcard.CMOS90

M1 out in 0 0 N90 W=1u L=90n
M2 out bias vdd vdd P90 W=1u L=90n

Vdd vdd 0 DC 1.8

Vb vdd bias DC 0.8

Vin in 0 SIN ([0.2:0.01:0.9] 20m 10e6 0)

*.dc Vin 0 1.8 0.01
.tran 1n 1u

.end

basic amp - CS load - vdd var

Basic amp - CS
.include modelcard.CMOS90

M1 out in 0 0 N90 W=1u L=90n
M2 out bias vdd vdd P90 W=1u L=90n

Vdd vdd 0 SIN (1.8 [5:5:100]m 300e6 0)

Vb vdd bias DC 0.8

Vin in 0 SIN (0.6 20m 10e6 0)

*.dc Vin 0 1.8 0.01
.tran 100p 200n

.end

CMOS Inv

CMOS inv
.include modelcard.CMOS90

Mn out in 0 0 N90 W=1u L=90n
Mp out in vdd vdd P90 W=[0.3:0.1:10]u L=90n


Vdd vdd 0 DC 1.8

Vin in 0 pulse (0.8 1.0 0 1n 1n 150n 300n)

.dc Vin 0 1.8 0.001
*.tran 1n 1u

.end

CMOS inv - tran vdd var

CMOS inv - vdd var
.include modelcard.CMOS90

Mn out in 0 0 N90 W=1u L=90n
Mp out in vdd vdd P90 W=2.8u L=90n


Vdd vdd 0 SIN (1.8 [5:5:100]m 300e6 0)

Vin in 0 SIN (0.9 20m 10e6 0)

*.dc Vin 0 1.8 0.001
.tran 100p 200n

.end

source follower

Basic amp - source follower
.include modelcard.CMOS90

M1 vdd in out 0 N90 W=1u L=90n
M2 out bias 0 0 N90 W=1u L=90n

Vdd vdd 0 DC 1.8

Vb bias 0 DC [0.4:0.1:1.8]

Vin in 0 1.0

.dc Vin 0 1.8 0.01

.end

current mirror

simple current mirror - i(in) vs i(out)
.include modelcard.CMOS90

M1 in in 0 0 N90 W=1u L=90n
M2 vdd in 0 0 N90 W=1u L=90n


Iin vdd in 10u

Vdd vdd 0 DC 1.8

.dc Iin 0 10u 0.1u

.options savecurrents

.end

Current Mirror

simple current mirror - i(in) vs v(out)
.include modelcard.CMOS90

M1 in in 0 0 N90 W=1u L=1u
M2 out in 0 0 N90 W=1u L=1u


Iin vdd in [1:1:10]u

Vout out 0 DC 1.0

Vdd vdd 0 DC 1.8

.dc Vout 0 1.8 0.01

.options savecurrents

.end

cascode current mirror

cascode current mirror - i(in) vs i(out)
.include modelcard.CMOS90

*M1 in in 0 0 N90 W=1u L=90n
*M2 out in 0 0 N90 W=1u L=90n
M1 d1 d1 0 0 N90 W=1u L=90n
M2 d2 d1 0 0 N90 W=1u L=90n
M3 in in d1 0 N90 W=1u L=90n
M4 out in d2 0 N90 W=1u L=90n


Iin vdd in 10u

Vdd vdd 0 DC 1.8
Vin out 0 DC 1.8

.dc Iin 0 10u 0.1u

.options savecurrents

.end

Cascode Mirror

cascode current mirror - i(in) vs v(out)
.include modelcard.CMOS90

*M1 in in 0 0 N90 W=1u L=90n
*M2 out in 0 0 N90 W=1u L=90n
M1 d1 d1 0 0 N90 W=1u L=1u
M2 d2 d1 0 0 N90 W=1u L=1u
M3 in in d1 0 N90 W=1u L=1u
M4 out in d2 0 N90 W=1u L=1u


Iin vdd in [1:1:10]u

Vdd vdd 0 DC 1.8
Vout out 0 DC 1.8

*.dc Iin 0 10u 0.1u
.dc Vout 0 1.8 0.01

.options savecurrents

.end

Diff amp - vid vcm sources

Basic amp - diff input
.include modelcard.CMOS90

Vcm cm 0 DC 1
Eidp cm inp d 0 1
Eidn cm inn d 0 -1

Vd d 0 SIN (0 0.1 1MEG)

*.dc Vd -0.1 0.1 0.01
.tran 1n 10u

.end

Diff amp - Vcm sweep

Basic amp - diff Vcm sweep current
.include modelcard.CMOS90

R1 vdd out1 1
R2 vdd out2 1

M1 out1 in1 midp 0 N90 W=1u L=90n
M2 out2 in2 midp 0 N90 W=1u L=90n

Is midp 0 160u

vdd vdd 0 1.8

*diff sources
Vcm cm 0 DC [0.5:0.1:1.5]
Eidp cm in1 diffin 0 1
Eidn cm in2 diffin 0 -1

Vid diffin 0 SIN (0 0.1 1MEG)

.dc Vid -0.5 0.5 0.01

.option savecurrents

.end

Diff amp - Is sweep

Basic amp - diff Is sweep
.include modelcard.CMOS90

R1 vdd out1 10k
R2 vdd out2 10k

M1 out1 in1 midp 0 N90 W=1u L=90n
M2 out2 in2 midp 0 N90 W=1u L=90n

Is midp 0 [10:10:1000]u

vdd vdd 0 1.8

*diff sources
Vcm cm 0 DC 1
Eidp cm in1 diffin 0 1
Eidn cm in2 diffin 0 -1

Vid diffin 0 SIN (0 0.1 1MEG)

.dc Vid -0.5 0.5 0.01

.end

Diff Amp - Vcm sweep

Basic amp - diff Vcm sweep
.include modelcard.CMOS90

R1 vdd out1 10k
R2 vdd out2 10k

M1 out1 in1 midp 0 N90 W=1u L=90n
M2 out2 in2 midp 0 N90 W=1u L=90n

Is midp 0 120u

vdd vdd 0 1.8

*diff sources
Vcm cm 0 DC [0:0.1:1.8]
Eidp cm in1 diffin 0 1
Eidn cm in2 diffin 0 -1

Vid diffin 0 SIN (0 0.1 1MEG)

.tran 1n 5u

*plot vin1 vin2 vo1 vo2

.end

Diff Amp - Current Mirror Load

Basic amp - diff Vcm mosfet source
.include modelcard.CMOS90

M3 out1 out1 vdd vdd P90 W=1u L=90n
M4 out2 out1 vdd vdd P90 W=1u L=90n

M1 out1 in1 midp 0 N90 W=1u L=90n
M2 out2 in2 midp 0 N90 W=1u L=90n

*Is midp 0 50u
M5 midp bias temp 0 N90 W=1u L=90n

Rtemp temp 0 1
vbias bias 0 DC 0.52

vdd vdd 0 1.8

*diff sources
Vcm cm 0 DC [0.8:0.1:1.5]
Eidp cm in1 diffin 0 1
Eidn cm in2 diffin 0 -1

Vid diffin 0 SIN (0 0.01 1MEG)

.dc Vid -0.5 0.5 0.001
*.tran 1n 10u

*.options savecurrents

.end

Diff Amp - Current Source Load

Basic amp - diff Vcm mosfet source
.include modelcard.CMOS90

M3 out1 biasp vdd vdd P90 W=1u L=90n
M4 out2 biasp vdd vdd P90 W=1u L=90n

M1 out1 in1 midp 0 N90 W=1u L=90n
M2 out2 in2 midp 0 N90 W=1u L=90n

*Is midp 0 50u
M5 midp bias temp 0 N90 W=1u L=90n

Rtemp temp 0 1
vbias bias 0 DC 0.52
vbiasp vdd biasp DC [0.4:0.01:0.7]

vdd vdd 0 1.8

*diff sources
Vcm cm 0 DC 1.0
Eidp cm in1 diffin 0 1
Eidn cm in2 diffin 0 -1

Vid diffin 0 SIN (0 0.01 1MEG)

.dc Vid -0.5 0.5 0.001
*.tran 1n 10u

*.options savecurrents

.end

Diff Amp - Current Source Load #2

Basic amp - diff Vcm mosfet source
.include modelcard.CMOS90

M3 out1 biasp vdd vdd P90 W=1u L=90n
M4 out2 biasp vdd vdd P90 W=1u L=90n

M1 out1 in1 midp 0 N90 W=1u L=90n
M2 out2 in2 midp 0 N90 W=1u L=90n

*Is midp 0 50u
M5 midp bias temp 0 N90 W=1u L=90n

Rtemp temp 0 1
vbias bias 0 DC 0.52
vbiasp vdd biasp DC 0.56

vdd vdd 0 1.8

*diff sources
Vcm cm 0 DC [0.5:0.1:1.5]
Eidp cm in1 diffin 0 1
Eidn cm in2 diffin 0 -1

Vid diffin 0 SIN (0 0.01 1MEG)

.dc Vid -0.5 0.5 0.001
*.tran 1n 10u

*.options savecurrents

.end
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