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danielholanda / quickDraw.v
Created November 21, 2018 02:05
LeFlow - Quick Draw Verilog File
`define MEMORY_CONTROLLER_ADDR_SIZE 64
`define MEMORY_CONTROLLER_DATA_SIZE 64
// Number of RAM elements: 16
`define MEMORY_CONTROLLER_TAG_SIZE 9
// @param0 = internal global [5 x [5 x [1 x [8 x float]]]] zeroinitializer, align 8
`define TAG_g_param0 `MEMORY_CONTROLLER_TAG_SIZE'd17
`define TAG_g_param0_a {`TAG_g_param0, 55'd0}
// @param1 = internal global [1 x [28 x [28 x [1 x float]]]] zeroinitializer, align 8
`define TAG_g_param1 `MEMORY_CONTROLLER_TAG_SIZE'd16
`define TAG_g_param1_a {`TAG_g_param1, 55'd0}