AD9361 overclock snippet

ad9361_overclock.c

/// Rx Enable and Filter Control register:
/// - Rx Enable = 1
/// The ad9361_en_dis_rx function sets this bit. This bit
/// determines if the receiver is enabled. Setting the bit enables the
/// receiver signal path. Clearing the bit disables the receiver.
/// - RHB3 Enable and Decimation[1:0] = 0b01
/// See note in 0x002[D5:D4]. These bits set the decimation of the
/// first filtering stage after the ADC per Table 4.
/// 00 Decimate by 1, no filtering
/// 01 Decimate by 2 (half-band filter)
/// 10 Decimate by 3 and filter
/// 11 Invalid
/// - RHB2 Enable = 0
/// See note in 0x002[D5:D4]. Setting this bit enables the decimate-
/// by-2 RHB2 half-band filter. Clearing this bit bypasses the filter.
/// - RHB1 Enable = 1
/// See note in 0x002[D5:D4]. Setting this bit enables the decimate-
/// by-2 RHB1 half-band filter. Clearing this bit bypasses the filter.
/// - Rx FIR Enable and Decimation[1:0] = 0b00
/// See note at 0x002[D5:D4]. These two bits control the
/// programmable Rx FIR filter per Table 5.
/// 00 Decimate by 1 and bypass filter
/// 01 Decimate by 1 and enable filter
/// 10 Decimate by 2 and enable filter
/// 11 Decimate by 4 and enable filter
bladerf_set_rfic_register(state->dev,0x003,0x54); // OC Register

/* TX Register Assignments */
/// Tx Enable and Filter Control register:
/// - Open = 1 ??
/// - Tx Enable = 1
/// The ad9361_en_dis_tx function sets this bit. This bit
/// determines if the the transmitter is enabled. Setting the bit
/// enables the transmitter signal path. Clearing the bit disables the
/// transmitter.
/// - THB3 Enable and Interp[1:0] = 0b00
/// Note that there are several functions that calculate digital filter
/// settings. The ad9361_calculate_rf_clock_chain function
/// calculates all Rx and Tx rates.
/// These bits set interpolation of the digital filter that feeds the
/// DAC per Table 2.
/// 00 Interpolate by 1, no filtering
/// 01 Interpolate by 2 (half-band filter)
/// 10 Interpolate by 3 and filter
/// 11 Invalid
/// - THB2 Enable = 0
/// See note in Bits[D5:D4] section. Setting this bit enables the
/// interpolate-by-2 THB2 half-band filter. Clearing this bit
/// bypasses the filter.
/// - THB1 Enable = 0
/// See note in Bits[D5:D4] section. Setting this bit enables the
/// interpolate-by-2 THB2 half-band filter. Clearing this bit
/// bypasses the filter.
/// - Tx FIR Enable and Interpolation[1:0] = 0b00
/// See note at 0x002[D5:D4]. These two bits control the
/// programmable Rx FIR filter per Table 5.
/// 00 Interpolate by 1 and bypass filter
/// 01 Interpolate by 1 and enable filter
/// 10 Interpolate by 2 and enable filter
/// 11 Interpolate by 4 and enable filter
bladerf_set_rfic_register(dev,0x02,0xc0);  // TX Enable and Filter Control
/// Tx BBF R1
/// - Override Enable = 1
/// Setting this bit forces the baseband filter to use the values
/// written into Register 0x0C2 through Register 0x0CB.
/// - R1[4:0] = 0x1f
/// Tx baseband filter R1 word
bladerf_set_rfic_register(state->dev,0xc2,0x9f);  // TX BBF R1
/// - R2[4:0] = 0x1f
/// Tx baseband filter R2 through R4 words.
bladerf_set_rfic_register(state->dev,0xc3,0x9f);  // TX baseband filter R2
/// - R3[4:0] = 0x1f
bladerf_set_rfic_register(state->dev,0xc4,0x9f);  // TX baseband filter R3
/// - R4[4:0] = 0x1f
bladerf_set_rfic_register(state->dev,0xc5,0x9f);  // TX baseband filter R4
/// - RP[4:0] = 0x1f
/// Tx baseband filter real pole word.
bladerf_set_rfic_register(state->dev,0xc6,0x9f);  // TX baseband filter real pole word
/// - C1[5:0] = 0x0
/// Tx baseband filter C1 and C2 words.
bladerf_set_rfic_register(state->dev,0xc7,0x00);  // TX baseband filter C1
/// - C2[5:0] = 0x0
/// Tx baseband filter C1 and C2 words.
bladerf_set_rfic_register(state->dev,0xc8,0x00);  // TX baseband filter C2
/// - CP[5:0] = 0x0
/// Tx baseband filter real pole word.
bladerf_set_rfic_register(state->dev,0xc9,0x00);  // TX baseband filter real pole word

/* RX Register Assignments */
/// Gain and calibration
/// BBF R1A
/// - Force resistors = 1
/// Test bit; should be normally cleared. Setting this bit forces the
/// use of the resistor register values.
/// - BBF R1A[5:0] = 0x3f
/// This register in combination with R4 (Register 0x1E6) sets the
/// bi-quad signal gain (R4/R1A = Av).
bladerf_set_rfic_register(state->dev,0x1e0,0xBF);
/// - Rx BBF R5[7:0] = 0xff
/// This register along with R6 (Register 0x1E6) controls the pole
/// signal gain (R6/F5 = Av). If this register is nonzero, Register
/// 0x1F2 must be zero.
bladerf_set_rfic_register(state->dev,0x1e4,0xFF);
/// - Rx BBF R5 Tune[7:0] = 0xff
/// This register along with the value of R6 (Register 0x1E6) sets
/// the pole signal gain during calibration. If this is nonzero,
/// Register 0x1E4 and Register 0x1E5 must be all zeros.
bladerf_set_rfic_register(state->dev,0x1f2,0xFF);
/// Rx BBF R2346
/// - Tune override = 1
/// Normally clear. Setting this bit overrides the calibration values,
/// forcing the filter to use the R2346 value and all capacitor words
/// - Rx BBF R2346[2:0] = 0x7
/// These bits control the value of Resistors R2, R3, R4, and R6.
// bladerf_set_rfic_register(state->dev,0x1e6,0x87); // Causes gr-osmosdr to freak out

// Miller and BBF caps
/// - Rx BBF C1 MSB[5:0] = 0x00
/// These bits affect the C1 and C2 BBF capacitors. Typically, both
/// registers, along with Register 0x1EB, should use the same word
bladerf_set_rfic_register(state->dev,0x1e7,0x00);
/// - Rx BBF C1 LSB[6:0] = 0x00
/// These bits affect the C1 and C2 BBF capacitors. Typically,
/// both registers, along with Register 0x1EC, should use the same
/// word.
bladerf_set_rfic_register(state->dev,0x1e8,0x00);
/// - Rx BBF C2 MSB[5:0] = 0x00
bladerf_set_rfic_register(state->dev,0x1e9,0x00);
/// - Rx BBF C2 LSB[6:0] = 0x00
bladerf_set_rfic_register(state->dev,0x1ea,0x00);
/// - Rx BBF C3 MSB[5:0] = 0x00
/// These bits affect the C3 BBF capacitor. Typically equal to
/// Register 0x1E7 and Register 0x1E9.
bladerf_set_rfic_register(state->dev,0x1eb,0x00);
/// - Rx BBF C3 LSB[6:0] = 0x00
/// These bits affect the C3 BBF capacitor. Typically equal to 0x1E8
/// and 0x1EA.
bladerf_set_rfic_register(state->dev,0x1ec,0x00);
/// - Rx BBF CC1 Ctr[6:0] = 0x00
/// These bits control the Miller compensation capacitor for Op
/// Amp 1.
bladerf_set_rfic_register(state->dev,0x1ed,0x00);
/// - Must be 0x60 ??
bladerf_set_rfic_register(state->dev,0x1ee,0x00);
/// - Rx BBF CC2 Ctr[6:0] = 0x00
bladerf_set_rfic_register(state->dev,0x1ef,0x00);
/// Same as Register 0x1ED but applies to Op Amp2.
/// This is set again to the same value (see above)
bladerf_set_rfic_register(state->dev,0x1e0,0xBF);

// BIST and Data Port Test Config [D1:D0] "Must be 2’b00"
/// - BIST Mask Q data = 0
/// - BIST Mask I data = 0
/// - Must be 2'b00 = 0b11 ??
bladerf_set_rfic_register(state->dev,0x3f6,0x03);