OpenOCD - Fetch SRAM and process for OTA URLs

fetch.sh

#!/bin/bash -e
#
# OpenOCD should be run via:
#
#   openocd -f 2232H.cfg -f stm32f1x.cfg
#

# Spawn an instance of OpenOCD.
openocd -f 2232H.cfg -f stm32f1x.cfg &> /dev/null &
OPENOCD_PID=$!

# Give OpenOCD a moment.
sleep 0.1

# Dump SRAM, convert to binary.
echo -e 'mdw 0x20000000 0x4000\nexit' | \
  nc 127.0.0.1 4444 2>&1 | \
  egrep -ai '^0x[0-9A-Z]+: ' | \
  cut -d : -f 2 | \
  tr -d ' ' | \
  tr -d '\n' | \
  xxd -r -p > in

# Swap endian-ness
objcopy -I binary -O binary --reverse-bytes=4 in

# Look for URLs.
egrep -aoi 'https?://[a-zA-Z0-9\.\-\/\_]+' in

# Kill OpenOCD.
kill $OPENOCD_PID

FT2232H.cfg

#
# FTDI MiniModule
#
# http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf
#

interface ftdi
ftdi_device_desc "FT2232H MiniModule"
ftdi_vid_pid 0x0403 0x6010
transport select swd

ftdi_layout_init 0x0018 0x05fb
ftdi_layout_signal SWD_EN -data 0
ftdi_layout_signal nSRST -data 0x0020

Notes.md

Notes

Ensure the appropriate 470 Ohm resistor has been applied betwen TDI and SWDIO per:

• https://github.com/arduino/OpenOCD/blob/master/tcl/interface/ftdi/swd-resistor-hack.cfg

stm32f1x.cfg

# script for stm32f1x family

#
# stm32 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME stm32f1x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 4kB (as found on some STM32F100s)
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1000
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   if { [using_jtag] } {
      # See STM Document RM0008 Section 26.6.3
      set _CPUTAPID 0x3ba00477
   } {
      # this is the SW-DP tap id not the jtag tap id
      set _CPUTAPID 0x1ba01477
   }
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

if {[using_jtag]} {
   jtag newtap $_CHIPNAME bs -irlen 5
}

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME

# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
adapter_khz 1000

adapter_nsrst_delay 100
if {[using_jtag]} {
 jtag_ntrst_delay 100
}

reset_config srst_nogate

if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
	mmw 0xE0042004 0x00000307 0
}

$_TARGETNAME configure -event trace-config {
	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
	# change this value accordingly to configure trace pins
	# assignment
	mmw 0xE0042004 0x00000020 0
}