daveshah1

import re, sys

extras = {
	("ddram", "dm"): [("IOStandard", "POD12_DCI")],
	("ddram", "dq"): [
		("IOStandard", "POD12_DCI"),
		("Misc", "PRE_EMPHASIS=RDRV_240"),
		("Misc", "EQUALIZATION=EQ_LEVEL2"),
	],
	("ddram", "dqs_p"): [

daveshah1

#!/usr/bin/env bash
set -ex
cp soc_ethernetsoc_arty/gateware/*.init .
yosys -p "scratchpad -set xilinx_dsp.multonly 1; synth_xilinx -noclkbuf -nowidelut -flatten -top top; write_json litex.json" `grep -Po '(?<=read_verilog {)[^}]*' soc_ethernetsoc_arty/gateware/top.tcl` `grep -Po '(?<=read_verilog )[^ ]*$' soc_ethernetsoc_arty/gateware/top.ys`
nextpnr-xilinx --chipdb ../../nextpnr-xilinx/xilinx/xc7a35t.bin --xdc soc_ethernetsoc_arty/gateware/top.xdc --json litex.json --write litex_routed.json --fasm litex.fasm
source ${XRAY_DIR}/utils/environment.sh
${XRAY_UTILS_DIR}/fasm2frames.py --part xc7a35tcsg324-1 --db-root ${XRAY_UTILS_DIR}/../database/artix7 litex.fasm > litex.frames
${XRAY_TOOLS_DIR}/xc7frames2bit --part_file ${XRAY_UTILS_DIR}/../database/artix7/xc7a35tcsg324-1.yaml --part_name xc7a35tcsg324-1  --frm_file litex.frames --output_file litex.bit

daveshah1

// Harris

block harris(clock<rising,126e6>, enable, unsigned<6>[3] input) => (unsigned<6>[3] output) {
  /*convert image to greyscale*/
  stream2d<unsigned<6>, 7, 7, 1024> greyscale;
  greyscale << ((input[0] + input[1] + input[2]) / 3);
  /*obtain x and y derivatives*/
  /*signed<7>[5][5] mx = {{0, 1, 0, -1, 0},
                        {2, 20, 0, -20, -2},
                        {5, 55, 0, -55, -5},

daveshah1

import codecs, sys

# Simple parser for Intel pinout files
# ./extract_pinout.py 10m08da.txt

# Prints a list of bidirectional, non-JTAG, IO pins

delim = "\t"
device_prefix = '"Pin Information for the '

daveshah1

/* Generated by Yosys 0.8+612 (git sha1 a66f17b, clang 3.8.0-2ubuntu4 -fPIC -Os) */

module \$verific$nand_64 (a, b, o);
  wire \$verific$i1$9689 ;
  wire \$verific$i10$9716 ;
  wire \$verific$i11$9719 ;
  wire \$verific$i12$9722 ;
  wire \$verific$i13$9725 ;
  wire \$verific$i14$9728 ;
  wire \$verific$i15$9731 ;

daveshah1

#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <stdint.h>

// FIXME: This will break once we have a real MMU ;)

volatile uint32_t *gpio = (uint32_t*)0xe000f000; //FIXME

#define CRESET 1U

daveshah1

#!/usr/bin/env bash
set -ex
ECP5=/usr/local/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u
TOP=dqsbuf_tb
iverilog -s $TOP -o $TOP -Dmixed_hdl $ECP5/DQSBUFM.v $ECP5/IDDRX2DQA.v tb.v
vvp $TOP

daveshah1

PROJ=demo
CONSTR=versa.lpf

all: ${PROJ}.bit

%.json: %.v
	yosys -p "synth_ecp5 -nomux -json $@" $<

TRELLIS=/home/david/prjtrellis

daveshah1

#require 'vagrant-auto_network'

$script = <<SCRIPT
echo Fetching Yosys - synthesis...
curl -s -S https://rqou.com/jenkins/job/open-fpga-tools/job/yosys-linux-x86_64/lastSuccessfulBuild/artifact/yosys-master.tar.xz > yosys-master.tar.xz  && echo 'Success!'
echo 'Fetching icestorm - database and utilities...'
curl -s -S https://rqou.com/jenkins/job/open-fpga-tools/job/icestorm-linux-x86_64/lastSuccessfulBuild/artifact/icestorm-master.tar.xz > icestorm-master.tar.xz && echo 'Success!'
echo 'Fetching arachne-pnr - place & route...'
curl -s -S https://rqou.com/jenkins/job/open-fpga-tools/job/arachne-pnr-linux-x86_64/lastSuccessfulBuild/artifact/arachne-pnr-master.tar.xz > arachne-pnr-master.tar.xz && echo 'Success!'
echo 'Extracting and Installing Tools...'

daveshah1

#!/usr/bin/env python3
import sys, os, re

# Compare the output of a Lattice `bstool` dump  with ecpunpack and note discrepancies

if len(sys.argv) < 3:
    print("Usage: compare_bits.py lattice_dump.txt ecpunpack.out")
    sys.exit(2)

ecpup_re = re.compile(r'\((\d+), (\d+)\)')