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@daveshah1
daveshah1 / ecc.c
Created November 28, 2019 20:00
elasticc examples
// Harris
block harris(clock<rising,126e6>, enable, unsigned<6>[3] input) => (unsigned<6>[3] output) {
/*convert image to greyscale*/
stream2d<unsigned<6>, 7, 7, 1024> greyscale;
greyscale << ((input[0] + input[1] + input[2]) / 3);
/*obtain x and y derivatives*/
/*signed<7>[5][5] mx = {{0, 1, 0, -1, 0},
{2, 20, 0, -20, -2},
{5, 55, 0, -55, -5},
#!/usr/bin/env bash
set -ex
cp soc_ethernetsoc_arty/gateware/*.init .
yosys -p "scratchpad -set xilinx_dsp.multonly 1; synth_xilinx -noclkbuf -nowidelut -flatten -top top; write_json litex.json" `grep -Po '(?<=read_verilog {)[^}]*' soc_ethernetsoc_arty/gateware/top.tcl` `grep -Po '(?<=read_verilog )[^ ]*$' soc_ethernetsoc_arty/gateware/top.ys`
nextpnr-xilinx --chipdb ../../nextpnr-xilinx/xilinx/xc7a35t.bin --xdc soc_ethernetsoc_arty/gateware/top.xdc --json litex.json --write litex_routed.json --fasm litex.fasm
source ${XRAY_DIR}/utils/environment.sh
${XRAY_UTILS_DIR}/fasm2frames.py --part xc7a35tcsg324-1 --db-root ${XRAY_UTILS_DIR}/../database/artix7 litex.fasm > litex.frames
${XRAY_TOOLS_DIR}/xc7frames2bit --part_file ${XRAY_UTILS_DIR}/../database/artix7/xc7a35tcsg324-1.yaml --part_name xc7a35tcsg324-1 --frm_file litex.frames --output_file litex.bit
@daveshah1
daveshah1 / extract_pins.py
Created April 25, 2020 07:17
Xilinx XDC --> LiteX board file
import re, sys
extras = {
("ddram", "dm"): [("IOStandard", "POD12_DCI")],
("ddram", "dq"): [
("IOStandard", "POD12_DCI"),
("Misc", "PRE_EMPHASIS=RDRV_240"),
("Misc", "EQUALIZATION=EQ_LEVEL2"),
],
("ddram", "dqs_p"): [