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@daveshah1
daveshah1 / xz-premium.dts
Created May 27, 2017 09:47
XZ Premium Extracted DTS
/dts-v1/;
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "SoMC Maple-ROW(MSM8998 v2.1)";
compatible = "somc,maple-row", "qcom,msm8998";
qcom,msm-id = <0x124 0x20001>;
interrupt-parent = <0x1>;
qcom,board-id = <0x8 0x0>;
[options]
mode prove
depth 50
[engines]
abc pdr
[script]
read_verilog -formal lfsr_equiv.v lfsr_fib.v lfsr_gal.v
prep -top lfsr_equiv -nordff
@daveshah1
daveshah1 / vtbin2nes.py
Created February 2, 2018 18:59
VTxx BIN to NES 2.0 converter
#!/usr/bin/env python3
import os, sys
import argparse
def main():
parser = argparse.ArgumentParser(description='Convert VTxx BIN format to NES 2.0 format')
parser.add_argument('infile', metavar='infile', type=str, nargs=1,
help='Input .bin file')
parser.add_argument('-m', '--mapper', action='store', default=256,
help='NES 2.0 mapper number (default: 256)')
@daveshah1
daveshah1 / compare.py
Created March 12, 2018 21:12
ECP5 bitstream analysis tools
#!/usr/bin/env python3
import sys, os, re
# Compare the output of a Lattice `bstool` dump with ecpunpack and note discrepancies
if len(sys.argv) < 3:
print("Usage: compare_bits.py lattice_dump.txt ecpunpack.out")
sys.exit(2)
ecpup_re = re.compile(r'\((\d+), (\d+)\)')
@daveshah1
daveshah1 / Vagrantfile
Created March 26, 2018 09:13
icestorm Vagrantfile
#require 'vagrant-auto_network'
$script = <<SCRIPT
echo Fetching Yosys - synthesis...
curl -s -S https://rqou.com/jenkins/job/open-fpga-tools/job/yosys-linux-x86_64/lastSuccessfulBuild/artifact/yosys-master.tar.xz > yosys-master.tar.xz && echo 'Success!'
echo 'Fetching icestorm - database and utilities...'
curl -s -S https://rqou.com/jenkins/job/open-fpga-tools/job/icestorm-linux-x86_64/lastSuccessfulBuild/artifact/icestorm-master.tar.xz > icestorm-master.tar.xz && echo 'Success!'
echo 'Fetching arachne-pnr - place & route...'
curl -s -S https://rqou.com/jenkins/job/open-fpga-tools/job/arachne-pnr-linux-x86_64/lastSuccessfulBuild/artifact/arachne-pnr-master.tar.xz > arachne-pnr-master.tar.xz && echo 'Success!'
echo 'Extracting and Installing Tools...'
@daveshah1
daveshah1 / Makefile
Created November 7, 2018 15:00
ECP5 serdes testing
PROJ=demo
CONSTR=versa.lpf
all: ${PROJ}.bit
%.json: %.v
yosys -p "synth_ecp5 -nomux -json $@" $<
TRELLIS=/home/david/prjtrellis
@daveshah1
daveshah1 / sim.sh
Last active July 15, 2020 09:39
testbench for DQSBUFM
#!/usr/bin/env bash
set -ex
ECP5=/usr/local/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u
TOP=dqsbuf_tb
iverilog -s $TOP -o $TOP -Dmixed_hdl $ECP5/DQSBUFM.v $ECP5/IDDRX2DQA.v tb.v
vvp $TOP
@daveshah1
daveshah1 / icebang.c
Created March 20, 2019 18:44
Simple bitbang iCE40 programmer
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <stdint.h>
// FIXME: This will break once we have a real MMU ;)
volatile uint32_t *gpio = (uint32_t*)0xe000f000; //FIXME
#define CRESET 1U
@daveshah1
daveshah1 / microwatt_core.sv
Created August 22, 2019 16:45
Machine translation to Verilog of microwatt OpenPOWER core (https://github.com/antonblanchard/microwatt/blob/master/core.vhdl 5a29cb4) using Yosys+Verific
This file has been truncated, but you can view the full file.
/* Generated by Yosys 0.8+612 (git sha1 a66f17b, clang 3.8.0-2ubuntu4 -fPIC -Os) */
module \$verific$nand_64 (a, b, o);
wire \$verific$i1$9689 ;
wire \$verific$i10$9716 ;
wire \$verific$i11$9719 ;
wire \$verific$i12$9722 ;
wire \$verific$i13$9725 ;
wire \$verific$i14$9728 ;
wire \$verific$i15$9731 ;
@daveshah1
daveshah1 / extract_pinout.py
Created September 17, 2019 21:30
Intel FPGA pinout parser
import codecs, sys
# Simple parser for Intel pinout files
# ./extract_pinout.py 10m08da.txt
# Prints a list of bidirectional, non-JTAG, IO pins
delim = "\t"
device_prefix = '"Pin Information for the '