codigo para procesador con ram de doble puerto como componente

lps.VHD

-- Unidad de sistema de lectura, procesamiento y salida de datos
-- de forma simultanea


library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;


entity lps is
generic (k : unsigned (7 downto 0) := "00111001");
    Port ( data_in : in  unsigned(7 downto 0);
           clkg : in  STD_LOGIC;
           data_out : out  unsigned(15 DOWNTO 0));
end lps;

architecture Behavioral of lps is
SIGNAL q_a, q_b : unsigned(7 DOWNTO 0):="00000000";
SIGNAL addr_a : integer range 0 to 63 :=0;
SIGNAL addr_b : integer range 0 to 63 :=0;
SIGNAL dir_a, dir_b : UNSIGNED(5 downto 0) := "000000";


COMPONENT dualportram
PORT (
	  data_a : in  unsigned(7 downto 0);
           data_b : in  unsigned(7 downto 0);
           addr_a : in integer range 0 to 63 :=0;
           addr_b : in integer range 0 to 63 :=0;
           en_a : in  STD_LOGIC ;
           en_b : in  STD_LOGIC ;
           we_a : in  STD_LOGIC ;
           we_b : in  STD_LOGIC ;
           clk : in  STD_LOGIC;
           q_a : out  unsigned(7 downto 0);
           q_b : out  unsigned(7 downto 0));

END COMPONENT;


begin


--instanciacion de dualportram
dpr: dualportram
port map(
	data_a => data_in,
	data_b => "00110010",
	addr_a => addr_a,
	addr_b => addr_b,
	en_a => '1',
	en_b => '1',
	we_a => '1',
	we_b=> '0',
	clk => clkg,
	q_a => q_a,
	q_b => q_b);


-- funcionamiento del sistema top level
PROCESS(clkg, addr_a, addr_b)
VARIABLE i : integer := 0;
BEGIN
if (rising_edge(clkg)) then
dir_a <= to_unsigned(addr_a, 6);
dir_a <= dir_a + i;
addr_a <= to_integer(dir_a);
dir_b <= to_unsigned(addr_b, 6);
dir_b <= dir_b + (i - 16);
if(dir_b < "000000") then
dir_b <= "111111";
end if;
addr_b <=to_integer(dir_b);
data_out <= q_b*k;
i := i + 1;
end if;
end process;	


			
end Behavioral;

lps_tb.VHD

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   00:22:24 04/01/2014
-- Design Name:   
-- Module Name:   F:/DSP/dsp GUIA 4/lps/lps_tb.vhd
-- Project Name:  lps
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: lps
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY lps_tb IS
END lps_tb;
 
ARCHITECTURE behavior OF lps_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT lps
    PORT(
         data_in : IN  std_logic_vector(7 downto 0);
         clkg : IN  std_logic := '0';
         data_out : OUT  std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal data_in : std_logic_vector(7 downto 0) := (others => '0');
   signal clkg : std_logic := '0';

 	--Outputs
   signal data_out : std_logic_vector(15 downto 0);

    
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: lps PORT MAP (
          data_in => data_in,
          clkg => clkg,
          data_out => data_out
        );

   -- Clock process definitions
   		clkg <= not clkg AFTER 10 ns;
 

			data_in <= "00010011" AFTER 100 ns, "00100110" AFTER 200 ns, "00011100" AFTER 300 ns,
							"0011110011" AFTER 400 ns, "00101010" AFTER 500 ns, "01010101" AFTER 600 ns,
							"00111110" AFTER 700 ns, "00111001" AFTER 800 ns, "00111001" AFTER 900 ns,
							"01110011" AFTER 1000 ns;
							
END;