davilamds

module uart_test
   (
    input wire clk, reset,
    input wire rx,
    input wire [2:0] btn,
    output wire tx
   );

   // declaración de señales
   wire tx_full, rx_empty, btn_tick;

davilamds

module uart
  #( // Seteo por defecto:
    // 19,200 baud, 8 bits de datos, 1 bit de stop (8N1), 2^2 FIFO
      parameter DBIT = 8,     // # bits de datos
                SB_TICK = 16, // # pulsos 16/24/32
                              // para 1/1.5/2 bits de stop
                DVSR = 163,   // divisor de baud rate
                              // DVSR = 50M/(16*baud rate)
                DVSR_BIT = 8, // # bits de DVSR
                FIFO_W = 2    // # bits de dirección del FIFO

davilamds

module uart_tx
   #(
     parameter DBIT = 8,     // # bits de datos
               SB_TICK = 16  // # ticks para bits de parada
   )
   (
    input wire clk, reset,
    input wire tx_start, s_tick,
    input wire [7:0] din,
    output reg tx_done_tick,

davilamds

module uart_rx
   #(
     parameter DBIT = 8,     // # bits de datos
               SB_TICK = 16  // # ticks para bits de stop
   )
   (
    input wire clk, reset,
    input wire rx, s_tick,
    output reg rx_done_tick,
    output wire [7:0] dout

davilamds

module mod_m_counter
   #(
    parameter N=8, // número de bits en el contador
              M=163 // mod-M
   )
   (
    input wire clk, reset,
    output wire max_tick,
    output wire [N-1:0] q
   );

davilamds

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_test is
   port(
      clk, reset: in std_logic;
      btn: std_logic_vector(2 downto 0);
      rx: in std_logic;
      tx: out std_logic
   );

davilamds

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
   generic(
     -- Seteo por defecto:
     -- 19,200 baud, 8 bis de datos, 1 bit de stop (8N1), 2^2 FIFO 
     DBIT: integer:=8;     -- # bits de datos
      SB_TICK: integer:=16; -- # pulsos 16/24/32
                            --   para 1/1.5/2 bits de stop

davilamds

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_tx is
   generic(
      DBIT: integer:=8;     -- # bits de datos(8 bits)
      SB_TICK: integer:=16  -- # ticks para bit de parada (1 bit)
   );
   port(
      clk, reset: in std_logic;

davilamds

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mod_m_counter is
   generic(
      N: integer := 8;     -- numero de bits
      M: integer := 163     -- numero de modulo
  );
   port(
      clk, reset: in std_logic;

davilamds

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rx is
   generic(
      DBIT: integer:=8;     -- # bits de datos (8 bits)
      SB_TICK: integer:=16  -- # ticks para bits de stop (1 bit)
   );
   port(
      clk, reset: in std_logic;