davilamds

library ieee;
use ieee.std_logic_1164.all;
entity decoder_2_4 is
	port(
		a: in std_logic_vector(1 downto 0);
		en: in std_logic;
		y: out std_logic_vector(3 downto 0)
	);
end decoder_2_4;

davilamds

library ieee;
use ieee.std_logic_1164.all;
entity decoder_2_4_if is
	port(
		a: in std_logic_vector (1 downto 0);
		en: in std_logic;
		y: out std_logic_vector (3 downto 0)
	);
end decoder_2_4_if;

davilamds

library ieee;
use ieee.std_logic_1164.all;
entity decoder_2_4_case is
	port(
		a: in std_logic_vector (1 downto 0);
		en: in std_logic;
		y: out std_logic_vector (3 downto 0)
	);
end decoder_2_4_case;

davilamds

module eq1
(
	//declaración de entradas y salidas
	input wire i0, i1;
	output wire eq
);
	//declaración de señales internas
	wire p0, p1;

	//comportamiento del módulo

davilamds

module eq2
  (
    input wire [1:0] a,b,
    output wire aeqb
  );
  
  //señales internas
  wire e0, e1
  
  //instanciar dos comparadores de 1 bit

davilamds

'timescale 1ns/10ps // unidad de simulación 1ns con pasos de 10ps

module eq2_testbench;
  //declaración de señales
  reg [1:0] test_in0, test_in1;
  wire test_out;
  // instanciar el circuito que se va a simular
  eq2 uut
  (
    .a(test_in0), .b(test_in1), .aeqb(test_out)

davilamds

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binto7seg is
	port(a0,a1,a2,a3: in std_logic;A,B,C,D,E,F,G: out std_logic);
end binto7seg;
architecture Behavioral of binto7seg is
	signal s: std_logic_vector(3 downto 0);
begin
	s<=a3&a2&a1&a0;
	process (s)

davilamds

module decoder_2_4_if
  (
    input wire [1:0] a,
    input wire en,
    output reg [3:0] y
  );
  always @*
    if (en==1'b0)
      y = 4'b0000;
  else if (a==2'b00)

davilamds

module decoder_2_4_case
	(
		input wire [1:0] a,
		input wire en,
		output reg [3:0] y
	);

	always @*
		case ({en, a})
			3'b000, 3'b001, 3'b010, 3'b011: y = 4'b0000;

davilamds

module adder_carry_hard(

	input  wire [3:0] a, b,
	output wire [3:0] sum,
	output wire cout
    );
	 //declaracion de señales
	 wire[4:0] sum_ext;
	 
	 //cuerpo del módulo