fpga reverse memory

gistfile1.coq

module trigger(clk, rxReady, rxData, txBusy, txStart, txData, memAddr, memWriteEnable, memWrite, memRead);
input clk;
input [7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
output reg[24:0] memWrite;
output reg[9:0] memAddr;
output reg memWriteEnable;
input [24:0] memRead;

integer countIO;
reg[24:0] data[0:24];



integer read=0, solving=1, write1=2, write2=3;
integer state;

initial begin
	txStart <= 0;
	state <= read;
end

always @(posedge clk) begin
	integer i, m, next;
	i = countIO/4;
	m = countIO%4;
	next = (countIO + 1) % 100;
	txStart <= 0;
	memWriteEnable <= 0;
	case (state)
		read: begin
			data[i][m*8+7 -:8] <= rxData;
			if (rxReady) begin
				countIO <= next;
				if (next == 0) state <= solving;
			end end
		solving: begin
			integer i2, m2, k, i2a;
			k = 20;
			countIO <= countIO + 1;
			i2 = countIO/k;
			m2 = countIO%k;
			i2a = i2 - 25;
			if (i2 < 25) begin
				memAddr <= i2;
				memWriteEnable <= 1;
				memWrite <= data[i2];
			end else if (i2 < 50) begin
				memAddr <= (24-i2a);
				data[i2a] <= memRead;
			end else begin
				countIO <= 0;
				state <= write1;
			end
		end
		write1:
			if (!txBusy) begin
				txData <= data[i][m*8+7 -:8];
				txStart <= 1;
				state <= write2;
			end
		write2: begin
			countIO <= next;
			state <= (next == 0) ? read : write1;
		end
	endcase
end
endmodule