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@daxfohl
daxfohl / SubjWorldValue.cs
Created October 18, 2011 22:46
Purely Functional Events
using System;
using System.Collections.Generic;
using System.Linq;
namespace SubjWorldValue {
class Program {
static void Main() {
var uim = new UIM();
//var uim2 = uim.AddListenerx(w => w.BPM, (w, i) => w.Set(w1 => w1.Resp, i));
var uim2 = uim.AddBPMListener((w, i) => w.SetResp(i));
@daxfohl
daxfohl / ImmutableArrays.cs
Created October 20, 2011 17:10
ImmutableArrays
using System;
using System.Collections.Generic;
using System.Diagnostics;
using System.Linq;
namespace ImmutableArrays {
class Program {
static void Main() {
const int I = 1000000;
var sw = new Stopwatch();
@daxfohl
daxfohl / gist:2884473
Last active September 21, 2020 07:36
verilog sudoku
module trigger(clk, rxReady, rxData, txBusy, txStart, txData);
input clk;
input[7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
integer countIO;
reg[8:0] data[0:8][0:8];
@daxfohl
daxfohl / sudoku.v
Last active September 21, 2022 20:53
Verilog sudoku feedback loop
module trigger(clk, rxReady, rxData, txBusy, txStart, txData);
input clk;
input [7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
integer count81; // Number of cells received/sent over serial
reg[8:0] possible[0:8][0:8];
@daxfohl
daxfohl / gist:3593745
Created September 2, 2012 01:59
haskell sudoku
{-# LANGUAGE BangPatterns #-}
import Data.Bits
import Data.List
import qualified Data.Vector.Unboxed as UV
type Grid = UV.Vector PossSet
type PossSet = Int
type Index = Int
type Value = Int
data Region = Row Int | Col Int | Sq Int deriving(Show)
line = "0 0 12 0 0 0 21 0 0 11 0 0 0 7 0 0 0 0 3 17 0 0 9 0 24 0 0 0 0 17 0 0 18 0 0 11 0 0 0 0 0 22 0 0 0 1 13 20 0 0 4 1 2 8 9 0 0 0 3 0 0 0 24 20 0 0 6 0 0 0 0 0 0 22 11 21 22 24 23 0 0 4 10 5 0 0 0 9 18 1 0 0 15 0 0 3 8 0 0 0 11 0 0 7 0 24 6 0 2 23 17 4 0 0 12 0 0 0 0 0 0 0 15 0 0 0 0 0 0 0 17 9 21 0 0 0 15 0 19 0 0 0 0 18 0 0 0 0 16 14 0 0 0 5 0 4 22 11 0 10 0 0 0 16 17 0 0 12 0 1 13 9 25 0 8 0 0 6 0 3 0 18 1 0 0 0 0 14 21 7 0 0 0 9 23 19 0 0 2 0 0 9 0 17 8 0 15 25 0 0 12 0 0 4 0 0 2 0 0 11 20 0 21 0 0 0 13 7 0 0 23 3 0 0 0 0 0 20 0 0 0 0 0 0 10 0 18 0 4 22 13 0 18 0 5 2 0 0 0 0 0 0 4 0 0 3 0 0 0 8 0 1 0 7 23 0 0 0 16 23 0 0 7 0 0 1 25 0 0 5 0 0 0 0 0 24 0 14 0 0 0 0 0 11 25 0 0 12 0 0 0 0 0 23 21 20 0 14 4 0 0 0 0 0 0 8 12 20 19 0 0 0 0 23 0 0 0 0 0 11 24 0 0 0
@daxfohl
daxfohl / ants.clj
Created October 10, 2012 20:10 — forked from dribnet/ants.clj
Clojure ant sim from Rich Hickey
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Ant sim ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) Rich Hickey. All rights reserved.
; The use and distribution terms for this software are covered by the
; Common Public License 1.0 (http://opensource.org/licenses/cpl.php)
; which can be found in the file CPL.TXT at the root of this distribution.
; By using this software in any fashion, you are agreeing to be bound by
; the terms of this license.
; You must not remove this notice, or any other, from this software.
; Note: This code cannot run for very long on clojure 1.3 because
@daxfohl
daxfohl / postsave.bat
Created October 26, 2012 16:22
Postsave that distinguishes prints and regular images
set str1=%1
if x%str1:prints=%==x%str1% goto :regular
:prints
copy %1.jpg "D:\smilebooth\network\eventfolder\prints\"
goto :end
:regular
resizer titos.png %1.jpg %1_overlay.jpg
copy %1_overlay.jpg "D:\smilebooth\network\eventfolder\"
goto :end
:end
@daxfohl
daxfohl / gist:4010101
Created November 4, 2012 03:57
fpga reverse memory
module trigger(clk, rxReady, rxData, txBusy, txStart, txData, memAddr, memWriteEnable, memWrite, memRead);
input clk;
input [7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
output reg[24:0] memWrite;
output reg[9:0] memAddr;
output reg memWriteEnable;
@daxfohl
daxfohl / gist:4375461
Last active December 10, 2015 03:38
9-row LR and SI all regions in one-shot (51K logic elements, 2hr compile)
module trigger(clk, rxReady, rxData, txBusy, txStart, txData);
input clk;
input[7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
integer countIO;
reg[8:0] data[0:8][0:8];
@daxfohl
daxfohl / gist:4414011
Last active December 10, 2015 09:28
sudoku all
module trigger(clk, rxReady, rxData, txBusy, txStart, txData);
input clk;
input[7:0] rxData;
input rxReady;
input txBusy;
output reg txStart;
output reg[7:0] txData;
localparam READ=0, SOLVING=1, WRITE1=2, WRITE2=3;
localparam ROW=0, COL=1, SQ=2;