stm32l0-pins.rs

#[cfg(feature = "io-STM32L021")]
pins! {
    PA0 => {
        AF0: RxPin<USART2>,
        AF6: RxPin<LPUART1>,
    },
    PA1 => {AF6: TxPin<LPUART1>},
    PA2 => {
        AF4: TxPin<USART2>,
        AF6: TxPin<LPUART1>,
    },
    PA3 => {
        AF4: RxPin<USART2>,
        AF6: RxPin<LPUART1>,
    },
    PA4 => {
        AF3: SclPin<I2C1>,
        AF6: TxPin<LPUART1>,
    },
    PA5 => {AF0: SckPin<SPI1>},
    PA6 => {AF0: MisoPin<SPI1>},
    PA7 => {AF0: MosiPin<SPI1>},
    PA9 => {
        AF1: SclPin<I2C1>,
        AF4: TxPin<USART2>,
    },
    PA10 => {
        AF1: SdaPin<I2C1>,
        AF4: RxPin<USART2>,
    },
    PA11 => {AF0: MisoPin<SPI1>},
    PA12 => {AF0: MosiPin<SPI1>},
    PA13 => {
        AF3: SdaPin<I2C1>,
        AF5: SckPin<SPI1>,
        AF6: RxPin<LPUART1>,
    },
    PA14 => {
        AF4: TxPin<USART2>,
        AF5: MisoPin<SPI1>,
        AF6: TxPin<LPUART1>,
    },
    PA15 => {AF4: RxPin<USART2>},
    PB0 => {AF1: MisoPin<SPI1>},
    PB1 => {AF1: MosiPin<SPI1>},
    PB3 => {AF0: SckPin<SPI1>},
    PB4 => {AF0: MisoPin<SPI1>},
    PB5 => {AF0: MosiPin<SPI1>},
    PB6 => {
        AF0: TxPin<USART2>,
        AF1: SclPin<I2C1>,
        AF6: TxPin<LPUART1>,
    },
    PB7 => {
        AF0: RxPin<USART2>,
        AF1: SdaPin<I2C1>,
        AF6: RxPin<LPUART1>,
    },
    PB8 => {
        AF0: TxPin<USART2>,
        AF4: SclPin<I2C1>,
    },
}


#[cfg(feature = "io-STM32L031")]
pins! {
    PA2 => {
        AF4: TxPin<USART2>,
        AF6: TxPin<LPUART1>,
    },
    PA3 => {
        AF4: RxPin<USART2>,
        AF6: RxPin<LPUART1>,
    },
    PA5 => {AF0: SckPin<SPI1>},
    PA6 => {AF0: MisoPin<SPI1>},
    PA7 => {AF0: MosiPin<SPI1>},
    PA9 => {
        AF1: SclPin<I2C1>,
        AF4: TxPin<USART2>,
    },
    PA10 => {
        AF1: SdaPin<I2C1>,
        AF4: RxPin<USART2>,
    },
    PA11 => {AF0: MisoPin<SPI1>},
    PA12 => {AF0: MosiPin<SPI1>},
    PA13 => {AF6: RxPin<LPUART1>},
    PA14 => {
        AF4: TxPin<USART2>,
        AF6: TxPin<LPUART1>,
    },
    PA15 => {AF4: RxPin<USART2>},
    PB0 => {AF1: MisoPin<SPI1>},
    PB1 => {AF1: MosiPin<SPI1>},
    PB3 => {AF0: SckPin<SPI1>},
    PB4 => {AF0: MisoPin<SPI1>},
    PB5 => {AF0: MosiPin<SPI1>},
    PB6 => {
        AF0: TxPin<USART2>,
        AF1: SclPin<I2C1>,
    },
    PB7 => {
        AF0: RxPin<USART2>,
        AF1: SdaPin<I2C1>,
    },
    PB8 => {AF4: SclPin<I2C1>},
    PB9 => {AF4: SdaPin<I2C1>},
    PB10 => {AF6: TxPin<LPUART1>},
    PB11 => {AF6: RxPin<LPUART1>},
    PB13 => {AF0: SckPin<SPI1>},
    PB14 => {AF0: MisoPin<SPI1>},
    PB15 => {AF0: MosiPin<SPI1>},
    PC0 => {AF6: RxPin<LPUART1>},
}


#[cfg(feature = "io-STM32L051")]
pins! {
    PA2 => {AF4: TxPin<USART2>},
    PA3 => {AF4: RxPin<USART2>},
    PA5 => {AF0: SckPin<SPI1>},
    PA6 => {AF0: MisoPin<SPI1>},
    PA7 => {AF0: MosiPin<SPI1>},
    PA9 => {AF4: TxPin<USART1>},
    PA10 => {AF4: RxPin<USART1>},
    PA11 => {AF0: MisoPin<SPI1>},
    PA12 => {AF0: MosiPin<SPI1>},
    PA14 => {AF4: TxPin<USART2>},
    PA15 => {AF4: RxPin<USART2>},
    PB3 => {AF0: SckPin<SPI1>},
    PB4 => {AF0: MisoPin<SPI1>},
    PB5 => {AF0: MosiPin<SPI1>},
    PB6 => {
        AF0: TxPin<USART1>,
        AF1: SclPin<I2C1>,
    },
    PB7 => {
        AF0: RxPin<USART1>,
        AF1: SdaPin<I2C1>,
    },
    PB8 => {AF4: SclPin<I2C1>},
    PB9 => {AF4: SdaPin<I2C1>},
    PB10 => {
        AF4: TxPin<LPUART1>,
        AF5: SckPin<SPI2>,
        AF6: SclPin<I2C2>,
    },
    PB11 => {
        AF4: RxPin<LPUART1>,
        AF6: SdaPin<I2C2>,
    },
    PB13 => {
        AF0: SckPin<SPI2>,
        AF5: SclPin<I2C2>,
    },
    PB14 => {
        AF0: MisoPin<SPI2>,
        AF5: SdaPin<I2C2>,
    },
    PB15 => {AF0: MosiPin<SPI2>},
    PC2 => {AF2: MisoPin<SPI2>},
    PC3 => {AF2: MosiPin<SPI2>},
    PC4 => {AF2: TxPin<LPUART1>},
    PC5 => {AF2: RxPin<LPUART1>},
    PC10 => {AF0: TxPin<LPUART1>},
    PC11 => {AF0: RxPin<LPUART1>},
}


#[cfg(feature = "io-STM32L071")]
pins! {
    PA0 => {AF6: TxPin<USART4>},
    PA1 => {AF6: RxPin<USART4>},
    PA2 => {
        AF4: TxPin<USART2>,
        AF6: TxPin<LPUART1>,
    },
    PA3 => {
        AF4: RxPin<USART2>,
        AF6: RxPin<LPUART1>,
    },
    PA5 => {AF0: SckPin<SPI1>},
    PA6 => {AF0: MisoPin<SPI1>},
    PA7 => {AF0: MosiPin<SPI1>},
    PA8 => {AF7: SclPin<I2C3>},
    PA9 => {
        AF4: TxPin<USART1>,
        AF6: SclPin<I2C1>,
    },
    PA10 => {
        AF4: RxPin<USART1>,
        AF6: SdaPin<I2C1>,
    },
    PA11 => {AF0: MisoPin<SPI1>},
    PA12 => {AF0: MosiPin<SPI1>},
    PA13 => {AF6: RxPin<LPUART1>},
    PA14 => {
        AF4: TxPin<USART2>,
        AF6: TxPin<LPUART1>,
    },
    PA15 => {AF4: RxPin<USART2>},
    PB3 => {
        AF0: SckPin<SPI1>,
        AF6: TxPin<USART5>,
    },
    PB4 => {
        AF0: MisoPin<SPI1>,
        AF6: RxPin<USART5>,
        AF7: SdaPin<I2C3>,
    },
    PB5 => {AF0: MosiPin<SPI1>},
    PB6 => {
        AF0: TxPin<USART1>,
        AF1: SclPin<I2C1>,
    },
    PB7 => {
        AF0: RxPin<USART1>,
        AF1: SdaPin<I2C1>,
    },
    PB8 => {AF4: SclPin<I2C1>},
    PB9 => {AF4: SdaPin<I2C1>},
    PB10 => {
        AF4: TxPin<LPUART1>,
        AF5: SckPin<SPI2>,
        AF6: SclPin<I2C2>,
        AF7: RxPin<LPUART1>,
    },
    PB11 => {
        AF4: RxPin<LPUART1>,
        AF6: SdaPin<I2C2>,
        AF7: TxPin<LPUART1>,
    },
    PB13 => {
        AF0: SckPin<SPI2>,
        AF5: SclPin<I2C2>,
    },
    PB14 => {
        AF0: MisoPin<SPI2>,
        AF5: SdaPin<I2C2>,
    },
    PB15 => {AF0: MosiPin<SPI2>},
    PC0 => {
        AF6: RxPin<LPUART1>,
        AF7: SclPin<I2C3>,
    },
    PC1 => {
        AF6: TxPin<LPUART1>,
        AF7: SdaPin<I2C3>,
    },
    PC2 => {AF2: MisoPin<SPI2>},
    PC3 => {AF2: MosiPin<SPI2>},
    PC4 => {AF2: TxPin<LPUART1>},
    PC5 => {AF2: RxPin<LPUART1>},
    PC9 => {AF7: SdaPin<I2C3>},
    PC10 => {
        AF0: TxPin<LPUART1>,
        AF6: TxPin<USART4>,
    },
    PC11 => {
        AF0: RxPin<LPUART1>,
        AF6: RxPin<USART4>,
    },
    PC12 => {AF2: TxPin<USART5>},
    PD1 => {AF1: SckPin<SPI2>},
    PD2 => {AF6: RxPin<USART5>},
    PD3 => {AF2: MisoPin<SPI2>},
    PD4 => {AF1: MosiPin<SPI2>},
    PD5 => {AF0: TxPin<USART2>},
    PD6 => {AF0: RxPin<USART2>},
    PD8 => {AF0: TxPin<LPUART1>},
    PD9 => {AF0: RxPin<LPUART1>},
    PE8 => {AF6: TxPin<USART4>},
    PE9 => {AF6: RxPin<USART4>},
    PE10 => {AF6: TxPin<USART5>},
    PE11 => {AF6: RxPin<USART5>},
    PE13 => {AF2: SckPin<SPI1>},
    PE14 => {AF2: MisoPin<SPI1>},
    PE15 => {AF2: MosiPin<SPI1>},
}