something.vhdl

library ieee;
use ieee.std_logic_1164.all;		-- ===================
use ieee.std_logic_arith.all;		-- |     LIBRERIE	 |
use ieee.std_logic_unsigned.all;	-- ===================

entity es5_led is
port(
	CLK : in std_logic;
	L: out std_logic_vector (3 downto 0);
	P: in std_logic
);

end;
architecture comportamentale of es5_led is
signal count : integer range 0 to 10000000;
begin

process (CLK)
begin
	if rising_edge(CLK) then
			
			if(count > 10000000) then
				count <= 0;
			else
				count <= count+1;
			end if;
			
			if(P = '1') then
				if(count < 2000000) then
					L <= "0001";			
				elsif(count < 4000000) then
					L <= "0011";			
				elsif(count < 6000000) then
					L <= "0111";
				elsif(count < 8000000) then
					L <= "1111";
				else
					L <= "0000";
				end if;
			else
				if(count < 2000000) then
					L <= "1000";			
				elsif(count < 4000000) then
					L <= "1100";			
				elsif(count < 6000000) then
					L <= "1110";
				elsif(count < 8000000) then
					L <= "1111";
				else
					L <= "0000";
				end if;
			end if;
	end if;
end process;

end comportamentale;