Created
January 4, 2024 11:37
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IDA Pro config for NEC 780101/780102/780103
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| .UPD780101 | |
| .UPD780102 | |
| .UPD780103 | |
| ; U15836EJ5V0UD00 | |
| ; MEMORY MAP | |
| area DATA ROM 0x0000:0x6000 Internal ROM | |
| area DATA RAM 0xFC00:0xFF00 Internal High-Speed RAM | |
| area DATA SFR 0xFF00:0x10000 Special Function Register | |
| interrupt RESET 0x0000 RESET | |
| interrupt INTLVI_ 0x0004 INTLVI | |
| interrupt INTP0_ 0x0006 INTP0 | |
| interrupt INTP1_ 0x0008 INTP1 | |
| interrupt INTP2_ 0x000A INTP2 | |
| interrupt INTP3_ 0x000C INTP3 | |
| interrupt INTP4_ 0x000E INTP4 | |
| interrupt INTP5_ 0x0010 INTP5 | |
| interrupt INTSRE6_ 0x0012 INTSRE6 | |
| interrupt INTSR6_ 0x0014 INTSR6 | |
| interrupt INTST6_ 0x0016 INTST6 | |
| interrupt INTST0_ 0x0018 INTCSI10/INTST0 | |
| interrupt INTTMH1_ 0x001A INTTMH1 | |
| interrupt INTTMH0_ 0x001C INTTMH0 | |
| interrupt INTTM50_ 0x001E INTTM50 | |
| interrupt INTTM000_ 0x0020 INTTM000 | |
| interrupt INTTM010_ 0x0022 INTTM010 | |
| interrupt INTAD_ 0x0024 INTAD | |
| interrupt INTSR0_ 0x0026 INTSR0 | |
| interrupt BRK_ 0x003E BRK | |
| P0 0xFF00 Port register | |
| P1 0xFF01 Port register | |
| P2 0xFF02 Port register | |
| P3 0xFF03 Port register | |
| ADCR 0xFF08 A/D conversion result | |
| RXB6 0xFF0A Receive buffer register | |
| TXB6 0xFF0B Transmit buffer register | |
| P12 0xFF0C Port register | |
| P13 0xFF0D Port register | |
| SIO10 0xFF0F Serial I/O shift register | |
| TM00 0xFF10 16-bit timer counter | |
| CR000 0xFF12 16-bit timer capture/compare register | |
| CR010 0xFF14 16-bit timer capture/compare register | |
| TM50 0xFF16 8-bit timer counter | |
| CR50 0xFF17 8-bit timer compare register | |
| CMP00 0xFF18 8-bit timer H compare register | |
| CMP10 0xFF19 8-bit timer H compare register | |
| CMP01 0xFF1A 8-bit timer H compare register | |
| CMP11 0xFF1B 8-bit timer H compare register | |
| PM0 0xFF20 Port mode register | |
| PM0.PM03 3 Selects I/O mode of P03 pin | |
| PM0.PM02 2 Selects I/O mode of P02 pin | |
| PM0.PM01 1 Selects I/O mode of P01 pin | |
| PM0.PM00 0 Selects I/O mode of P00 pin | |
| PM1 0xFF21 Port mode register | |
| PM1.PM17 7 Selects I/O mode of P17 pin | |
| PM1.PM16 6 Selects I/O mode of P16 pin | |
| PM1.PM15 5 Selects I/O mode of P15 pin | |
| PM1.PM14 4 Selects I/O mode of P14 pin | |
| PM1.PM13 3 Selects I/O mode of P13 pin | |
| PM1.PM12 2 Selects I/O mode of P12 pin | |
| PM1.PM11 1 Selects I/O mode of P11 pin | |
| PM1.PM10 0 Selects I/O mode of P10 pin | |
| PM3 0xFF23 Port mode register | |
| PM3.PM33 3 Selects I/O mode of P33 pin | |
| PM3.PM32 2 Selects I/O mode of P32 pin | |
| PM3.PM31 1 Selects I/O mode of P31 pin | |
| PM3.PM30 0 Selects I/O mode of P30 pin | |
| ADM 0xFF28 A/D converter mode | |
| ADM.ADCS 7 A/D conversion operation control | |
| ADM.FR2 5 Conversion time selection bit 2 | |
| ADM.FR1 4 Conversion time selection bit 1 | |
| ADM.FR0 3 Conversion time selection bit 0 | |
| ADM.ADCE 0 Boost reference voltage generator operation control | |
| ADS 0xFF29 Analog input channel specification | |
| ADS.ADS1 1 Analog input channel specification bit 1 | |
| ADS.ADS0 0 Analog input channel specification bit 0 | |
| PFM 0xFF2A Power-fail comparison mode | |
| PFM.PFEN 7 Power-fail comparison enable | |
| PFM.PFCM 6 Power-fail comparison mode selection | |
| PFT 0xFF2B Power-fail comparison threshold | |
| PM12 0xFF2C Port mode register | |
| PM12.PM120 0 Selects I/O mode of P120 pin | |
| PU0 0xFF30 Pull-up resistor option register | |
| PU0.PU03 3 Selects internal pull-up resistor of P03 pin | |
| PU0.PU02 2 Selects internal pull-up resistor of P02 pin | |
| PU0.PU01 1 Selects internal pull-up resistor of P01 pin | |
| PU0.PU00 0 Selects internal pull-up resistor of P00 pin | |
| PU1 0xFF31 Pull-up resistor option register | |
| PU1.PU17 7 Selects internal pull-up resistor of P17 pin | |
| PU1.PU16 6 Selects internal pull-up resistor of P16 pin | |
| PU1.PU15 5 Selects internal pull-up resistor of P15 pin | |
| PU1.PU14 4 Selects internal pull-up resistor of P14 pin | |
| PU1.PU13 3 Selects internal pull-up resistor of P13 pin | |
| PU1.PU12 2 Selects internal pull-up resistor of P12 pin | |
| PU1.PU11 1 Selects internal pull-up resistor of P11 pin | |
| PU1.PU10 0 Selects internal pull-up resistor of P10 pin | |
| PU3 0xFF33 Pull-up resistor option register | |
| PU3.PU33 3 Selects internal pull-up resistor of P33 pin | |
| PU3.PU32 2 Selects internal pull-up resistor of P32 pin | |
| PU3.PU31 1 Selects internal pull-up resistor of P31 pin | |
| PU3.PU30 0 Selects internal pull-up resistor of P30 pin | |
| PU12 0xFF3C Pull-up resistor option register | |
| PU12.PU120 0 Selects internal pull-up resistor of P120 pin | |
| EGP 0xFF48 External interrupt rising edge enable | |
| EGP.EGP5 5 INTPn pin valid edge selection bit 5 | |
| EGP.EGP4 4 INTPn pin valid edge selection bit 4 | |
| EGP.EGP3 3 INTPn pin valid edge selection bit 3 | |
| EGP.EGP2 2 INTPn pin valid edge selection bit 2 | |
| EGP.EGP1 1 INTPn pin valid edge selection bit 1 | |
| EGP.EGP0 0 INTPn pin valid edge selection bit 0 | |
| EGN 0xFF49 External interrupt falling edge enable | |
| EGN.EGN5 5 INTPn pin valid edge selection bit 5 | |
| EGN.EGN4 4 INTPn pin valid edge selection bit 4 | |
| EGN.EGN3 3 INTPn pin valid edge selection bit 3 | |
| EGN.EGN2 2 INTPn pin valid edge selection bit 2 | |
| EGN.EGN1 1 INTPn pin valid edge selection bit 1 | |
| EGN.EGN0 0 INTPn pin valid edge selection bit 0 | |
| ISC 0xFF4F Input switch control | |
| ISC.ISC1 1 TI000 input source selection | |
| ISC.ISC0 0 INTP0 input source selection | |
| ASIM6 0xFF50 Asynchronous serial interface operation mode register | |
| ASIM6.POWER6 7 Enables/disables operation of internal operation clock | |
| ASIM6.TXE6 6 Enables/disables transmission | |
| ASIM6.RXE6 5 Enables/disables reception | |
| ASIM6.PS61 4 Parity setting bit 1 | |
| ASIM6.PS60 3 Parity setting bit 0 | |
| ASIM6.CL6 2 Specifies character length of transmit/receive data | |
| ASIM6.SL6 1 Specifies number of stop bits of transmit data | |
| ASIM6.ISRM6 0 Enables/disables occurrence of reception completion interrupt in case of error | |
| ASIS6 0xFF53 Asynchronous serial interface reception error status register | |
| ASIS6.PE6 2 Status flag indicating parity error | |
| ASIS6.FE6 1 Status flag indicating framing error | |
| ASIS6.OVE6 0 Status flag indicating overrun error | |
| ASIF6 0xFF55 Asynchronous serial interface transmission status register | |
| ASIF6.TXBF6 1 Transmit buffer data flag | |
| ASIF6.TXSF6 0 Transmit shift register data flag | |
| CKSR6 0xFF56 Clock selection register | |
| CKSR6.TPS63 3 Base clock selection bit 3 | |
| CKSR6.TPS62 2 Base clock selection bit 2 | |
| CKSR6.TPS61 1 Base clock selection bit 1 | |
| CKSR6.TPS60 0 Base clock selection bit 0 | |
| BRGC6 0xFF57 Baud rate generator control register | |
| BRGC6.MDL67 7 Output clock selection of 8-bit counter bit 7 | |
| BRGC6.MDL66 6 Output clock selection of 8-bit counter bit 6 | |
| BRGC6.MDL65 5 Output clock selection of 8-bit counter bit 5 | |
| BRGC6.MDL64 4 Output clock selection of 8-bit counter bit 4 | |
| BRGC6.MDL63 3 Output clock selection of 8-bit counter bit 3 | |
| BRGC6.MDL62 2 Output clock selection of 8-bit counter bit 2 | |
| BRGC6.MDL61 1 Output clock selection of 8-bit counter bit 1 | |
| BRGC6.MDL60 0 Output clock selection of 8-bit counter bit 0 | |
| ASICL6 0xFF58 Asynchronous serial interface control register | |
| ASICL6.SBRF6 7 SBF reception status flag | |
| ASICL6.SBRT6 6 SBF reception trigger | |
| ASICL6.DIR6 1 First bit specification | |
| ASICL6.TXDLV6 0 Enables/disables inverting TXD6 output | |
| TMHMD0 0xFF69 8-bit timer H mode register | |
| TMHMD0.TMHE0 7 Timer operation enable | |
| TMHMD0.CKS02 6 Count clock selection bit 2 | |
| TMHMD0.CKS01 5 Count clock selection bit 1 | |
| TMHMD0.CKS00 4 Count clock selection bit 0 | |
| TMHMD0.TMMD01 3 Timer operation mode bit 1 | |
| TMHMD0.TMMD00 2 Timer operation mode bit 0 | |
| TMHMD0.TOLEV0 1 Timer output level control (in default mode) | |
| TMHMD0.TOEN0 0 Timer output control | |
| TCL50 0xFF6A Timer clock selection register | |
| TCL50.TCL502 2 Count clock selection bit 2 | |
| TCL50.TCL501 1 Count clock selection bit 1 | |
| TCL50.TCL500 0 Count clock selection bit 0 | |
| TMC50 0xFF6B 8-bit timer mode control register | |
| TMC50.TCE50 7 TM50 count operation control | |
| TMC50.TMC506 6 TM50 operating mode selection | |
| TMC50.LVS50 3 Timer output F/F status setting bit 1 | |
| TMC50.LVR50 2 Timer output F/F status setting bit 0 | |
| TMC50.TMC501 1 Timer F/F control or Active level selection | |
| TMC50.TOE50 0 Timer output control | |
| TMHMD1 0xFF6C 8-bit timer H mode register | |
| TMHMD1.TMHE1 7 Timer operation enable | |
| TMHMD1.CKS12 6 Count clock selection bit 2 | |
| TMHMD1.CKS11 5 Count clock selection bit 1 | |
| TMHMD1.CKS10 4 Count clock selection bit 0 | |
| TMHMD1.TMMD11 3 Timer operation mode bit 1 | |
| TMHMD1.TMMD10 2 Timer operation mode bit 0 | |
| TMHMD1.TOLEV1 1 Timer output level control (in default mode) | |
| TMHMD1.TOEN1 0 Timer output control | |
| ASIM0 0xFF70 Asynchronous serial interface operation mode register | |
| ASIM0.POWER0 7 Enables/disables operation of internal operation clock | |
| ASIM0.TXE0 6 Enables/disables transmission | |
| ASIM0.RXE0 5 Enables/disables reception | |
| ASIM0.PS01 4 Parity setting bit 1 | |
| ASIM0.PS00 3 Parity setting bit 0 | |
| ASIM0.CL0 2 Specifies character length of transmit/receive data | |
| ASIM0.SL0 1 Specifies number of stop bits of transmit data | |
| BRGC0 0xFF71 Baud rate generator control register | |
| BRGC0.TPS01 7 Base clock selection bit 1 | |
| BRGC0.TPS00 6 Base clock selection bit 0 | |
| BRGC0.MDL04 4 Selection of 5-bit counter output clock bit 4 | |
| BRGC0.MDL03 3 Selection of 5-bit counter output clock bit 3 | |
| BRGC0.MDL02 2 Selection of 5-bit counter output clock bit 2 | |
| BRGC0.MDL01 1 Selection of 5-bit counter output clock bit 1 | |
| BRGC0.MDL00 0 Selection of 5-bit counter output clock bit 0 | |
| RXB0 0xFF72 Receive buffer register | |
| ASIS0 0xFF73 Asynchronous serial interface reception error status register | |
| ASIS0.PE0 2 Status flag indicating parity error | |
| ASIS0.FE0 1 Status flag indicating framing error | |
| ASIS0.OVE0 0 Status flag indicating overrun error | |
| TXS0 0xFF74 Transmit shift register | |
| CSIM10 0xFF80 Serial operation mode register | |
| CSIM10.CSIE10 7 Operation control in 3-wire serial I/O mode | |
| CSIM10.TRMD10 6 Transmit/receive mode control | |
| CSIM10.DIR10 1 First bit specification | |
| CSIM10.CSOT10 0 Communication status flag | |
| CSIC10 0xFF81 Serial clock selection register | |
| CSIC10.CKP10 4 Specification of data transmission/reception timing | |
| CSIC10.DAP10 3 Specification of data transmission/reception timing | |
| CSIC10.CKS102 2 CSI10 serial clock selection bit 2 | |
| CSIC10.CKS101 1 CSI10 serial clock selection bit 1 | |
| CSIC10.CKS100 0 CSI10 serial clock selection bit 0 | |
| SOTB10 0xFF84 Transmit buffer register | |
| WDTM 0xFF98 Watchdog timer mode | |
| WDTM.WDCS4 4 Operation clock selection bit 1 | |
| WDTM.WDCS3 3 Operation clock selection bit 0 | |
| WDTM.WDCS2 2 Overflow time setting bit 2 | |
| WDTM.WDCS1 1 Overflow time setting bit 1 | |
| WDTM.WDCS0 0 Overflow time setting bit 0 | |
| WDTE 0xFF99 Watchdog timer enable | |
| RCM 0xFFA0 Ring-OSC mode | |
| RCM.RSTOP 0 Ring-OSC oscillating/stopped | |
| MCM 0xFFA1 Main clock mode | |
| MCM.MCS 1 CPU clock status | |
| MCM.MCM0 0 Selection of clock supplied to CPU | |
| MOC 0xFFA2 Main OSC control | |
| MOC.MSTOP 7 Control of X1 oscillator operation | |
| OSTC 0xFFA3 Oscillation stabilization time counter status | |
| OSTC.MOST11 4 Oscillation stabilization time status bit 11 | |
| OSTC.MOST13 3 Oscillation stabilization time status bit 13 | |
| OSTC.MOST14 2 Oscillation stabilization time status bit 14 | |
| OSTC.MOST15 1 Oscillation stabilization time status bit 15 | |
| OSTC.MOST16 0 Oscillation stabilization time status bit 16 | |
| OSTS 0xFFA4 Oscillation stabilization time select | |
| OSTS.OSTS2 2 Oscillation stabilization time selection bit 2 | |
| OSTS.OSTS1 1 Oscillation stabilization time selection bit 1 | |
| OSTS.OSTS0 0 Oscillation stabilization time selection bit 0 | |
| CLM 0xFFA9 Clock monitor mode | |
| CLM.CLME 0 Enables/disables clock monitor operation | |
| RESF 0xFFAC Reset control flag | |
| RESF.WDTRF 4 Internal reset request by watchdog timer (WDT) | |
| RESF.CLMRF 1 Internal reset request by clock monitor (CLM) | |
| RESF.LVIRF 0 Internal reset request by low-voltage detector (LVI) | |
| TMC00 0xFFBA 16-bit timer mode control register | |
| TMC00.TMC003 3 Operating mode and clear mode selection bit 2 | |
| TMC00.TMC002 2 Operating mode and clear mode selection bit 1 | |
| TMC00.TMC001 1 Operating mode and clear mode selection bit 0 | |
| TMC00.OVF00 0 16-bit timer counter 00 (TM00) overflow detection | |
| PRM00 0xFFBB Prescaler mode register | |
| PRM00.ES101 7 TI010 valid edge selection bit 1 | |
| PRM00.ES100 6 TI010 valid edge selection bit 0 | |
| PRM00.ES001 5 TI000 valid edge selection bit 1 | |
| PRM00.ES000 4 TI000 valid edge selection bit 0 | |
| PRM00.PRM001 1 Count clock selection bit 1 | |
| PRM00.PRM000 0 Count clock selection bit 0 | |
| CRC00 0xFFBC Capture/compare control register | |
| CRC00.CRC002 2 CR010 operating mode selection | |
| CRC00.CRC001 1 CR000 capture trigger selection | |
| CRC00.CRC000 0 CR000 operating mode selection | |
| TOC00 0xFFBD 16-bit timer output control register | |
| TOC00.OSPT00 7 One-shot pulse output trigger control via software | |
| TOC00.OSPE00 6 One-shot pulse output operation control | |
| TOC00.TOC004 4 Timer output F/F control using match of CR010 and TM00 | |
| TOC00.LVS00 3 Timer output F/F status setting bit 1 | |
| TOC00.LVR00 2 Timer output F/F status setting bit 0 | |
| TOC00.TOC001 1 Timer output F/F control using match of CR000 and TM00 | |
| TOC00.TOE00 0 Timer output control | |
| LVIM 0xFFBE Low-voltage detection | |
| LVIM.LVION 7 Enables low-voltage detection operation | |
| LVIM.LVIE 4 Specifies reference voltage generator | |
| LVIM.LVIMD 1 Low-voltage detection operation mode selection | |
| LVIM.LVIF 0 Low-voltage detection flag | |
| LVIS 0xFFBF Low-voltage detection level selection | |
| LVIS.LVIS2 2 Detection level bit 2 | |
| LVIS.LVIS1 1 Detection level bit 1 | |
| LVIS.LVIS0 0 Detection level bit 0 | |
| IF0L 0xFFE0 Interrupt request flag register | |
| IF0L.SREIF6 7 | |
| IF0L.PIF5 6 | |
| IF0L.PIF4 5 | |
| IF0L.PIF3 4 | |
| IF0L.PIF2 3 | |
| IF0L.PIF1 2 | |
| IF0L.PIF0 1 | |
| IF0L.LVIIF 0 | |
| IF0H 0xFFE1 Interrupt request flag register | |
| IF0H.TMIF010 7 | |
| IF0H.TMIF000 6 | |
| IF0H.TMIF50 5 | |
| IF0H.TMIFH0 4 | |
| IF0H.TMIFH1 3 | |
| IF0H.DUALIF0 2 | |
| IF0H.STIF6 1 | |
| IF0H.SRIF6 0 | |
| IF1L 0xFFE2 Interrupt request flag register | |
| IF1L.SRIF0 1 | |
| IF1L.ADIF 0 | |
| MK0L 0xFFE4 Interrupt mask flag register | |
| MK0L.SREMK6 7 | |
| MK0L.PMK5 6 | |
| MK0L.PMK4 5 | |
| MK0L.PMK3 4 | |
| MK0L.PMK2 3 | |
| MK0L.PMK1 2 | |
| MK0L.PMK0 1 | |
| MK0L.LVIMK 0 | |
| MK0H 0xFFE5 Interrupt mask flag register | |
| MK0H.TMMK010 7 | |
| MK0H.TMMK000 6 | |
| MK0H.TMMK50 5 | |
| MK0H.TMMKH0 4 | |
| MK0H.TMMKH1 3 | |
| MK0H.DUALMK0 2 | |
| MK0H.STMK6 1 | |
| MK0H.SRMK6 0 | |
| MK1L 0xFFE6 Interrupt mask flag register | |
| MK1L.SRMK0 1 | |
| MK1L.ADMK 0 | |
| PR0L 0xFFE8 Priority specification flag register | |
| PR0L.SREPR6 7 | |
| PR0L.PPR5 6 | |
| PR0L.PPR4 5 | |
| PR0L.PPR3 4 | |
| PR0L.PPR2 3 | |
| PR0L.PPR1 2 | |
| PR0L.PPR0 1 | |
| PR0L.LVIPR 0 | |
| PR0H 0xFFE9 Priority specification flag register | |
| PR0H.TMPR010 7 | |
| PR0H.TMPR000 6 | |
| PR0H.TMPR50 5 | |
| PR0H.TMPRH0 4 | |
| PR0H.TMPRH1 3 | |
| PR0H.DUALPR0 2 | |
| PR0H.STPR6 1 | |
| PR0H.SRPR6 0 | |
| PR1L 0xFFEA Priority specification flag register | |
| PR1L.SRPR0 1 | |
| PR1L.ADPR 0 | |
| IMS 0xFFF0 Internal memory size switching | |
| IMS.RAM2 7 Internal high-speed RAM capacity selection bit 2 | |
| IMS.RAM1 6 Internal high-speed RAM capacity selection bit 1 | |
| IMS.RAM0 5 Internal high-speed RAM capacity selection bit 0 | |
| IMS.ROM3 3 Internal ROM capacity selection bit 3 | |
| IMS.ROM2 2 Internal ROM capacity selection bit 2 | |
| IMS.ROM1 1 Internal ROM capacity selection bit 1 | |
| IMS.ROM0 0 Internal ROM capacity selection bit 0 | |
| PCC 0xFFFB Processor clock control | |
| PCC.PCC2 2 Selects CPU cIock bit 2 | |
| PCC.PCC1 1 Selects CPU cIock bit 1 | |
| PCC.PCC0 0 Selects CPU cIock bit 0 |
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