gistfile1.clj

;Define a module with 1 parameter (n)
;it's an up-counter
(defmodule counter [n]
    [:outputs [x ((uintm n) 0)]]
    (connect x (inc x)))

;Generate the verilog for the module
(println (module->verilog (counter 8)))

;Generate a testbest that verifies that it produces
;((uintm 8) 0), ((uintm 8) 1), ((uintm 8) 2), ... each cycle
(println
  (make-testbench
    (counter 8)
    (map (fn [x]
           {:x (verilog-repr ((uintm 8) x))})
         (take 10 (iterate inc 0)))))