gistfile1.v

module counter12952(
  clock,
  reset,
  x
);
  input wire clock;
  input wire reset;

  //outputs
  output reg [7:0] x;


  wire [7:0] G__13904 = x + 8'd1;


  always @(posedge clock)
    if (reset) begin
      x <= 8'd0;
    end else begin
      x <= G__13904;
    end
endmodule

module test;
  reg clk = 0;
  always #5 clk = !clk;
  reg rst = 1;

  counter12952 dut(
    .clock(clk), .reset(rst),
    .x()
  );

  initial begin
    #10 rst = 0;
    if (dut.x != 8'd0) begin
      $display("failed assertion: dut.x != 8'd0");
      $finish;
    end    #10
    if (dut.x != 8'd1) begin
      $display("failed assertion: dut.x != 8'd1");
      $finish;
    end    #10
    if (dut.x != 8'd2) begin
      $display("failed assertion: dut.x != 8'd2");
      $finish;
    end    #10
    if (dut.x != 8'd3) begin
      $display("failed assertion: dut.x != 8'd3");
      $finish;
    end    #10
    if (dut.x != 8'd4) begin
      $display("failed assertion: dut.x != 8'd4");
      $finish;
    end    #10
    if (dut.x != 8'd5) begin
      $display("failed assertion: dut.x != 8'd5");
      $finish;
    end    #10
    if (dut.x != 8'd6) begin
      $display("failed assertion: dut.x != 8'd6");
      $finish;
    end    #10
    if (dut.x != 8'd7) begin
      $display("failed assertion: dut.x != 8'd7");
      $finish;
    end    #10
    if (dut.x != 8'd8) begin
      $display("failed assertion: dut.x != 8'd8");
      $finish;
    end    #10
    if (dut.x != 8'd9) begin
      $display("failed assertion: dut.x != 8'd9");
      $finish;
    end    #10
    $display("test passed");
    $finish;
  end
endmodule