Created
July 4, 2017 03:13
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ATMega328 setup INT0 and INT1 for hardware interrupt on falling edge
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//setup INT0 and INT1 for hw int. | |
DDRD &= ~(1 << DDD2); // Clear the PD2&PD3 pin & enable PD2 & PD3 as input | |
DDRD &= ~(1 << DDD3); | |
PORTD |= (1 << PORTD2) | (1 << PORTD3); | |
//trigger INT0, INT1 on falling edge | |
EICRA |= (1 << ISC11) | (1<< ISC01); | |
EIMSK |= (1 << INT0) | (1 << INT1); |
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