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/dts-v1/; | |
#include <dt-bindings/input/input.h> | |
#include "tegra20.dtsi" | |
/ { | |
model = "Acer A50x Tegra20 Picasso board"; | |
compatible = "acer,picasso", "nvidia,tegra20"; | |
aliases { | |
rtc0 = "/i2c@7000d000/tps6586x@34"; | |
rtc1 = "/rtc@7000e000"; | |
serial0 = &uartd; | |
serial1 = &uartb; | |
serial2 = &uartc; | |
}; | |
memory { | |
reg = <0x00000000 0x40000000>; | |
}; | |
host1x@50000000 { | |
dc@54200000 { | |
rgb { | |
status = "okay"; | |
nvidia,panel = <&panel>; | |
}; | |
}; | |
hdmi@54280000 { | |
status = "okay"; | |
vdd-supply = <&hdmi_vdd_reg>; | |
pll-supply = <&hdmi_pll_reg>; | |
nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) | |
GPIO_ACTIVE_HIGH>; | |
}; | |
}; | |
pinmux@70000014 { | |
pinctrl-names = "default"; | |
pinctrl-0 = <&state_default>; | |
state_default: pinmux { | |
ata { | |
nvidia,pins = "ata"; | |
nvidia,function = "ide"; | |
}; | |
atb { | |
nvidia,pins = "atb", "gma", "gme"; | |
nvidia,function = "sdio4"; | |
}; | |
atc { | |
nvidia,pins = "atc"; | |
nvidia,function = "nand"; | |
}; | |
atd { | |
nvidia,pins = "atd", "ate", "gmb", "spia", | |
"spib", "spic"; | |
nvidia,function = "gmi"; | |
}; | |
cdev1 { | |
nvidia,pins = "cdev1"; | |
nvidia,function = "plla_out"; | |
}; | |
cdev2 { | |
nvidia,pins = "cdev2"; | |
nvidia,function = "pllp_out4"; | |
}; | |
crtp { | |
nvidia,pins = "crtp", "lm1"; | |
nvidia,function = "crt"; | |
}; | |
csus { | |
nvidia,pins = "csus"; | |
nvidia,function = "vi_sensor_clk"; | |
}; | |
dap1 { | |
nvidia,pins = "dap1"; | |
nvidia,function = "dap1"; | |
}; | |
dap2 { | |
nvidia,pins = "dap2"; | |
nvidia,function = "dap2"; | |
}; | |
dap3 { | |
nvidia,pins = "dap3"; | |
nvidia,function = "dap3"; | |
}; | |
dap4 { | |
nvidia,pins = "dap4"; | |
nvidia,function = "dap4"; | |
}; | |
dta { | |
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
nvidia,function = "vi"; | |
}; | |
dtf { | |
nvidia,pins = "dtf"; | |
nvidia,function = "i2c3"; | |
}; | |
gmc { | |
nvidia,pins = "gmc"; | |
nvidia,function = "uartd"; | |
}; | |
gmd { | |
nvidia,pins = "gmd"; | |
nvidia,function = "sflash"; | |
}; | |
gpu { | |
nvidia,pins = "gpu"; | |
nvidia,function = "pwm"; | |
}; | |
gpu7 { | |
nvidia,pins = "gpu7"; | |
nvidia,function = "rtck"; | |
}; | |
gpv { | |
nvidia,pins = "gpv", "slxa"; | |
nvidia,function = "pcie"; | |
}; | |
hdint { | |
nvidia,pins = "hdint"; | |
nvidia,function = "hdmi"; | |
}; | |
i2cp { | |
nvidia,pins = "i2cp"; | |
nvidia,function = "i2cp"; | |
}; | |
irrx { | |
nvidia,pins = "irrx", "irtx"; | |
nvidia,function = "uartb"; | |
}; | |
kbca { | |
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
"kbce", "kbcf"; | |
nvidia,function = "kbc"; | |
}; | |
lcsn { | |
nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", | |
"lsdi", "lvp0"; | |
nvidia,function = "rsvd4"; | |
}; | |
ld0 { | |
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
"ld5", "ld6", "ld7", "ld8", "ld9", | |
"ld10", "ld11", "ld12", "ld13", "ld14", | |
"ld15", "ld16", "ld17", "ldi", "lhp0", | |
"lhp1", "lhp2", "lhs", "lpp", "lsc0", | |
"lsc1", "lsck", "lsda", "lspi", "lvp1", | |
"lvs"; | |
nvidia,function = "displaya"; | |
}; | |
owc { | |
nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
nvidia,function = "rsvd2"; | |
}; | |
pmc { | |
nvidia,pins = "pmc"; | |
nvidia,function = "pwr_on"; | |
}; | |
rm { | |
nvidia,pins = "rm"; | |
nvidia,function = "i2c1"; | |
}; | |
sdb { | |
nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; | |
nvidia,function = "sdio3"; | |
}; | |
sdio1 { | |
nvidia,pins = "sdio1"; | |
nvidia,function = "sdio1"; | |
}; | |
slxd { | |
nvidia,pins = "slxd"; | |
nvidia,function = "spdif"; | |
}; | |
spid { | |
nvidia,pins = "spid", "spie", "spif"; | |
nvidia,function = "spi1"; | |
}; | |
spig { | |
nvidia,pins = "spig", "spih"; | |
nvidia,function = "spi2_alt"; | |
}; | |
uaa { | |
nvidia,pins = "uaa", "uab", "uda"; | |
nvidia,function = "ulpi"; | |
}; | |
uad { | |
nvidia,pins = "uad"; | |
nvidia,function = "irda"; | |
}; | |
uca { | |
nvidia,pins = "uca", "ucb"; | |
nvidia,function = "uartc"; | |
}; | |
conf_ata { | |
nvidia,pins = "ata", "atb", "atc", "atd", | |
"cdev1", "cdev2", "csus", "dap1", | |
"dap4", "dte", "dtf", "gma", "gmc", | |
"gme", "gpu", "gpu7", "gpv", "i2cp", | |
"irrx", "irtx", "pta", "rm", | |
"sdc", "sdd", "slxc", "slxd", "slxk", | |
"spdi", "spdo", "uac", "uad", "uda"; | |
nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
}; | |
conf_ate { | |
nvidia,pins = "ate", "dap2", "dap3", | |
"gmd", "owc", "spia", "spib", "spic", | |
"spid", "spie"; | |
nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
}; | |
conf_ck32 { | |
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
"pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
}; | |
conf_crtp { | |
nvidia,pins = "crtp", "gmb", "slxa", "spig", | |
"spih"; | |
nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
}; | |
conf_dta { | |
nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; | |
nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
}; | |
conf_dte { | |
nvidia,pins = "spif"; | |
nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
}; | |
conf_hdint { | |
nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
"lpw1", "lsck", "lsda", "lsdi", | |
"lvp0"; | |
nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
}; | |
conf_kbca { | |
nvidia,pins = "kbca", "kbcc", "kbcd", | |
"kbce", "kbcf", "sdio1", "uaa", | |
"uab", "uca", "ucb"; | |
nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
}; | |
conf_lc { | |
nvidia,pins = "lc", "ls"; | |
nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
}; | |
conf_ld0 { | |
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
"ld5", "ld6", "ld7", "ld8", "ld9", | |
"ld10", "ld11", "ld12", "ld13", "ld14", | |
"ld15", "ld16", "ld17", "ldi", "lhp0", | |
"lhp1", "lhp2", "lhs", "lm0", "lpp", | |
"lpw0", "lpw2", "lsc0", "lsc1", "lspi", | |
"lvp1", "lvs", "pmc", "sdb"; | |
nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
}; | |
conf_ld17_0 { | |
nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
"ld23_22"; | |
nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
}; | |
drive_ddc { | |
nvidia,pins = "drive_ddc"; | |
nvidia,schmitt = <TEGRA_PIN_ENABLE>; | |
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; | |
}; | |
drive_vi1 { | |
nvidia,pins = "drive_vi1"; | |
nvidia,schmitt = <TEGRA_PIN_ENABLE>; | |
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; | |
}; | |
drive_sdio1 { | |
nvidia,pins = "drive_sdio1"; | |
nvidia,schmitt = <TEGRA_PIN_ENABLE>; | |
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; | |
}; | |
drive_dbg { | |
nvidia,pins = "drive_dbg"; | |
nvidia,schmitt = <TEGRA_PIN_ENABLE>; | |
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; | |
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
}; | |
drive_vi2 { | |
nvidia,pins = "drive_vi2"; | |
nvidia,schmitt = <TEGRA_PIN_ENABLE>; | |
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; | |
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
}; | |
drive_at1 { | |
nvidia,pins = "drive_at1"; | |
nvidia,schmitt = <TEGRA_PIN_ENABLE>; | |
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; | |
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
}; | |
drive_ao1 { | |
nvidia,pins = "drive_ao1"; | |
nvidia,schmitt = <TEGRA_PIN_ENABLE>; | |
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; | |
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
}; | |
}; | |
state_i2cmux_ddc: pinmux_i2cmux_ddc { | |
ddc { | |
nvidia,pins = "ddc"; | |
nvidia,function = "i2c2"; | |
}; | |
pta { | |
nvidia,pins = "pta"; | |
nvidia,function = "rsvd4"; | |
}; | |
}; | |
state_i2cmux_pta: pinmux_i2cmux_pta { | |
ddc { | |
nvidia,pins = "ddc"; | |
nvidia,function = "rsvd4"; | |
}; | |
pta { | |
nvidia,pins = "pta"; | |
nvidia,function = "i2c2"; | |
}; | |
}; | |
state_i2cmux_idle: pinmux_i2cmux_idle { | |
ddc { | |
nvidia,pins = "ddc"; | |
nvidia,function = "rsvd4"; | |
}; | |
pta { | |
nvidia,pins = "pta"; | |
nvidia,function = "rsvd4"; | |
}; | |
}; | |
}; | |
i2c@7000c000 { | |
status = "okay"; | |
clock-frequency = <400000>; | |
touchscreen@4c { | |
compatible = "atmel,maxtouch", "atmel,mxt-ts-a500"; | |
reg = <0x4c>; | |
interrupt-parent = <&gpio>; | |
interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_EDGE_FALLING>; | |
}; | |
wm8903: wm8903@1a { | |
compatible = "wlf,wm8903"; | |
reg = <0x1a>; | |
interrupt-parent = <&gpio>; | |
interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; | |
gpio-controller; | |
#gpio-cells = <2>; | |
micdet-cfg = <0>; | |
micdet-delay = <500>; | |
gpio-cfg = <0 0 0 0xffffffff 0xffffffff>; | |
}; | |
}; | |
i2c@7000c400 { | |
status = "okay"; | |
clock-frequency = <10000>; | |
}; | |
i2cmux { | |
compatible = "i2c-mux-pinctrl"; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
i2c-parent = <&{/i2c@7000c400}>; | |
pinctrl-names = "ddc", "pta", "idle"; | |
pinctrl-0 = <&state_i2cmux_ddc>; | |
pinctrl-1 = <&state_i2cmux_pta>; | |
pinctrl-2 = <&state_i2cmux_idle>; | |
hdmi_ddc: i2c@0 { | |
reg = <0>; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
}; | |
lvds_ddc: i2c@1 { | |
reg = <1>; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
embedded-controller@58 { | |
compatible = "acer,a50x-ec"; | |
reg = <0x58>; | |
ec,i2c-retry-count = <5>; | |
system-power-controller; | |
battery { | |
compatible = "acer,a50x-battery"; | |
power-supplies = <&gpio_charger>; | |
}; | |
leds { | |
compatible = "acer,a50x-leds"; | |
leds-reset; | |
}; | |
}; | |
}; | |
}; | |
i2c@7000c500 { | |
status = "okay"; | |
clock-frequency = <400000>; | |
}; | |
gpio_charger: charger { | |
compatible = "gpio-charger"; | |
charger-type = "mains"; | |
gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; | |
}; | |
pwm: pwm@7000a000 { | |
status = "okay"; | |
}; | |
backlight: backlight { | |
compatible = "pwm-backlight"; | |
enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; | |
power-supply = <&vdd_bl_reg>; | |
pwms = <&pwm 2 41667>; | |
brightness-levels = <3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | |
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 | |
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 | |
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 | |
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 | |
82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 | |
98 99 100 101 102 103 104 105 106 107 108 109 | |
110 111 112 113 114 115 116 117 118 119 120 121 | |
122 123 124 125 126 127 128 129 130 131 132 133 | |
134 135 136 137 138 139 140 141 142 143 144 145 | |
146 147 148 149 150 151 152 153 154 155 156 157 | |
158 159 160 161 162 163 164 165 166 167 168 169 | |
170 171 172 173 174 175 176 177 178 179 180 181 | |
182 183 184 185 186 187 188 189 190 191 192 193 | |
194 195 196 197 198 199 200 201 202 203 204 205 | |
206 207 208 209 210 211 212 213 214 215 216 217 | |
218 219 220 221 222 223 224 225 226 227 228 229 | |
230 231 232 233 234 235 236 237 238 239 240 241 | |
242 243 244 245 246 247 248 249 250 251 252 253 | |
254 255>; | |
default-brightness-level = <70>; | |
}; | |
panel: panel { | |
compatible = "auo,b101ew05"; | |
power-supply = <&vdd_pnl_reg>; | |
backlight = <&backlight>; | |
ddc-i2c-bus = <&lvds_ddc>; | |
}; | |
clocks { | |
compatible = "simple-bus"; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
clk32k_in: clock@0 { | |
compatible = "fixed-clock"; | |
reg=<0>; | |
#clock-cells = <0>; | |
clock-frequency = <32768>; | |
}; | |
}; | |
regulators { | |
compatible = "simple-bus"; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
vdd_5v0_reg: regulator@0 { | |
compatible = "regulator-fixed"; | |
reg = <0>; | |
regulator-name = "vdd_5v0"; | |
regulator-min-microvolt = <5000000>; | |
regulator-max-microvolt = <5000000>; | |
regulator-always-on; | |
}; | |
vdd_pnl_reg: regulator@1 { | |
compatible = "regulator-fixed"; | |
reg = <1>; | |
regulator-name = "vdd_pnl"; | |
regulator-min-microvolt = <2800000>; | |
regulator-max-microvolt = <2800000>; | |
gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; | |
enable-active-high; | |
}; | |
vdd_bl_reg: regulator@2 { | |
compatible = "regulator-fixed"; | |
reg = <2>; | |
regulator-name = "vdd_bl"; | |
regulator-min-microvolt = <2800000>; | |
regulator-max-microvolt = <2800000>; | |
regulator-enable-ramp-delay = <300000>; | |
gpio = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; | |
enable-active-high; | |
}; | |
regulator@3 { | |
compatible = "regulator-fixed"; | |
reg = <3>; | |
regulator-name = "bcm_pwr"; | |
regulator-min-microvolt = <3300000>; | |
regulator-max-microvolt = <3300000>; | |
gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; | |
enable-active-high; | |
regulator-boot-on; | |
}; | |
vbus1_reg: regulator@4 { | |
compatible = "regulator-fixed"; | |
reg = <4>; | |
regulator-name = "vdd_usb1_vbus"; | |
regulator-min-microvolt = <5000000>; | |
regulator-max-microvolt = <5000000>; | |
gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; | |
enable-active-high; | |
regulator-always-on; | |
regulator-boot-on; | |
}; | |
vbus3_reg: regulator@5 { | |
compatible = "regulator-fixed"; | |
reg = <5>; | |
regulator-name = "vdd_usb3_vbus"; | |
regulator-min-microvolt = <5000000>; | |
regulator-max-microvolt = <5000000>; | |
gpio = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; | |
enable-active-high; | |
regulator-always-on; | |
regulator-boot-on; | |
}; | |
}; | |
i2c@7000d000 { | |
status = "okay"; | |
clock-frequency = <400000>; | |
tps6586x@34 { | |
compatible = "ti,tps6586x"; | |
reg = <0x34>; | |
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
#gpio-cells = <2>; | |
gpio-controller; | |
sys-supply = <&vdd_5v0_reg>; | |
vin-sm0-supply = <&sys_reg>; | |
vin-sm1-supply = <&sys_reg>; | |
vin-sm2-supply = <&sys_reg>; | |
vinldo01-supply = <&sm2_reg>; | |
vinldo23-supply = <&sm2_reg>; | |
vinldo4-supply = <&sm2_reg>; | |
vinldo678-supply = <&sm2_reg>; | |
vinldo9-supply = <&sm2_reg>; | |
regulators { | |
sys_reg: sys { | |
regulator-name = "vdd_sys"; | |
regulator-always-on; | |
}; | |
sm0 { | |
regulator-name = "vdd_sm0,vdd_core"; | |
regulator-min-microvolt = <1200000>; | |
regulator-max-microvolt = <1200000>; | |
regulator-always-on; | |
}; | |
sm1 { | |
regulator-name = "vdd_sm1,vdd_cpu"; | |
regulator-min-microvolt = <1000000>; | |
regulator-max-microvolt = <1000000>; | |
regulator-always-on; | |
}; | |
sm2_reg: sm2 { | |
regulator-name = "vdd_sm2,vin_ldo*"; | |
regulator-min-microvolt = <3700000>; | |
regulator-max-microvolt = <3700000>; | |
regulator-always-on; | |
}; | |
/* LDO0 is not connected to anything */ | |
ldo1 { | |
regulator-name = "vdd_ldo1,avdd_pll*"; | |
regulator-min-microvolt = <1100000>; | |
regulator-max-microvolt = <1100000>; | |
regulator-always-on; | |
}; | |
ldo2 { | |
regulator-name = "vdd_ldo2,vdd_rtc"; | |
regulator-min-microvolt = <1200000>; | |
regulator-max-microvolt = <1200000>; | |
}; | |
ldo3 { | |
regulator-name = "vdd_ldo3,avdd_usb*"; | |
regulator-min-microvolt = <3300000>; | |
regulator-max-microvolt = <3300000>; | |
regulator-always-on; | |
}; | |
ldo4 { | |
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; | |
regulator-min-microvolt = <1800000>; | |
regulator-max-microvolt = <1800000>; | |
regulator-always-on; | |
}; | |
mmc_vdd_reg: ldo5 { | |
regulator-name = "vdd_ldo5,vcore_mmc"; | |
regulator-min-microvolt = <1250000>; | |
regulator-max-microvolt = <3300000>; | |
regulator-always-on; | |
}; | |
avdd_vdac_reg: ldo6 { | |
regulator-name = "vdd_ldo6,avdd_vdac"; | |
regulator-min-microvolt = <1800000>; | |
regulator-max-microvolt = <1800000>; | |
}; | |
hdmi_vdd_reg: ldo7 { | |
regulator-name = "vdd_ldo7,avdd_hdmi"; | |
regulator-min-microvolt = <3300000>; | |
regulator-max-microvolt = <3300000>; | |
}; | |
hdmi_pll_reg: ldo8 { | |
regulator-name = "vdd_ldo8,avdd_hdmi_pll"; | |
regulator-min-microvolt = <1800000>; | |
regulator-max-microvolt = <1800000>; | |
}; | |
ldo9 { | |
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; | |
regulator-min-microvolt = <2850000>; | |
regulator-max-microvolt = <2850000>; | |
}; | |
ldo_rtc { | |
regulator-name = "vdd_rtc_out,vdd_cell"; | |
regulator-min-microvolt = <3300000>; | |
regulator-max-microvolt = <3300000>; | |
}; | |
}; | |
}; | |
temperature-sensor@4c { | |
compatible = "onnn,nct1008"; | |
reg = <0x4c>; | |
}; | |
magnetometer@c { | |
compatible = "ak,ak8975"; | |
reg = <0xc>; | |
interrupt-parent = <&gpio>; | |
interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; | |
}; | |
}; | |
pmc@7000e400 { | |
nvidia,invert-interrupt; | |
nvidia,suspend-mode = <1>; | |
nvidia,cpu-pwr-good-time = <2000>; | |
nvidia,cpu-pwr-off-time = <100>; | |
nvidia,core-pwr-good-time = <3845 3845>; | |
nvidia,core-pwr-off-time = <458>; | |
nvidia,sys-clock-req-active-high; | |
}; | |
sdhci@c8000000 { | |
#address-cells = <1>; | |
#size-cells = <0>; | |
status = "okay"; | |
bus-width = <4>; | |
power-gpios = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>; | |
keep-power-in-suspend; | |
sd-ignore-pm-notify; | |
enable-sdio-wakeup; | |
broken-cd; | |
brcmf: bcrmf@1 { | |
reg = <1>; | |
compatible = "brcm,bcm4329-fmac"; | |
interrupt-parent = <&gpio>; | |
interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>; | |
interrupt-names = "host-wake"; | |
}; | |
}; | |
sdhci@c8000400 { | |
status = "okay"; | |
bus-width = <4>; | |
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; | |
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; | |
}; | |
sdhci@c8000600 { | |
status = "okay"; | |
bus-width = <8>; | |
vmmc-supply = <&mmc_vdd_reg>; | |
non-removable; | |
}; | |
usb@c5000000 { | |
compatible = "nvidia,tegra20-udc"; | |
status = "okay"; | |
dr_mode = "otg"; | |
}; | |
usb-phy@c5000000 { | |
status = "okay"; | |
dr_mode = "otg"; | |
nvidia,xcvr-setup = <15>; | |
nvidia,xcvr-setup-use-fuses; | |
nvidia,xcvr-lsfslew = <2>; | |
nvidia,xcvr-lsrslew = <2>; | |
vbus-supply = <&vbus1_reg>; | |
}; | |
usb@c5004000 { | |
status = "disabled"; | |
}; | |
usb-phy@c5004000 { | |
status = "disabled"; | |
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) | |
GPIO_ACTIVE_LOW>; | |
}; | |
usb@c5008000 { | |
status = "okay"; | |
}; | |
usb-phy@c5008000 { | |
status = "okay"; | |
nvidia,hssync-start-delay = <9>; | |
nvidia,idle-wait-delay = <17>; | |
nvidia,elastic-limit = <16>; | |
nvidia,term-range-adj = <6>; | |
nvidia,xcvr-setup = <10>; | |
nvidia,xcvr-setup-use-fuses; | |
nvidia,xcvr-lsfslew = <2>; | |
nvidia,xcvr-lsrslew = <2>; | |
vbus-supply = <&vbus3_reg>; | |
}; | |
gpio-keys { | |
compatible = "gpio-keys"; | |
power { | |
label = "Power"; | |
gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; | |
linux,code = <KEY_POWER>; | |
gpio-key,wakeup; | |
}; | |
wakeup { | |
label = "Wakeup"; | |
gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; | |
linux,code = <KEY_POWER>; | |
gpio-key,wakeup; | |
}; | |
volume-up { | |
label = "Volume-up"; | |
gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; | |
linux,code = <KEY_VOLUMEUP>; | |
debounce-interval = <10>; | |
}; | |
volume-down { | |
label = "Volume-down"; | |
gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; | |
linux,code = <KEY_VOLUMEDOWN>; | |
debounce-interval = <10>; | |
}; | |
}; | |
tegra_i2s1: i2s@70002800 { | |
status = "okay"; | |
}; | |
sound { | |
compatible = "nvidia,tegra-audio-wm8903-picasso", | |
"nvidia,tegra-audio-wm8903"; | |
nvidia,model = "WM8903 NVIDIA Tegra Picasso"; | |
nvidia,audio-routing = | |
"Headphone Jack", "HPOUTR", | |
"Headphone Jack", "HPOUTL", | |
"Int Spk", "LINEOUTL", | |
"Int Spk", "LINEOUTR", | |
"Mic Jack", "MICBIAS", | |
"IN2L", "Mic Jack", | |
"IN2R", "Mic Jack", | |
"IN1L", "MICBIAS", | |
"IN1R", "MICBIAS"; | |
nvidia,i2s-controller = <&tegra_i2s1>; | |
nvidia,audio-codec = <&wm8903>; | |
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; | |
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; | |
nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; | |
vdd_dmic-supply = <&avdd_vdac_reg>; | |
clocks = <&tegra_car TEGRA20_CLK_PLL_A>, | |
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
<&tegra_car TEGRA20_CLK_CDEV1>; | |
clock-names = "pll_a", "pll_a_out0", "mclk"; | |
}; | |
uartb: serial@70006040 { | |
compatible = "nvidia,tegra20-hsuart"; | |
status = "okay"; | |
}; | |
uartc: serial@70006200 { | |
compatible = "nvidia,tegra20-hsuart"; | |
status = "okay"; | |
}; | |
uartd: serial@70006300 { | |
status = "okay"; | |
}; | |
memory-controller@7000f400 { | |
nvidia,use-ram-code; | |
elpida-8gb { | |
nvidia,ram-code = <0x0>; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
emc-table@25000 { | |
reg = <25000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <25000>; | |
nvidia,emc-registers = <0x00000002 0x00000006 | |
0x00000003 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000004 | |
0x00000003 0x00000008 0x0000000b 0x0000004d | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000004 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000068 0x00000000 0x00000003 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x00070000 0x00000000 0x00000000 0x00000003 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@50000 { | |
reg = <50000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <50000>; | |
nvidia,emc-registers = <0x00000003 0x00000007 | |
0x00000003 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x0000009f | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000007 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x000000d0 0x00000000 0x00000000 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x00070000 0x00000000 0x00000000 0x00000005 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@75000 { | |
reg = <75000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <75000>; | |
nvidia,emc-registers = <0x00000005 0x0000000a | |
0x00000004 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x000000ff | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x0000000b | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000138 0x00000000 0x00000000 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x00070000 0x00000000 0x00000000 0x00000007 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@150000 { | |
reg = <150000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <150000>; | |
nvidia,emc-registers = <0x00000009 0x00000014 | |
0x00000007 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x0000021f | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000015 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000270 0x00000000 0x00000001 | |
0x00000000 0x00000000 0x00000282 0xa07c04ae | |
0x007dd510 0x00000000 0x00000000 0x0000000e | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@300000 { | |
reg = <300000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <300000>; | |
nvidia,emc-registers = <0x00000012 0x00000027 | |
0x0000000d 0x00000006 0x00000007 0x00000005 | |
0x00000003 0x00000009 0x00000006 0x00000006 | |
0x00000003 0x00000003 0x00000002 0x00000006 | |
0x00000003 0x00000009 0x0000000c 0x0000045f | |
0x00000000 0x00000004 0x00000004 0x00000006 | |
0x00000008 0x00000001 0x0000000e 0x0000002a | |
0x00000003 0x0000000f 0x00000007 0x00000005 | |
0x00000002 0x000004e1 0x00000005 0x00000002 | |
0x00000000 0x00000000 0x00000282 0xe059048b | |
0x007e1510 0x00000000 0x00000000 0x0000001b | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
}; | |
elpida-4gb { | |
nvidia,ram-code = <0x1>; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
emc-table@25000 { | |
reg = <25000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <25000>; | |
nvidia,emc-registers = <0x00000002 0x00000006 | |
0x00000003 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000004 | |
0x00000003 0x00000008 0x0000000b 0x0000004d | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000004 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000068 0x00000000 0x00000003 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x0007c000 0x00000000 0x00000000 0x00000003 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@50000 { | |
reg = <50000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <50000>; | |
nvidia,emc-registers = <0x00000003 0x00000007 | |
0x00000003 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x0000009f | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000007 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x000000d0 0x00000000 0x00000000 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x0007c000 0x00000000 0x00000000 0x00000005 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@75000 { | |
reg = <75000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <75000>; | |
nvidia,emc-registers = <0x00000005 0x0000000a | |
0x00000004 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x000000ff | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x0000000b | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000138 0x00000000 0x00000000 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x0007c000 0x00000000 0x00000000 0x00000007 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@150000 { | |
reg = <150000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <150000>; | |
nvidia,emc-registers = <0x00000009 0x00000014 | |
0x00000007 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x0000021f | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000015 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000270 0x00000000 0x00000001 | |
0x00000000 0x00000000 0x00000282 0xa07c04ae | |
0x007e4010 0x00000000 0x00000000 0x0000000e | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@300000 { | |
reg = <300000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <300000>; | |
nvidia,emc-registers = <0x00000012 0x00000027 | |
0x0000000d 0x00000006 0x00000007 0x00000005 | |
0x00000003 0x00000009 0x00000006 0x00000006 | |
0x00000003 0x00000003 0x00000002 0x00000006 | |
0x00000003 0x00000009 0x0000000c 0x0000045f | |
0x00000000 0x00000004 0x00000004 0x00000006 | |
0x00000008 0x00000001 0x0000000e 0x0000002a | |
0x00000003 0x0000000f 0x00000007 0x00000005 | |
0x00000002 0x000004e1 0x00000005 0x00000002 | |
0x00000000 0x00000000 0x00000282 0xe059048b | |
0x007e0010 0x00000000 0x00000000 0x0000001b | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
}; | |
hynix-8gb { | |
nvidia,ram-code = <0x2>; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
emc-table@25000 { | |
reg = <25000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <25000>; | |
nvidia,emc-registers = <0x00000002 0x00000006 | |
0x00000003 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000004 | |
0x00000003 0x00000008 0x0000000b 0x0000004d | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000004 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000068 0x00000000 0x00000003 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x00070000 0x00000000 0x00000000 0x00000003 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@50000 { | |
reg = <50000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <50000>; | |
nvidia,emc-registers = <0x00000003 0x00000007 | |
0x00000003 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x0000009f | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000007 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x000000d0 0x00000000 0x00000000 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x00070000 0x00000000 0x00000000 0x00000005 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@75000 { | |
reg = <75000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <75000>; | |
nvidia,emc-registers = <0x00000005 0x0000000a | |
0x00000004 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x000000ff | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x0000000b | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000138 0x00000000 0x00000000 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x00070000 0x00000000 0x00000000 0x00000007 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@150000 { | |
reg = <150000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <150000>; | |
nvidia,emc-registers = <0x00000009 0x00000014 | |
0x00000007 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x0000021f | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000015 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000270 0x00000000 0x00000001 | |
0x00000000 0x00000000 0x00000282 0xa07c04ae | |
0x007dd010 0x00000000 0x00000000 0x0000000e | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@300000 { | |
reg = <300000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <300000>; | |
nvidia,emc-registers = <0x00000012 0x00000027 | |
0x0000000d 0x00000006 0x00000007 0x00000005 | |
0x00000003 0x00000009 0x00000006 0x00000006 | |
0x00000003 0x00000003 0x00000002 0x00000006 | |
0x00000003 0x00000009 0x0000000c 0x0000045f | |
0x00000000 0x00000004 0x00000004 0x00000006 | |
0x00000008 0x00000001 0x0000000e 0x0000002a | |
0x00000003 0x0000000f 0x00000007 0x00000005 | |
0x00000002 0x000004e1 0x00000005 0x00000002 | |
0x00000000 0x00000000 0x00000282 0xe059048b | |
0x007e2010 0x00000000 0x00000000 0x0000001b | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
}; | |
hynix-4gb { | |
nvidia,ram-code = <0x3>; | |
#address-cells = <1>; | |
#size-cells = <0>; | |
emc-table@25000 { | |
reg = <25000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <25000>; | |
nvidia,emc-registers = <0x00000002 0x00000006 | |
0x00000003 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000004 | |
0x00000003 0x00000008 0x0000000b 0x0000004d | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000004 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000068 0x00000000 0x00000003 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x0007c000 0x00000000 0x00000000 0x00000003 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@50000 { | |
reg = <50000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <50000>; | |
nvidia,emc-registers = <0x00000003 0x00000007 | |
0x00000003 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x0000009f | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000007 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x000000d0 0x00000000 0x00000000 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x0007c000 0x00078000 0x00000000 0x00000005 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@75000 { | |
reg = <75000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <75000>; | |
nvidia,emc-registers = <0x00000005 0x0000000a | |
0x00000004 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x000000ff | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x0000000b | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000138 0x00000000 0x00000000 | |
0x00000000 0x00000000 0x00000282 0xa0ae04ae | |
0x0007c000 0x00000000 0x00000000 0x00000007 | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@150000 { | |
reg = <150000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <150000>; | |
nvidia,emc-registers = <0x00000009 0x00000014 | |
0x00000007 0x00000003 0x00000006 0x00000004 | |
0x00000002 0x00000009 0x00000003 0x00000003 | |
0x00000002 0x00000002 0x00000002 0x00000005 | |
0x00000003 0x00000008 0x0000000b 0x0000021f | |
0x00000000 0x00000003 0x00000003 0x00000003 | |
0x00000008 0x00000001 0x0000000a 0x00000015 | |
0x00000003 0x00000008 0x00000004 0x00000006 | |
0x00000002 0x00000270 0x00000000 0x00000001 | |
0x00000000 0x00000000 0x00000282 0xa07c04ae | |
0x007e4010 0x00000000 0x00000000 0x0000000e | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
emc-table@300000 { | |
reg = <300000>; | |
compatible = "nvidia,tegra20-emc-table"; | |
clock-frequency = <300000>; | |
nvidia,emc-registers = <0x00000012 0x00000027 | |
0x0000000d 0x00000006 0x00000007 0x00000005 | |
0x00000003 0x00000009 0x00000006 0x00000006 | |
0x00000003 0x00000003 0x00000002 0x00000006 | |
0x00000003 0x00000009 0x0000000c 0x0000045f | |
0x00000000 0x00000004 0x00000004 0x00000006 | |
0x00000008 0x00000001 0x0000000e 0x0000002a | |
0x00000003 0x0000000f 0x00000007 0x00000005 | |
0x00000002 0x000004e1 0x00000005 0x00000002 | |
0x00000000 0x00000000 0x00000282 0xe059048b | |
0x007e0010 0x00000000 0x00000000 0x0000001b | |
0x00000000 0x00000000 0x00000000 0x00000000>; | |
}; | |
}; | |
}; | |
}; |
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