Currently the ITM is broken. This is my current setup.
- VSCode with Cortex Debug plugin
- STM32H743
Both .cfg files are put in the project folder so OpenOCD can find them.
Ticket for OpenOCD: https://sourceforge.net/p/openocd/tickets/266/
Currently the ITM is broken. This is my current setup.
Both .cfg files are put in the project folder so OpenOCD can find them.
Ticket for OpenOCD: https://sourceforge.net/p/openocd/tickets/266/
pub fn initialize_system_clocks(rcc: Rcc, vos: VoltageScale, syscfg: &SYSCFG) -> Ccdr { | |
let ccdr = rcc | |
.use_hse(16.mhz()) // XTAL X1 | |
.sys_ck(400.mhz()) | |
.pll1_r_ck(400.mhz()) // for TRACECK | |
.freeze(vos, syscfg); | |
ccdr | |
} | |
/// Enables ITM | |
unsafe fn enable_itm( | |
dbgmcu: &stm32h7xx_hal::stm32::DBGMCU, | |
dcb: &mut cortex_m::peripheral::DCB, | |
itm: &mut cortex_m::peripheral::ITM, | |
swo_frequency: u32, | |
) { | |
// ARMv7-M DEMCR: Set TRCENA. Enables DWT and ITM units | |
//unsafe { *(0xE000_EDFC as *mut u32) |= 1 << 24 }; | |
dcb.enable_trace(); | |
// Ensure debug blocks are clocked before interacting with them | |
dbgmcu.cr.modify(|_, w| { | |
w.d1dbgcken() | |
.set_bit() | |
.d3dbgcken() | |
.set_bit() | |
.traceclken() | |
.set_bit() | |
.dbgsleep_d1() | |
.set_bit() | |
}); | |
// SWO: Unlock | |
*(0x5c00_3fb0 as *mut u32) = 0xC5ACCE55; | |
// SWTF: Unlock | |
*(0x5c00_4fb0 as *mut u32) = 0xC5ACCE55; | |
// SWO CODR Register: Set SWO speed | |
*(0x5c00_3010 as *mut _) = crate::system::clock::get_clocks().c_ck().0 / swo_frequency - 1; | |
// SWO SPPR Register: | |
// 1 = Manchester | |
// 2 = NRZ | |
*(0x5c00_30f0 as *mut _) = 2; | |
// SWTF Trace Funnel: Enable for CM7 | |
*(0x5c00_4000 as *mut u32) |= 1; | |
// ITM: Unlock | |
itm.lar.write(0xC5ACCE55); | |
// ITM Trace Enable Register: Enable lower 8 stimulus ports | |
itm.ter[0].write(1); | |
// ITM Trace Control Register: Enable ITM | |
itm.tcr.write( | |
(0b000001 << 16) | // TraceBusID | |
(1 << 3) | // enable SWO output | |
(1 << 0), // enable the ITM | |
); | |
} |
{ | |
// Use IntelliSense to learn about possible attributes. | |
// Hover to view descriptions of existing attributes. | |
// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 | |
"version": "0.2.0", | |
"configurations": [ | |
{ | |
"type": "cortex-debug", | |
"request": "launch", | |
"servertype": "openocd", | |
"cwd": "${workspaceRoot}", | |
"executable": "./target/thumbv7em-none-eabihf/debug/${workspaceFolderBasename}", | |
"interface": "swd", | |
"name": "Debug", | |
"device": "STM32H743VI", | |
"svdFile": "./STM32H743x.svd", | |
"configFiles": [ | |
"./openocd.cfg" | |
], | |
"preLaunchTask": "Build", | |
"runToMain": true, | |
"swoConfig": { | |
"enabled": true, | |
"cpuFrequency": 400000000, | |
"source": "probe", | |
"swoFrequency": 2000000, | |
"decoders": [ | |
{ "type": "console", "label": "Console", "port": 0, "encoding": "utf8" } | |
] | |
}, | |
"graphConfig": [ | |
] | |
} | |
] | |
} |
source [find interface/stlink.cfg] | |
source [find ./stm32h7x_dual_bank-itm_fix.cfg] |
# This is a custom version of the config that has the ITM fixed. | |
# The official version can be used again when https://sourceforge.net/p/openocd/tickets/266/ has been dealt with. | |
# script for stm32h7x family | |
# | |
# stm32h7 devices support both JTAG and SWD transports. | |
# | |
source [find target/swj-dp.tcl] | |
source [find mem_helper.tcl] | |
if { [info exists CHIPNAME] } { | |
set _CHIPNAME $CHIPNAME | |
} else { | |
set _CHIPNAME stm32h7x | |
} | |
if { [info exists DUAL_BANK] } { | |
set $_CHIPNAME.DUAL_BANK $DUAL_BANK | |
unset DUAL_BANK | |
} else { | |
set $_CHIPNAME.DUAL_BANK 0 | |
} | |
if { [info exists DUAL_CORE] } { | |
set $_CHIPNAME.DUAL_CORE $DUAL_CORE | |
unset DUAL_CORE | |
} else { | |
set $_CHIPNAME.DUAL_CORE 0 | |
} | |
# Issue a warning when hla is used, and fallback to single core configuration | |
if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } { | |
echo "Warning : hla does not support multicore debugging" | |
set $_CHIPNAME.DUAL_CORE 0 | |
} | |
if { [info exists USE_CTI] } { | |
set $_CHIPNAME.USE_CTI $USE_CTI | |
unset USE_CTI | |
} else { | |
set $_CHIPNAME.USE_CTI 0 | |
} | |
# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0 | |
if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } { | |
echo "Warning : could not use CTI with a single core device, CTI is disabled" | |
set $_CHIPNAME.USE_CTI 0 | |
} | |
set _ENDIAN little | |
# Work-area is a space in RAM used for flash programming | |
# By default use 64kB | |
if { [info exists WORKAREASIZE] } { | |
set _WORKAREASIZE $WORKAREASIZE | |
} else { | |
set _WORKAREASIZE 0x10000 | |
} | |
#jtag scan chain | |
if { [info exists CPUTAPID] } { | |
set _CPUTAPID $CPUTAPID | |
} else { | |
if { [using_jtag] } { | |
set _CPUTAPID 0x6ba00477 | |
} { | |
set _CPUTAPID 0x6ba02477 | |
} | |
} | |
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID | |
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu | |
if {[using_jtag]} { | |
swj_newdap $_CHIPNAME bs -irlen 5 | |
} | |
if {![using_hla]} { | |
# STM32H7 provides an APB-AP at access port 2, which allows the access to | |
# the debug and trace features on the system APB System Debug Bus (APB-D). | |
target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 | |
} | |
target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0 | |
$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |
flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0 | |
if {[set $_CHIPNAME.DUAL_BANK]} { | |
flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0 | |
} | |
if {[set $_CHIPNAME.DUAL_CORE]} { | |
target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3 | |
$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 | |
flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1 | |
if {[set $_CHIPNAME.DUAL_BANK]} { | |
flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1 | |
} | |
} | |
# Make sure that cpu0 is selected | |
targets $_CHIPNAME.cpu0 | |
# Clock after reset is HSI at 64 MHz, no need of PLL | |
adapter speed 1800 | |
adapter srst delay 100 | |
if {[using_jtag]} { | |
jtag_ntrst_delay 100 | |
} | |
# use hardware reset | |
# | |
# The STM32H7 does not support connect_assert_srst mode because the AXI is | |
# unavailable while SRST is asserted, and that is used to access the DBGMCU | |
# component at 0x5C001000 in the examine-end event handler. | |
# | |
# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead | |
# of the default AP0, and that works with SRST asserted; however, nonzero AP | |
# usage does not work with HLA, so is not done by default. That change could be | |
# made in a local configuration file if connect_assert_srst mode is needed for | |
# a specific application and a non-HLA adapter is in use. | |
reset_config srst_only srst_nogate | |
if {![using_hla]} { | |
# if srst is not fitted use SYSRESETREQ to | |
# perform a soft reset | |
$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq | |
if {[set $_CHIPNAME.DUAL_CORE]} { | |
$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq | |
} | |
# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal | |
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 | |
# makes the data access cacheable. This allows reading and writing data in the | |
# CPU cache from the debugger, which is far more useful than going straight to | |
# RAM when operating on typical variables, and is generally no worse when | |
# operating on special memory locations. | |
$_CHIPNAME.dap apcsw 0x08000000 0x08000000 | |
} | |
$_CHIPNAME.cpu0 configure -event examine-end { | |
# Enable D3 and D1 DBG clocks | |
# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN | |
stm32h7x_dbgmcu_mmw 0x004 0x00600000 0 | |
# Enable debug during low power modes (uses more power) | |
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains | |
stm32h7x_dbgmcu_mmw 0x004 0x00000007 0 | |
# Stop watchdog counters during halt | |
# DBGMCU_APB3FZ1 |= WWDG1 | |
stm32h7x_dbgmcu_mmw 0x034 0x00000040 0 | |
# DBGMCU_APB1LFZ1 |= WWDG2 | |
stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0 | |
# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2 | |
stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0 | |
} | |
$_CHIPNAME.cpu0 configure -event trace-config { | |
# Set TRACECLKEN; TRACE_MODE is set to async; when using sync | |
# change this value accordingly to configure trace pins | |
# assignment | |
stm32h7x_dbgmcu_mmw 0x004 0x00100000 0 | |
} | |
$_CHIPNAME.cpu0 configure -event reset-init { | |
# Clock after reset is HSI at 64 MHz, no need of PLL | |
adapter speed 4000 | |
} | |
if {[set $_CHIPNAME.DUAL_CORE]} { | |
$_CHIPNAME.cpu1 configure -event examine-end { | |
# get _CHIPNAME from the current target | |
set _CHIPNAME [regsub ".cpu\\d$" [target current] ""] | |
global $_CHIPNAME.USE_CTI | |
# Stop watchdog counters during halt | |
# DBGMCU_APB3FZ2 |= WWDG1 | |
stm32h7x_dbgmcu_mmw 0x038 0x00000040 0 | |
# DBGMCU_APB1LFZ2 |= WWDG2 | |
stm32h7x_dbgmcu_mmw 0x040 0x00000800 0 | |
# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2 | |
stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0 | |
if {[set $_CHIPNAME.USE_CTI]} { | |
stm32h7x_cti_start | |
} | |
} | |
} | |
# like mrw, but with target selection | |
proc stm32h7x_mrw {used_target reg} { | |
set value "" | |
$used_target mem2array value 32 $reg 1 | |
return $value(0) | |
} | |
# like mmw, but with target selection | |
proc stm32h7x_mmw {used_target reg setbits clearbits} { | |
set old [stm32h7x_mrw $used_target $reg] | |
set new [expr ($old & ~$clearbits) | $setbits] | |
$used_target mww $reg $new | |
} | |
# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base | |
# this procedure will use the mem_ap on AP2 whenever possible | |
proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} { | |
# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address | |
if {![using_hla]} { | |
# get _CHIPNAME from the current target | |
set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""] | |
set used_target $_CHIPNAME.ap2 | |
set reg_addr [expr 0xE00E1000 + $reg_offset] | |
} { | |
set used_target [target current] | |
set reg_addr [expr 0x5C001000 + $reg_offset] | |
} | |
stm32h7x_mmw $used_target $reg_addr $setbits $clearbits | |
} | |
if {[set $_CHIPNAME.USE_CTI]} { | |
# create CTI instances for both cores | |
cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000 | |
cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000 | |
$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all } | |
$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all } | |
$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all } | |
$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all } | |
proc stm32h7x_cti_start {} { | |
# get _CHIPNAME from the current target | |
set _CHIPNAME [regsub ".cpu\\d$" [target current] ""] | |
# Configure Cores' CTIs to halt each other | |
# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0 | |
$_CHIPNAME.cti0 write INEN0 0x1 | |
$_CHIPNAME.cti0 write OUTEN0 0x1 | |
$_CHIPNAME.cti1 write INEN0 0x1 | |
$_CHIPNAME.cti1 write OUTEN0 0x1 | |
# enable CTIs | |
$_CHIPNAME.cti0 enable on | |
$_CHIPNAME.cti1 enable on | |
} | |
proc stm32h7x_cti_stop {} { | |
# get _CHIPNAME from the current target | |
set _CHIPNAME [regsub ".cpu\\d$" [target current] ""] | |
$_CHIPNAME.cti0 enable off | |
$_CHIPNAME.cti1 enable off | |
} | |
proc stm32h7x_cti_prepare_restart_all {} { | |
stm32h7x_cti_prepare_restart cti0 | |
stm32h7x_cti_prepare_restart cti1 | |
} | |
proc stm32h7x_cti_prepare_restart {cti} { | |
# get _CHIPNAME from the current target | |
set _CHIPNAME [regsub ".cpu\\d$" [target current] ""] | |
# Acknowlodge EDBGRQ at TRIGOUT0 | |
$_CHIPNAME.$cti write INACK 0x01 | |
$_CHIPNAME.$cti write INACK 0x00 | |
} | |
} |
# script for stm32h7x family (dual flash bank) | |
# STM32H7xxxI 2Mo have a dual bank flash. | |
set DUAL_BANK 1 | |
source [find ./stm32h7x-itm_fix.cfg] |