VHDL stuff

VHDL

Some VHDL stuff

8bit_full_adder.vhd

-- 8bit_full_adder
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity eight_bit_full_adder is
port(
  Cin: in std_logic;
  A: in std_logic_vector(7 downto 0);
  B: in std_logic_vector(7 downto 0);
  S: out std_logic_vector(7 downto 0);
  Cout: out std_logic);
end eight_bit_full_adder;

architecture comportamento of eight_bit_full_adder is
begin
  process(Cin, A, B) is
  variable A9, S9: std_logic_vector(8 downto 0);
  begin
    A9(7 downto 0) := A;
    A9(8) := '0';
    S9 := A9 + B + Cin;
    S <= S9(7 downto 0);
    Cout <= S9(8);
  end process;
end comportamento;

8bit_multiplier.vhd

-- 8bit_multiplier
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity multiplier is
port(
  A: in std_logic_vector(7 downto 0);
  B: in std_logic_vector(7 downto 0);
  M: out std_logic_vector(15 downto 0));
end multiplier;

architecture comportamento of multiplier is
begin
  process(A, B) is
  variable A16, B16: std_logic_vector(15 downto 0);
  begin
    A16(7 downto 0) := A;
    A16(15 downto 8) := "00000000";
    B16(7 downto 0) := B;
    B16(15 downto 8) := "00000000";
    M <= A16 * B16;
  end process;
end comportamento;

full_adder.vhd

-- Simple full_adder design
library IEEE;
use IEEE.std_logic_1164.all;
 
entity full_adder is
port(
  Cin: in std_logic;
  A: in std_logic;
  B: in std_logic;
  S: out std_logic;
  Cout: out std_logic);
end full_adder;
 
architecture comportamento of full_adder is
begin
  process(Cin, A, B) is
  variable AxorB: std_logic;
  begin
    AxorB := A xor B;
    S <= Cin xor AxorB;
    Cout <= (A and B) or (Cin and AxorB);
  end process;
end comportamento;

testbench_model.vhd

-- Testbench for 8bit_full_adder
library IEEE;
use IEEE.std_logic_1164.all;
 
entity testbench is
-- empty
end testbench; 
 
architecture tb of testbench is
 
-- DUT component
component to_test is
PORTS;
end component;
 
SIGNALS;
 
begin
 
  -- Connect DUT
  DUT: to_test port map(SIGNALS);
 
  process
  begin
    SIGNALS;
    wait for 1 ns;
    assert(SOMETHING) report "SOMETHING" severity error;
    
    -- Clear inputs
 
    assert false report "Test done." severity note;
    wait;
  end process;
end tb;