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March 21, 2019 00:05
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synth.tcl
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Here is what I'm using: | |
common-setup.tcl: | |
Name of top-level design | |
set DESIGN_NAME "mips32" | |
# Set Design Path | |
set DESIGN_PATH [file normalize ~/cad/mips32] | |
# Aboslute path prefix variable for library/design data. Use this variable to | |
# prefix the common absolute path to the common variables defined | |
# below. Absolute paths are mandatory are mandary for heirarchical RM flow. | |
set DESIGN_REF_DATA_PATH "${DESIGN_PATH}/ref" | |
# List of hierarchical block design names "DesignA DesignB" ... | |
set HIERARCHICAL_DESIGNS "" | |
# List of hierarchical block cell instance names "u_DesignA u_DesignB" ... | |
set HIERARCHICAL_CELLS "" | |
# Additional search path to be added to the default search path | |
set ADDITIONAL_SEARCH_PATH "${DESIGN_PATH} \ | |
${DESIGN_REF_DATA_PATH}/icons \ | |
${DESIGN_REF_DATA_PATH}/itf \ | |
${DESIGN_REF_DATA_PATH}/models \ | |
${DESIGN_REF_DATA_PATH}/plib \ | |
${DESIGN_REF_DATA_PATH}/tech \ | |
${DESIGN_REF_DATA_PATH}/tluplus" | |
# Target libraries | |
set TARGET_LIBRARY_FILES "saed90nm_typ.db" | |
# Symbol library | |
set SYMBOL_LIBRARY_FILES "saed90nm.sdb" | |
# Extra link logical libraries not included in TARGET_LIBRARY_FILES | |
set ADDITIONAL_LINK_LIB_FILES "" | |
# List of max/min library pairs | |
set MIN_LIBRARY_FILES "saed90nm_max.db saed90nm_min.db" | |
# Milkyway refere libraries (include IC compiler ILMs here) | |
set MW_REFERENCE_LIB_DIRS "${DESIGN_REF_DATA_PATH}/saed90nm_fr" | |
# Reference control file to define the MW reference libraries | |
set MW_REFERENCE_CONTROL_FILE "" | |
# Milkyway technology file | |
set TECH_FILE "${DESIGN_REF_DATA_PATH}/tech/saed90nm.tf" | |
# Mapping file for TLUplus | |
set MAP_FILE "saed90nm.map" | |
# Max/Min TLUplus file | |
set TLUPLUS_MAX_FILE "saed90nm_1p9m_1t_Cmax.tluplus" | |
set TLUPLUS_MIN_FILE "saed90nm_1p9m_1t_Cmin.tluplus" | |
# Names for power/ground nets | |
set MW_POWER_NET "VDD" | |
set MW_POWER_PORT "VDD" | |
set MW_GROUND_NET "VSS" | |
set MW_GROUND_PORT "VSS" | |
# Min/Max routing layer | |
set MIN_ROUTING_LAYER "" | |
set MAX_ROUTING_LAYER "" | |
# Tcl file with library modificatiosn for don't use | |
set LIBRARY_DONT_USE_FILE "" | |
# Multi-Voltage Common Variables | |
# | |
# Define the following MV common variables for the RM scripts for multi-voltage | |
# flows. Use as few or as many of the following definitions as needed by your | |
# design. | |
set PD1 "" ;# Name of power domain/voltage area 1 | |
set PD1_CELLS "" ;# Instances to include in power domain/voltage area 1 | |
set VA1_COORDINATES {} ;# Coordinates for voltage area 1 | |
set MW_POWER_NET1 "VDD1" ;# Power net for voltage area 1 | |
set MW_POWER_PORT1 "VDD" ;# Power port for voltage area 1 | |
set PD2 "" ;# Name of power domain/voltage area 2 | |
set PD2_CELLS "" ;# Instances to include in power domain/voltage area 2 | |
set VA2_COORDINATES {} ;# Coordinates for voltage area 2 | |
set MW_POWER_NET2 "VDD2" ;# Power net for voltage area 2 | |
set MW_POWER_PORT2 "VDD" ;# Power port for voltage area 2 | |
dc-setup.tcl | |
# Source the file that is common to ALL Synopsys tools to setup commmon variables | |
source common-setup.tcl | |
# Setup variables: Portions of the dc_setup.tcl may be used by other tools, so | |
# do check for DC only commands | |
if {$synopsys_program_name == "dc_shell"} { | |
# Change alib_library_analysis_path to point to a centeral cache of analyzed | |
# libraries to save some runtime and disk space. The following setting only | |
# reflects the default value and shoudl be changed to a central location for | |
# best results. | |
set alib_library_analysis_path . | |
# Add any other DC variables here | |
} | |
# List of source files to read if reading from RTL | |
set RTL_SOURCE_FILES "${DESIGN_PATH}/src/mips32.v"; | |
# The following directories are created and used by DC scripts to direct the | |
# location of the output files | |
set REPORTS_DIR "syn-reports" | |
set RESULTS_DIR "syn-results" | |
set LOG "syn-log" | |
file mkdir ${REPORTS_DIR} | |
file mkdir ${RESULTS_DIR} | |
file mkdir ${LOG} | |
# Library Setup: Define all the library variables shared by all the front-end | |
# tools. It is designed to work with the settings in common-setup.tcl without | |
# any additional modification. | |
set search_path ". ${DESIGN_PATH}/synopsys/syn \ | |
${DESIGN_PATH}/synopsys/syn/dc \ | |
${ADDITIONAL_SEARCH_PATH} $search_path" | |
# Milkyway variable settings: make sure to define the variables mw_logic1_net, | |
# mw_logic0_net and mw_design_library as they are need by write_milkway command. | |
set mw_logic1_net ${MW_POWER_NET} | |
set mw_logic0_net ${MW_GROUND_NET} | |
set mw_reference_library ${MW_REFERENCE_LIB_DIRS} | |
set mw_design_library ${DESIGN_NAME}_lib | |
set mw_site_name_mapping [list CORE unit Core unit core unit] | |
# The remainder of the seutp should only be performed in Design Compiler | |
if {$synopsys_program_name == "dc_shell"} { | |
# Include all libraries for multi-Vth leakage power optimization | |
set target_library ${TARGET_LIBRARY_FILES} | |
set symbol_library ${SYMBOL_LIBRARY_FILES} | |
set synthetic_library dw_foundation.sldb | |
set link_library "* $target_library $ADDITIONAL_LINK_LIB_FILES $synthetic_library" | |
# Set min libraries if they exist | |
foreach {max_library min_library} $MIN_LIBRARY_FILES { | |
set_min_library $max_library -min_version $min_library | |
} | |
# If in topological mode, create/open milkway library and setup TLU+ files for | |
# RC extraction | |
if {[shell_is_in_topographical_mode]} { | |
# Only create new Milkyway design library if it doesn't already exist | |
if {![file isdirectory $mw_design_library]} { | |
create_mw_lib -technology $TECH_FILE \ | |
-mw_reference_library $mw_reference_library $mw_design_library \ | |
-hier_separator {/} | |
} else { | |
# If Milkyway design library already exists, ensure that is consistent with | |
# specified Milkyway reference libraries | |
set_mw_lib_reference $mw_design_library -mw_reference_library $mw_reference_library | |
} | |
open_mw_lib $mw_design_library | |
check_library | |
set_tlu_plus_file -max_tluplus $TLUPLUS_MAX_FILE \ | |
-min_tluplus $TLUPLUS_MIN_FILE \ | |
-tech2itf_map $MAP_FILE | |
check_tlu_plus_files | |
} | |
# Library modifications: Apply library modifications here after the | |
# libraries are loaded. | |
if {[file exists [which ${LIBRARY_DONT_USE_FILE}]]} { | |
source -echo ${LIBRARY_DONT_USE_FILE} | |
} | |
} | |
dc.tcl: | |
# Timestamp | |
sh date | |
# Apply the dc-setup.tcl to setup libraries, paths, variables, etc | |
source ./dc/dc-setup.tcl | |
# Synopsys auto setup mode | |
set synopsys_auto_setup true | |
# Note: The Synopsys Auto Setup mode is less conservative than the Formality | |
# default mode, and is more likely to result in a successful verification | |
# out-of-the-box. | |
# | |
# Using the Setting this variable will change the default values of the variables | |
# listed here below. You may change any of these variables back to their default | |
# settings to be more conservative. Uncomment the appropriate lines below to | |
# revert back to their default settings: | |
# set hdlin_ignore_parallel_case true | |
# set hdlin_ignore_full_case true | |
# set verification_verify_directly_undriven_output true | |
# set hdlin_ignore_embedded_configuration false | |
# set svf_ignore_unqualified_fsm_information true | |
# Other variables with changed default values are described in the next few sections. | |
# The Synopsys Auto Setup mode sets undriven signals in the reference design to "0" similar to DC. | |
# Undriven signals in the implementation design are set to "X". | |
# Uncomment the next line to revert back to the more conservative default setting: | |
set verification_set_undriven_signals BINARY:X | |
# The Synopsys Auto Setup mode will produce warning messages, not error messages, | |
# when Formality encounters potential differences between simulation and synthesis. | |
# Uncomment the next line to revert back to the more conservative default setting: | |
set hdlin_error_on_mismatch_message true | |
# The Synopsys Auto Setup mode, along with the SVF file, will appropriately | |
# set the clock-gating variable. Otherwise, the user will need to notify | |
# Formality of clock-gating by uncommenting the next line: | |
# set verification_clock_gate_hold_mode any | |
# Set this variable ONLY if your design contains instantiated DW or function-inferred DW | |
# set hdlin_dwroot "" ;# Enter the pathname to the top-level of the DC tree | |
# If the design has missing blocks or missing components in both the | |
# reference and implementation designs, uncomment the following variable | |
# so that Formality can complete linking each design: | |
# set hdlin_unresolved_modules black_box | |
# Set SVF file to read | |
set_svf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.svf | |
# Read in libraries | |
foreach tech_lib "${TARGET_LIBRARY_FILES} ${ADDITIONAL_LINK_LIB_FILES}" { | |
read_db -technology_library $tech_lib | |
} | |
# Read in the reference (original) design as verilog/vhdl source | |
read_verilog -r ${RTL_SOURCE_FILES} -work_library WORK | |
# Set reference design | |
set_top r:/WORK/${DESIGN_NAME} | |
# Read in the mapped design | |
# For verilog | |
# read_verilog -i ${RESULTS_DIR}/${DESIGN_NAME}.mapped.v | |
# For DDC | |
read_ddc -i ${RESULTS_DIR}/${DESIGN_NAME}.mapped.ddc | |
# Or Milkyway | |
# read_milkyway -i -libname ${mw_design_library} -cell_name ${DESIGN_NAME}_DCT ${mw_reference_library} | |
# Set implementation design | |
set_top i:/WORK/${DESIGN_NAME} | |
# Or for Milkyway | |
# set_top i:/${mw_design_library}/${DESIGN_NAME} | |
# Configure constant ports. When using the Synopsys Auto Setup mode, | |
# the SVF file will convey information automatically to Formality about | |
# how to disable scan. | |
# | |
# Otherwise, manually define those ports whose inputs should be assumed constant | |
# during verification. | |
# | |
# Example command format: | |
# | |
# set_constant -type port i:/WORK/$DESIGN_NAME/<port_name> <constant_value> | |
# Match compare points and report unmatched points | |
match | |
report_unmatched_points > ${REPORTS_DIR}/${DESIGN_NAME}.fmv_unmatched_points.rpt | |
# Verify and report | |
if {![verify]} { | |
save_session -replace ${REPORTS_DIR}/${DESIGN_NAME} | |
report_failing_points > ${REPORTS_DIR}/${DESIGN_NAME}.fmv_failing_points.rpt | |
report_aborted > ${REPORTS_DIR}/${DESIGN_NAME}.fmv_aborted_points.rpt | |
} | |
# Timestamp | |
sh date | |
# Terminate | |
exit | |
mips32.s0.tcl: (constraints) | |
echo "** LOG(mips32.s0.tcl): SCENARIO (S0)" | |
set PERIOD 10 ;# 10 ns clock period -> 100 MHz max | |
set INPUT_DELAY 1.0 | |
set OUTPUT_DELAY 1.0 | |
set CLOCK_LATENCY 1.5 | |
set MIN_TO_DELAY 1.0 | |
set MAX_TRANSITION 0.5 | |
# Preserve all heirarchy (set to true when RTL is in development) | |
set NO_UNGROUP false | |
echo "** LOG(mips32.s0.tcl): S0 PERIOD: ${PERIOD}" | |
# Clock basics | |
# Set clk period | |
create_clock -name "clk" -period $PERIOD [get_port clk] | |
# Set clk latency: time it takes for clk signal to get from source to FF sync pin. | |
set_clock_latency $CLOCK_LATENCY [get_clocks clk] | |
# Set clk uncertainity (jitter/skew): maximum time difference between two pins on | |
# a chip receiving the same clk signal | |
set_clock_uncertainty 0.3 [get_clocks clk] | |
# Set clk transition: time for clk to go 0->1 or 1->0 | |
set_clock_transition 0.4 [get_clocks clk] | |
# Grouping clk/inputs/outputs for better optimization | |
group_path -name CLK -to clk | |
group_path -name INPUTS -through [all_inputs] | |
group_path -name OUTPUTS -to [all_outputs] | |
# Set I/O names | |
set INPUTPORTS [remove_from_collection [all_inputs] [get_ports clk]] | |
set OUTPUTPORTS [all_outputs] | |
# Set delay constraints on I/O boundaries | |
set_input_delay -clock "clk" -max $INPUT_DELAY $INPUTPORTS | |
set_input_delay -clock "clk" -min $MIN_TO_DELAY $INPUTPORTS | |
set_output_delay -clock "clk" -max $OUTPUT_DELAY $OUTPUTPORTS | |
set_output_delay -clock "clk" -min $MIN_TO_DELAY $OUTPUTPORTS | |
# Set the load and driving cell | |
set REFLIB [file rootname $TARGET_LIBRARY_FILES] | |
set DFFCELL "DFFARX1" | |
set DFFCELL_IN_PIN "D" | |
set DFFCELL_OUT_PIN "Q" | |
# Set maximum load to be 5X the input capacitance of a DFFARX1 cell | |
set_load [expr 5 * [load_of $REFLIB/$DFFCELL/$DFFCELL_IN_PIN]] [all_outputs] | |
# Set a DFF flip flop as the driving cell for all inputs (pipelined stages) | |
set_driving_cell -library $REFLIB -lib_cell $DFFCELL -pin $DFFCELL_OUT_PIN [all_inputs] | |
# Driving cell does not drive clk so remove it | |
remove_driving_cell [get_ports clk] | |
# Set maximum transition time of any net in design to be 1 ns. | |
set_max_transition $MAX_TRANSITION [current_design] | |
# Set the maximum capacitance on any net in the design to be 1 pF. | |
set_max_capacitance 1.0 [current_design] | |
# Set maximum fanout of any net in the design | |
set_max_fanout 20 [current_design] | |
# Minimize the area | |
set_max_area 0 | |
Added after 45 minutes: | |
# Timestamp | |
sh date | |
# Apply the dc-setup.tcl to setup libraries, paths, variables, etc | |
source ./dc/dc-setup.tcl | |
# Design Compiler Reference Methodology Script for Top-Down Flow | |
# Add any additional variables here | |
# No additional flow variables are being recommended | |
# Setup for Formality verification: SVF should always be written to allow | |
# Formality verification for advanced optimizations | |
set_svf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.svf | |
# Setup SAIF name mapping database: Include an RTL SAIF for better power | |
# optimizaiton and analysis | |
saif_map -start | |
# Read in the RTL design: read in either RTL source files or an elaborated | |
# design (DDC) | |
define_design_lib WORK -path ./work | |
analyze -format verilog ${RTL_SOURCE_FILES} | |
elaborate ${DESIGN_NAME} | |
write -hierarchy -format ddc -output ${RESULTS_DIR}/${DESIGN_NAME}.elab.ddc | |
# OR read an elaborated design from the same release. Using an elaborated design | |
# from an older release will not give best results. | |
# | |
# read_ddc ${DESIGN_NAME}.elab.ddc | |
# current_design ${DESIGN_NAME} | |
# Resolve design/modules references by linking design to logical libraries | |
link | |
# Apply logical design constraints | |
source ${DESIGN_NAME}.s0.tcl | |
# We can enable analysis and optimization for multiple clocks per register. To | |
# use this, we must constrain to remove false interactions between mutually | |
# exclusive clocks. This is needed to prevent unnecesasry analysis that can result | |
# in a significant runtime incrase with this feature enabled. | |
# | |
# For mips32, it is unnecessary since we have a single clock. | |
# set_clock_groups -physically_exlucive | -logically_exclusive | -asynchronous \ | |
# -group {CLKA, CLKB} -group {CLKC, CLKD} | |
# | |
# set timing_enable_multiple_clocks_per_reg true | |
# Apply operating conditions on top level. Set min/max for delay analysis and | |
# typical for normal usage. | |
set_operating_conditions -max WORST \ | |
-max_library [file rootname $max_library] \ | |
-min BEST -min_library [file rootname $min_library] | |
set_operating_conditions TYPICAL | |
# Create default path groups: separating these paths can help improve optimization. | |
# Remove these path group settings if user path graoups have already been defined. | |
set ports_clock_root [get_ports [all_fanout -flat -clock_tree -level 0]] | |
group_path -name REGOUT -to [all_outputs] | |
group_path -name REGIN -from [remove_from_collection [all_inputs] $ports_clock_root] | |
group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_outputs] | |
# Power optimization | |
# Clock gating setup | |
# Default clock_gating_style suits most designs. Change only if necessary. | |
# set_clock_gating_style ... | |
# Clock gate insertion is now performed during compile_ultra -gate_clock | |
# so insert_clock_gating is no longer recommended at this step. | |
# For better timing optimization of enable logic, clock latency for | |
# clock gating cells can be optionally specified. | |
# set_clock_gate_latency -clock <clock_name> -stage <stage_num> \ | |
# -fanout_latency {fo_range1 latency_val1 fo_range2 latency_val2 ...} | |
# Apply power optimization constraints | |
# Include a SAIF file, if possible, for power optimization. If a SAIF file | |
# is not provided, the default toggle rate of 0.1 will be used for propagating | |
# switching activity. | |
# read_saif -auto_map_names -input ${DESIGN_NAME}.saif -instance < DESIGN_INSTANCE > -verbose | |
# Remove set_max_total_power power optimization constraint from scripts in 2008.09 | |
# Enable both of the following settings for total power optimization | |
set_max_leakage_power 0 | |
# set_max_dynamic_power 0 | |
if {[shell_is_in_topographical_mode]} { | |
# Setting power constraints will automatically enable power prediction using clock tree estimation. | |
# If you are not setting any power constraints and you still want to report | |
# correlated power, you can use the following command to turn on power prediction. | |
set_power_prediction true | |
} | |
if {[shell_is_in_topographical_mode]} { | |
# Apply physical desigin constraints | |
# Optional: Floorplan information can be read in here if available. | |
# This is highly recommended for irregular floorplans. | |
# | |
# Floorplan constraints can be extracted from DEF files using | |
# extract_physical_constraints OR provided from Tcl commands. | |
# | |
# DEF is the recommended input format to maximize the use of the latest | |
# floorplan read capabilities of Design Compiler topographical mode. | |
# Specify ignored layers for routing to improve correlation | |
# Use the same ignored layers that will be used during place and route | |
if {${MIN_ROUTING_LAYER} != ""} { | |
set_ignored_layers -min_routing_layer ${MIN_ROUTING_LAYER} | |
} | |
if {${MAX_ROUTING_LAYER} != ""} { | |
set_ignored_layers -max_routing_layer ${MAX_ROUTING_LAYER} | |
} | |
report_ignored_layers | |
# If the macro names change after mapping and writing out the design due to | |
# ungrouping or Verilog change_names renaming, it may be necessary to translate | |
# the names to correspond to the cell names that exist before compile. | |
# During DEF constraint extraction, extract_physical_constraints automatically | |
# matches DEF names back to precompile names in memory using standard matching rules. | |
# Modify fuzzy_query_options if other characters are used for hierarchy separators | |
# or bus names. | |
# set_fuzzy_query_options -hierarchical_separators {/ _ .} \ | |
# -bus_name_notations {[] __ ()} \ | |
# -class {cell pin port net} \ | |
# -show | |
# Note: The -site_row or -pre_route options are not needed to extract this info | |
# from the DEF file. These are extracted automatically and saved in DDC. | |
# Only use these options if you want this info to be included in the | |
# ASCII output from "extract_physical_constraints -output". | |
if {[file exists [which ${DESIGN_NAME}.def]]} { | |
extract_physical_constraints ${DESIGN_NAME}.def | |
} | |
# OR | |
# For Tcl constraints, the name matching feature must be explicitly enabled | |
# and will also use the set_fuzzy_query_options setttings. This should | |
# be turned off after the constraint read in order to minimize runtime. | |
# set fuzzy_matching_enabled true | |
# source -echo -verbose ${DESIGN_NAME}.physical_constraints.tcl | |
# set fuzzy_matching_enabled false | |
# Note: Include the -site_row or -pre_route options with either | |
# write_physical_constraints or report_physical_constraints if you also | |
# want to include these in the ASCII output files. Site rows and pre-routes | |
# are automatically extracted from the DEF and saved in the DDC even if these | |
# options are not specified. | |
# You can save the extracted constraints for fast loading next time. | |
# write_physical_constraints -output ${DESIGN_NAME}.physical_constraints.tcl | |
# Verify that all the desired physical constraints have been applied | |
report_physical_constraints > ${REPORTS_DIR}/${DESIGN_NAME}.physical_constraints.rpt | |
} | |
# Apply additional optimization constraints | |
# Prevent assignment statment in the Verilog netlist | |
set_fix_multiple_port_nets -all -buffer_constants | |
# Insert level-shifters on all clocks | |
set auto_insert_evel_shifters_on_clocks all | |
# Preserve subdesign interfaces | |
# NOTE; when design is matured, we can turn this off so it does heirarchical | |
# optimization by pushing subdesign constants (pins connected to logic 0/1) to | |
# the external environment and optimizing that. | |
#set compile_preserve_subdesign_interfaces true | |
# Write out all unconnected pins in verilog netlist | |
set verilogout_show_unconnected_pins true | |
# Fix hold-time violations on clock by slowing down data signals | |
set_fix_hold [get_clocks clk] | |
# Fix timing violations if not in topographical mode | |
if {![shell_is_in_topographical_mode]} { | |
set compile_top_all_paths true | |
} | |
# Compile the Design | |
# | |
# Recommended Options: | |
# | |
# -scan | |
# -gate_clock | |
# -retime | |
# -timing_high_effort_script | |
# -area_high_effort_script | |
# -congestion | |
# -num_cpus | |
# | |
# Use compile_ultra as your starting point. For test-ready compile, include | |
# the -scan option with the first compile and any subsequent compiles. | |
# | |
# Use -gate_clock to insert clock-gating logic during optimization. This | |
# is now the recommended methodology for clock gating. | |
# | |
# Use -retime to enable adapative retiming optimization for further timing | |
# benefit without any runtime or memory overhead. | |
# | |
# The -timing_high_effort_script or the -area_high_effort_script option | |
# may also be used to try and improve the optimization results at the tradeoff | |
# of some additional runtime. | |
# | |
# The -congestion option (topographical mode only) enables specialized optimizations that | |
# reduce routing related congestion during synthesis and scan compression insertion | |
# with DFT Compiler. Only enable congestion optimization if required. | |
# This option requires a license for Design Compiler Graphical. | |
# | |
# Use -num_cpus to enable multi-core optimization to improve runtime. Note | |
# that this feature has special usage and license requirements. See the following | |
# article for more info: https://solvnet.synopsys.com/retrieve/024947.html | |
if {[shell_is_in_topographical_mode]} { | |
# Use the "-check_only" option of "compile_ultra" to verify that your | |
# libraries and design are complete and that optimization will not fail | |
# in topographical mode. Use the same options as will be used in compile_ultra. | |
compile_ultra -check_only | |
} | |
if {$NO_UNGROUP} { | |
compile_ultra -gate_clock -area_high_effort_script -no_autoungroup -retime | |
} else { | |
compile_ultra -gate_clock -area_high_effort_script -retime | |
} | |
# Write Out Final Design and Reports | |
# | |
# .ddc: Recommended binary format used for subsequent Design Compiler sessions | |
# Milkyway: Recommended binary format for IC Compiler | |
# .v : Verilog netlist for ASCII flow (Formality, PrimeTime, VCS) | |
# .spef: Topographical mode parasitics for PrimeTime | |
# .sdf: SDF backannotated topographical mode timing for PrimeTime | |
# .sdc: SDC constraints for ASCII flow | |
# | |
change_names -rules verilog -hierarchy | |
# Check the design for consistency | |
check_design | |
# Write and close SVF file and make it available for immediate use | |
set_svf off | |
# Write out design | |
write -format ddc -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.ddc | |
write -f verilog -hierarchy -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.v | |
# Write out design data | |
if {[shell_is_in_topographical_mode]} { | |
# Note: Include the -site_row or -pre_route options with write_physical_constraints | |
# if you also want to include these in the ASCII output files. Site rows and pre-routes | |
# are automatically extracted from the DEF and saved in the DDC even if these | |
# options are not specified. | |
write_physical_constraints -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.physical_constraints.tcl | |
# Write parasitics data for static timing analysis | |
write_parasitics -output ${RESULTS_DIR}/${DESIGN_NAME}.mapped.spef | |
# Write SDF back annotation data from DCT placment for static timing analysis | |
write_sdf ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdf | |
# Do not write out net RC info onto SDC | |
set write_sdc_output_lumped_net_capacitance false | |
set write_sdc_output_net_resistance false | |
} | |
write_sdc -nosplit ${RESULTS_DIR}/${DESIGN_NAME}.mapped.sdc | |
# If SAIF is used, write out SAIF name mapping file for PrimeTime-PX | |
saif_map -type ptpx -write_map ${RESULTS_DIR}/${DESIGN_NAME}.mapped.SAIF.namemap | |
# Generate final reports - qor, timing, area, congestion, power, clock gating | |
report_qor > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.qor.rpt | |
report_timing -nworst 10 -transition_time -nets -attributes -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.timing.rpt | |
report_hierarchy -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.hierarchy.rpt | |
report_resources -nosplit -hierarchy > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.resources.rpt | |
report_constraint > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.constraints.rpt | |
if {[shell_is_in_topographical_mode]} { | |
report_area -physical -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.area.rpt | |
# report_congestion (topographical mode only) reports estimated routing related | |
# congestion after topographical mode synthesis. This command requires a | |
# license for Design Compiler Graphical. | |
# report_congestion > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.congestion.rpt | |
} else { | |
report_area -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.area.rpt | |
} | |
# Use SAIF file for power analysis | |
#read_saif -auto_map_names -input ${DESIGN_NAME}.saif -instance < DESIGN_INSTANCE > -verbose | |
report_power -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.power.rpt | |
report_clock_gating -nosplit > ${REPORTS_DIR}/${DESIGN_NAME}.mapped.clock_gating.rpt | |
# Write the shell command script to save current settings | |
write_script -out ${RESULTS_DIR}/${DESIGN_NAME}.script | |
# Write out Milkyway Design for Top-Down Flow | |
# NOTE: This should be the last step in the script | |
if {[shell_is_in_topographical_mode]} { | |
write_milkyway -overwrite -output ${DESIGN_NAME}_DCT | |
} | |
# Timestamp | |
sh date | |
# Terminate | |
exit |
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